Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment of Amendment
Acknowledgment is made of applicant's amendment, filed on 4/17/2026. The changes and remarks disclosed therein have been considered. Claims 3-4 have been cancelled by the amendment. Claims 1, 2, 8, 14, 15 have been amended. New Claims 21-22 have been added. Therefore, claims 1-2, 5-22 remain pending in the application.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 14-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 14 recites the limitation “the charge integration circuit”. There is insufficient antecedent basis for this limitation in the claim, as this is the first recitation. For the purpose of examination, it is assumed that " the charge integration circuit " is instead " a charge integration circuit ".
Claim 15 recites the limitation “a charge integration circuit”. Examiner is not sure whether this “a charge integration circuit” is same or different from “a charge integration circuit” in claim 14, thus render this limitation vague and indefinite. For the purpose of examination, it is assumed that " a charge integration circuit " is instead " the charge integration circuit ".
Claims 16-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, due to their dependency.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 5-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kumar US Patent 11048434 (hereinafter Kumar), in view of Kinyua US Patent 10164653 (Kinyua).
Regarding independent claim 1, Kumar teaches memory device, comprising: a memory array comprising a plurality of rows and a plurality of columns (abstract of Kumar, “…memory circuit includes an array of memory cells addressable with column address and row address…”), wherein each of the plurality of columns comprises a first plurality of memory cells connected to a bit line of a plurality of bitlines (Kumar teaches that memory cells in each column are commonly connected to a corresponding bitline for sensing and compute-in-memory operations);
an Input/Output circuit (sense AMP 144 plus TDC 152 in figure 1A of Kumar, abstract of Kumar, “…CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value…”) connectable to a bitline of the plurality of bitlines of the memory array, wherein the I/O circuit comprises:
a charge integration circuit coupled to the bitline (“charge integration circuit” has been interpreted as circuit accumulating charge/voltage change over time, Kumar teach “charge integration circuit” at the bitline, as multiple cells are activated together, their combined discharge represents the aggregate compute value, the bitline capacitance integrates this current, the discharge time is converted to a digital compute results, therefore, the bitline inherently functions as a charge integration circuit, figure 2D of Kumar teaches voltages vs time discharge curve, figure 2E teaches current behavior (constant current region), [0037] of Kumar, “…When multiple rows are selected together, the charge on the different rows combines to perform the equivalent of the multiplication of each row value, with the values stored in a column, and the accumulation of these partial sums…”, [0070] of Kumar, “…accumulation of voltage on a shared bitline results in accumulation of a time code output of the TDC…”, [0090]/[0108]/[0126] of Kumar),
a comparator (230 in figure 2B of Kumar) coupled to the charge integration circuit, wherein the comparator compares a sensing voltage (VBL in figure 2B of Kumar) from the charge integration circuit with a reference voltage (VREF in figure 2B of Kumar) and provides an output voltage based on the comparison ([0071] of Kumar, “…Comparator 230 receives VBL 212 and VREF 232 as inputs. When VBL 212 reaches VREF 232, comparator 230 will generate signal Stop 214…”, [0068] of Kumar, “…Stop 214 represents a stop signal that determines when latches 218 will sample the input…”) and
a time-to-digital converter (TDC 152 in figure 1A of Kumar, 210 in figure 2B of Kumar, abstract of Kumar, “…TDC circuit to convert a time for discharge of the multiple memory cells to a digital value…”, [0071] of Kumar, “…Start 222 to initiate TDC 210 and Stop 214, which triggers the latch elements of TDC 210 to sample their inputs which receive VBL 212…” ) coupled to the comparator (230 in figure 2B of Kumar), wherein the time-to- digital convertor (210 in figure 2B of Kumar) converts a time associated with the output voltage to a digital value ([0067] of Kumar, “…digital output represents bits of output that correspond to the time it takes to discharge the sampling lines (i.e., VBL 212)…”)
Kumar teaches a memory device including a memory array and sense circuitry configured to sense bitline voltage and convert a discharge time to a digital value using a time-to-digital converter (TDC) (Kumar [0027], [0066]). Kumar further teaches a comparator configured to compared a bitline voltage to a reference voltage ([0071]). Kumar teaches comparator generates an output (STOP signal) defines timing used by the TDC, and thus the time associated with the comparator output is converted to a digital signal. But Kumar does not explicitly teach a dedicated integration circuit.
However, Kinyua teaches in figure 6 a charge integration circuit including a capacitor C1 (610 in figure 6) and current source Idis configured to integrate charge and generate a voltage signal (capacitor is charge/discharge by current, voltage at node Vres represents integrated value), an analog-to-digital conversion architecture in which: an analog voltage signal is processed by an amplifier/comparator to produce an output voltage, the output voltage is converted to a time-domain signal and the time-domain signal is converted to a digital values using a time-to-digital converter (para(20) of Kinyua, “…residue voltage Vres is received as an input by a comparator 516 …”, figure 8 of Kinyua).
Even if Kumar inherently performs accumulation, Kinyua explicitly teaches a dedicated capacitor-based charge integration circuit, and it would have been obvious to implement such explicit circuitry to improve control and performance. It also would have been obvious to one of ordinary skill in the art to modify Kumar’s sense circuitry to employ the known signal processing chain of Kinyua, wherein the comparator output voltage is used to generate a time-domain signal that is converted to a digital value, in order to improve signal robustness, precision, and scalability of analog-to-digital conversion, as taught by Kinyua.
Regarding claim 2, the combination of Kumar and Kinyua teaches the memory device of claim 1, wherein the charge integration circuit provides the sensing voltage based on a decrease of a voltage on the bitline ([0057]/[0069] of Kumar, “…multiple bitcells will be discharged together and the TDC can generate a digital code as an output to represent an amount of time it takes for the bitcells to be discharged to a low voltage reference...”, Kumar ties sensing to bitline discharge)
Regarding claim 5, the combination of Kumar and Kinyua teaches the memory device of claim 1, further comprising a controller (150 in figure 1A of Kumar), wherein the controller is operative to initiate a multiply-accumulate operation ([0041] of Kumar “…Processor 150 receives two inputs and performs one or more computations on the inputs. The inputs are W from the memory, and X to compute a function...”, [0033] of Kumar, “…CIM accelerators targeted for various deep-learning applications perform multiply-accumulate (MAC) operations…”, Kumar teaches control circuit that can activates multiple memory cells simultaneously to initiate compute-in-memory operations that generate the aggregate bitline discharge)
Regarding claim 6, the combination of Kumar and Kinyua teaches the memory device of claim 1, wherein the time-to-digital convertor comprises a first delay circuit, a second delay circuit, and output circuits connected to the first delay circuit and the second delay circuit (Kumar teaches a time-to-digital converter that perform time measurement using internal timing circuitry and digital output logic. A TDC which generates a digital timing code comprising delay circuitry and associate output logic. The use of multiple delay circuits (first and second delay circuits) with output logic is a well-known and obvious implementation choice for TDC structures).
Regarding claim 7, the combination of Kumar and Kinyua teaches the memory device of claim 6, wherein the first delay circuit comprises a first plurality of delay elements connected in series, each of the first plurality of delay elements configured to delay a signal by a first predetermined delay time (Kumar teaches the use a TDC, a series chain of delay elements is a standard and fundamental structure for implementing delay circuitry of a TDC, therefore, configuring each delay element to provide a predetermined delay time is a routine design choice in TDC).
Regarding independent claim 8, the combination of Kumar and Kinyua teaches a method comprising:
sensing a voltage of a bitline (Kumar teaches sensing bitline voltages during compute-in-memory operation, [0044] of Kumar, “…bitline voltage…proportional to product…”);
charging, by a charge integration circuit (“charge integration circuit” has been interpreted as circuit accumulating charge/voltage change over time, Kumar inherently teach “charge integration circuit” at the bitline, Kinyua teaches in figure 6 a charge integration circuit including a capacitor C1 (610 in figure 6) and current source Idis configured to integrate charge and generate a voltage signal, figure 6 of Kinyua, para(20) of Kinyua, “…residue voltage Vres is received as an input by a comparator 516 …”) connected to the bitline, a sensing node based on a decrease of the voltage on the bitline;
comparing, by a comparator (230 in figure 2B of Kumar, or zero-crossing detector (ZCD 334) in Kinyua receiving the sensing node voltage via amplifier 330) coupled to the charge integration circuit (capacitor C1 charge/discharged by current source in figure 6 of Kinyua), a sensing voltage of the sensing node (VBL in figure 2B of Kumar, Vres in figure 5 of Kinyua) with a reference voltage (VREF in figure 2B of Kumar, threshold of ZCD 334 in figure 5 of Kinyua);
providing, by the comparator, an output voltage based on the comparison ([0071] of Kumar, “…Comparator 230 receives VBL 212 and VREF 232 as inputs. When VBL 212 reaches VREF 232, comparator 230 will generate signal Stop 214…”, [0068] of Kumar, “…Stop 214 represents a stop signal that determines when latches 218 will sample the input…”); and
converting, by a time-to-digital converter (TDC 152 in figure 1A of Kumar, 210 in figure 2B of Kumar, abstract of Kumar, “…TDC circuit to convert a time for discharge of the multiple memory cells to a digital value…”, [0071] of Kumar, “…Start 222 to initiate TDC 210 and Stop 214, which triggers the latch elements of TDC 210 to sample their inputs which receive VBL 212…” ) coupled to the comparator, a time associated with the output voltage to a digital value ([0067] of Kumar, “…digital output represents bits of output that correspond to the time it takes to discharge the sampling lines (i.e., VBL 212)…”, Kinyua also discloses converting a time representation derived from a comparison event (e.g., pulse width generated by a zero-crossing detector) into a digital value using time-to-digital conversion circuitry, see figure 8 of Kinyua).
Regarding claim 9, the combination of Kumar and Kinyua teaches the method of claim 8, wherein charging the sensing node comprises charging the sensing node at a first rate till the sensing voltage is pulled to a threshold voltage ([0057] of Kumar, “…multiple bitcells will be discharged together and the TDC can generate a digital code as an output to represent an amount of time it takes for the bitcells to be discharged to a low voltage reference…”, Kumar teaches multi-slope discharge/varying current behavior in figure 2D/[0074], Kinyua teaches controlled charging/discharging using current source, it would have been obvious to control charging rate using known current-controlled integration (Kinyua) to achieve timing behavior).
Regarding claim 10, the combination of Kumar and Kinyua teaches the method of claim 9, wherein charging the sensing node comprises charging the sensing node at a second rate after the sensing voltage is pulled to the threshold voltage (Kumar teaches that after threshold detection, the discharge behavior transitions into the time-measurement phase used by TDC. This transition produces a second effective rate of voltage evolution associated with post-threshold timing measurement).
Regarding claim 11, the combination of Kumar and Kinyua teaches the method of claim 10, wherein the second rate is greater than the first rate (Kumar teaches a rapid timing detection mechanism following threshold crossing that drives TDC input, the post -threshold timing signal transition is faster than the pre-threshold analog discharge behavior, yielding a second rate is greater than the first rate).
Regarding claim 12, the combination of Kumar and Kinyua teaches the method of claim 8, wherein charging the sensing node comprises: charging the sensing node based on discharge rate of a bitline voltage of the bitline ([0057] of Kumar, “…multiple bitcells will be discharged together and the TDC can generate a digital code as an output to represent an amount of time it takes for the bitcells to be discharged to a low voltage reference…”)
Regarding claim 13, the combination of Kumar and Kinyua teaches the method of claim 8, wherein connecting the charge integration circuit to the bitline comprises connecting the charge integration circuit to the bitline through a multiplexer (Figure 1A of Kumar teaches MUX 142 selects bitlines).
Regarding independent claim 14, the combination of Kumar and Kinyua teaches a method comprising:
selecting a multiplexer (Figure 1A of Kumar teaches MUX 142 selects bitlines) of a plurality of multiplexers of a memory device, wherein each of the plurality of multiplexers is associated with a predetermined number of bitlines of the plurality of bitlines;
connecting, by the multiplexer (Figure 1A of Kumar teaches MUX 142 selects bitlines), a bitline of the predetermined number of bitlines associated with the multiplexer to an associated Input/Output circuit (Figure 1A of Kumar teaches MUX 142 selects bitlines);
comparing, by a comparator (230 in figure 2B of Kumar, or zero-crossing detector (ZCD 334) in Kinyua receiving the sensing node voltage via amplifier 330) of the Input/Output circuit coupled to the charge integration circuit (“charge integration circuit” has been interpreted as circuit accumulating charge/voltage change over time, Kumar inherently teach “charge integration circuit” at the bitline, Kinyua teaches in figure 6 a charge integration circuit including a capacitor C1 (610 in figure 6) and current source Idis configured to integrate charge and generate a voltage signal, figure 6 of Kinyua, para(20) of Kinyua, “…residue voltage Vres is received as an input by a comparator 516 …”), a sensing voltage of a sensing node (VBL in figure 2B of Kumar, Vres in figure 5 of Kinyua) with a reference voltage (VREF in figure 2B of Kumar, threshold of ZCD 334 in figure 5 of Kinyua);
providing, by the comparator, an output voltage based on the comparison ([0071] of Kumar, “…Comparator 230 receives VBL 212 and VREF 232 as inputs. When VBL 212 reaches VREF 232, comparator 230 will generate signal Stop 214…”, [0068] of Kumar, “…Stop 214 represents a stop signal that determines when latches 218 will sample the input…”); and
converting, by a time-to-digital converter (TDC 152 in figure 1A of Kumar, 210 in figure 2B of Kumar, abstract of Kumar, “…TDC circuit to convert a time for discharge of the multiple memory cells to a digital value…”, [0071] of Kumar, “…Start 222 to initiate TDC 210 and Stop 214, which triggers the latch elements of TDC 210 to sample their inputs which receive VBL 212…” ) of the Input/Output circuit connected to the comparator, in a time associated with the output voltage to a digital value ([0067] of Kumar, “…digital output represents bits of output that correspond to the time it takes to discharge the sampling lines (i.e., VBL 212)…”, Kinyua also discloses converting a time representation derived from a comparison event (e.g., pulse width generated by a zero-crossing detector) into a digital value using time-to-digital conversion circuitry, see figure 8 of Kinyua).
Regarding claim 15, the combination of Kumar and Kinyua teaches the method of claim 14, further comprising
charging, by a charge integration circuit (“charge integration circuit” has been interpreted as circuit accumulating charge/voltage change over time, Kumar inherently teach “charge integration circuit” at the bitline, Kinyua teaches in figure 6 a charge integration circuit including a capacitor C1 (610 in figure 6) and current source Idis configured to integrate charge and generate a voltage signal, figure 6 of Kinyua, para(20) of Kinyua, “…residue voltage Vres is received as an input by a comparator 516 …”), the sensing node based on a decrease of the voltage on the bitline.
Regarding claim 16, the combination of Kumar and Kinyua teaches the method of claim 15, wherein charging the sensing node comprises charging the sensing node at a first rate till the sensing voltage is pulled to a threshold voltage ([0057] of Kumar, “…multiple bitcells will be discharged together and the TDC can generate a digital code as an output to represent an amount of time it takes for the bitcells to be discharged to a low voltage reference…”, Kumar teaches multi-slope discharge/varying current behavior in figure 2D/[0074], Kinyua teaches controlled charging/discharging using current source, it would have been obvious to control charging rate using known current-controlled integration (Kinyua) to achieve timing behavior).
Regarding claim 17, the combination of Kumar and Kinyua teaches the method of claim 16, wherein charging the sensing node comprises charging the sensing node at a second rate after the sensing voltage is pulled to the threshold voltage( Kumar teaches that after threshold detection, the discharge behavior transitions into the time-measurement phase used by TDC. This transition produces a second effective rate of voltage evolution associated with post-threshold timing measurement).
Regarding claim 18, the combination of Kumar and Kinyua teaches the method of claim 17, wherein the second rate is greater than the first rate( Kumar teaches a rapid timing detection mechanism following threshold crossing that drives TDC input, the post -threshold timing signal transition is faster than the pre-threshold analog discharge behavior, yielding a second rate is greater than the first rate).
Regarding claim 19, the combination of Kumar and Kinyua teaches the method of claim 15, wherein charging the sensing node comprises: charging the sensing node based on discharge rate of a bitline voltage of the bitline ([0057] of Kumar, “…multiple bitcells will be discharged together and the TDC can generate a digital code as an output to represent an amount of time it takes for the bitcells to be discharged to a low voltage reference…”)
Regarding claim 20, the combination of Kumar and Kinyua teaches the method of claim 15, wherein connecting the charge integration circuit to the bitline comprises connecting the charge integration circuit to the bitline through a multiplexer (Figure 1A of Kumar teaches MUX 142 selects bitlines).
Regarding claim 21, the combination of Kumar and Kinyua teaches the memory device of claim 1, wherein the charge integration circuit (“charge integration circuit” has been interpreted as circuit accumulating charge/voltage change over time, Kumar inherently teach “charge integration circuit” at the bitline, Kinyua teaches in figure 6 a charge integration circuit including a capacitor C1 (610 in figure 6) and current source Idis configured to integrate charge and generate a voltage signal, figure 6 of Kinyua, para(20) of Kinyua, “…residue voltage Vres is received as an input by a comparator 516 …”) comprises a charge circuit (the charge circuit is provided by the current source Idis and switching device that selectively connects the current source to capacitor C1 (figure 6 of Kinyua), thereby charging/discharging the sensing node (Vres) at a controlled rate) connected to a sensing node (Vres in figure 6 of Kinyua), wherein the charge circuit charges the sensing node at a first rate (figure 6 and para(22), “…constant discharge current I.sub.DIS to discharge the capacitor 610, thus inputting the residue voltage Vres to the input of the amplifier 330…”), and wherein the sensing node provides the sensing voltage.
Regarding claim 22, the combination of Kumar and Kinyua teaches the memory device of claim 21, wherein the charge integration circuit further comprises a feedback circuit connected to the sensing node, wherein the feedback circuit charges the sensing node at a second rate (Kinyua teaches a control architecture in which the sensing node voltage (Vres) is processed by an amplifier (330) and a zero-crossing detector (ZCD334), and the resulting comparison event is used by control logic (530) to control switching circuitry (e.g., switching device 332 and switches 521-524) that regulates the charging and discharging paths of the sensing node. This configuration forms a feedback mechanism, as the sensed voltage at the sensing node influences the operation of the switching network, which in turn controls the current applied to the sensing node. Through this feedback-controlled switching, Kinyua enables different effective charging and discharging behavior of sensing node, including providing different charging rates depending on circuit state. Accordingly, the control logic and switching circuitry of Kinyua constitute a feedback circuit connected to the sensing node that changes the sensing node at a second rate, para (22) of Kinyua, “…switching device 332 connects the capacitor 610 to the constant discharge current I.sub.DIS to discharge the capacitor 610 …”, multiple switching paths and capacitive elements in Kinyua provide different effective charging/discharging rates, by altering the current path and magnitude applied to the sensing node through the switching circuitry, the circuitry provides a second effective charging rate distinct from a first charging rate).
Response to Arguments
Applicant argument:
Kumar does not teach a comparator coupled to a charge integration circuit…
Response:
This argument is not persuasive.
Kumar does disclose a comparator and comparison operation (figure 2 and [0071], “…Comparator 230 receives VBL 212 and VREF 232 as inputs…”)
Applicant’s argument focuses on the absence of a “charge integration circuit” in Kumar.
The examiner acknowledges that Kumar does not explicitly label a discrete “charge integration circuit”. However, Kumar discloses current accumulation and charge accumulation on a bitline ([0044]/[0070]/[0108], which inherently performs integration of charge. Furthermore, the rejection relies on Kinyua to teach the claimed integration structure. Kinyua explicitly teaches a charge integration circuit including capacitor C1, current source Idis, and sensing node Vres. Additionaly, Kinyua teaches a comparator (zero-crossing detector 334), couples to the sensing node via amplifier 330. Thus the comparator is couples (directly or indirectly via amplification) to the charge integration circuit.
Applicant argument:
Kumar does not teach converting a time associated with the output voltage to a digital value…
Response:
Kumar explicitly teaches this limitation. Kumar teaches in abstract/[0052]/[0070] “TDC circuit to convert a time for discharge of the multiple memory cells to a digital value, further teaches in [0071] that comparator output (STOP signal) defines timing used by TDC. The STOP signal generated by the comparator is a voltage/time event that directly controls the TDC sampling operation, and thus time is associated with comparator output, and time is converted to digital value.
Applicant argument:
Kumar merely discloses CIM sensing and does not teach claimed structure…
Response:
This argument is not persuasive.
Kumar discloses more than generic sensing, Kumar teaches multi-cell current summation, accumulation on bitline, comparator threshold detection, and time-domain conversion via TDC. This is functionally identical to the claimed sensing /comparison and time conversion chain.
Applicant argument:
Lee does not sure Kumar’s deficiency…
Response:
Lee is no longer used. The rejection is now based on Kumar in view of Kinyua.
Applicant argument:
Combination would not lead to claimed subject matter
Response:
This argument is not persuasive.
The combination is straightforward and predictable, Kumar teaches performing sensing /comparison, and time encoding, while Kinyua provides explicit integration circuit prior to comparison.
The motivation to combine Kumar with Kinyua is to improve control, and noise immunity of the sensed signal prior to comparison.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/XIAOCHUN L CHEN/ Primary Examiner, Art Unit 2824
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