DETAILED ACTION
General Remarks
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
4. Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
5. Applicants seeking an interview with the examiner, including WebEx Video Conferencing, are encouraged to fill out the online Automated Interview Request (AIR) form
(http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html). See MPEP §502.03, §713.01(11) and Interview Practice for additional details.
6. Status of claim(s) to be treated in this office action:
a. Independent: 1, 8 and 14.
b. Pending: 1-20.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claims 1, 8, 14 recite, “senses a multiply-accumulate value for the bitline in a time domain”. However, claims and specification does not clearly describe, what exact multiplication is performed, what exact accumulation is performed, over what number of memory cells, how the multiplication mathematically occurs, therefore, instant application does not reasonably convey possession of a true MAC operation, as opposed to merely bitline voltage sensing and/or generalized charge accumulation.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 8, 14 recites, “multiple-accumulate value”, this term is not defined in specification, it is unclear what is being multiplied, whether time is proportional to product, or sum or product-sum, this renders this limitation vague and indefinite.
Rest of claims are also rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph and under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph due to their dependency on independent claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kumar US Patent 11048434 (hereinafter Kumar).
Regarding independent claim 1, Kumar teaches a memory device (title), comprising:
a memory array (figure 1 of Kumar) comprising a plurality of rows and a plurality of columns (abstract, “…memory circuit includes an array of memory cells addressable with column address and row address…”), wherein each of the plurality of columns comprises a first plurality of memory cells connected to a bit line of a plurality of bitlines (Kumar teaches that memory cells in each column are commonly connected to a corresponding bitline for sensing and compute-in-memory operations);
an Input/Output circuit (sense AMP 144 plus TDC 152 in figure 1A of Kumar) connectable to a bitline of the plurality of bitlines of the memory array, wherein the I/O circuit comprises: a charge integration circuit coupled to the bitline (Kumar inherently teach “charge integration circuit” at the bitline, as multiple cells are activated together, their combined discharge represents the aggregate compute value, the bitline capacitance integrates this current, the discharge time is converted to a digital compute results, therefore, the bitline inherently functions as a charge integration circuit), a comparator coupled to the charge integration circuit, and a time-to-digital converter (TDC 152 in figure 1A of Kumar) coupled to the comparator (a TDC cannot operate without a threshold detection event, which is functionally a comparator, Kumar teaches in Abstract “CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value”, therefore, Kumar needs detection of a timing of a discharge event, that time is used as the start/stop signal for the TDC, that threshold-crossing detection, by circuit definition, is a comparator, see 230 in figure 2B), wherein the the I/O circuit senses a multiply-accumulate value for the bitline in a time domain (para (23)/(26), “…memory circuit includes CIM sense circuitry to sense a voltage for multiple memory cells triggered together. The CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value...use of time-domain based analog computation in memory instead of voltage domain…”)
Regarding claim 2, Kumar teaches the memory device of claim 1, wherein the charge integration circuit provides a sensing voltage based on a decrease of a voltage on the bitline (para(530, “…multiple bitcells will be discharged together and the TDC can generate a digital code as an output to represent an amount of time it takes for the bitcells to be discharged to a low voltage reference…”)
Regarding claim 3, Kumar teaches the memory device of claim 2, wherein the comparator compares the sensing voltage with a reference voltage and provides an output voltage based on the comparison (Kumar teaches that discharge timing is detected based on when the bitline signal cross a predefined detection level, which requires comparison with a reference threshold).
Regarding claim 4, Kumar teaches the memory device of claim 3, wherein the time-to-digital convertor converts a time associated with the output voltage to a digital value (para(530, “…multiple bitcells will be discharged together and the TDC can generate a digital code as an output to represent an amount of time it takes for the bitcells to be discharged to a low voltage reference…”)
Regarding claim 5, Kumar teaches the memory device of claim 1, further comprising a controller (150 in figure 1A) , wherein the controller is operative to initiate a multiply-accumulate operation (Kumar teaches control circuit that can activates multiple memory cells simultaneously to initiate compute-in-memory operations that generate the aggregate bitline discharge).
Regarding claim 6, Kumar teaches the memory device of claim 1, wherein the time-to-digital convertor comprises a first delay circuit, a second delay circuit, and output circuits connected to the first delay circuit and the second delay circuit (Kumar teaches a time-to-digital converter that perform time measurement using internal timing circuitry and digital output logic. A TDC which generates a digital timing code comprising delay circuitry and associate output logic. The use of multiple delay circuits (first and second delay circuits) with output logic is a well-known and obvious implementation choice for TDC structures).
Regarding claim 7, Kumar teaches the memory device of claim 6, wherein the first delay circuit comprises a first plurality of delay elements connected in series, each of the first plurality of delay elements configured to delay a signal by a first predetermined delay time (Kumar teaches the use a TDC, a series chain of delay elements is a standard and fundamental structure for implementing delay circuitry of a TDC, therefore, configuring each delay element to provide a predetermined delay time is a routine design choice in TDC).
Regarding independent claim 8, Kumar teaches a method of Multiply-Accumulate (MAC) operation in a memory device, the method comprising: sensing a voltage of a bitline (para (23)/(26), “…memory circuit includes CIM sense circuitry to sense a voltage for multiple memory cells triggered together. The CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value...use of time-domain based analog computation in memory instead of voltage domain…”);
charging, by a charge integration circuit, a sensing node based on a decrease of the voltage on the bitline (Kumar teaches aggregate discharge of the bitline by multiple cells. The bitline capacitance inherently integrate this discharge to form a sensing voltage);
comparing, by a comparator (a TDC cannot operate without a threshold detection event, which is functionally a comparator, Kumar teaches in Abstract “CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value”, therefore, Kumar needs detection of a timing of a discharge event, that time is used as the start/stop signal for the TDC, that threshold-crossing detection, by circuit definition, is a comparator, see 230 in figure 2B of Kumar, or 375 in figure 3 of Lee) coupled to the charge integration circuit (Kumar inherently teach “charge integration circuit” at the bitline, as multiple cells are activated together, their combined discharge represents the aggregate compute value, the bitline capacitance integrates this current, the discharge time is converted to a digital compute results, therefore, the bitline inherently functions as a charge integration circuit), a sensing voltage of the sensing node with a reference voltage;
providing, by the comparator, an output voltage based on the comparison (Kumar teaches in Abstract “CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value”); and
converting, by a time-to-digital converter (TDC 152 in figure 1A of Kumar) coupled to the comparator, a time associated with the output voltage to a MAC value (para (23)/(26) of Kumar, “…memory circuit includes CIM sense circuitry to sense a voltage for multiple memory cells triggered together. The CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value…”).
Regarding claim 9, Kumar teaches the method of claim 8, wherein charging the sensing node comprises charging the sensing node at a first rate till the sensing voltage is pulled to a threshold voltage (para(53) of Kumar, “…multiple bitcells will be discharged together and the TDC can generate a digital code as an output to represent an amount of time it takes for the bitcells to be discharged to a low voltage reference…”)
Regarding claim 10, Kumar teaches the method of claim 9, wherein charging the sensing node comprises charging the sensing node at a second rate after the sensing voltage is pulled to the threshold voltage (Kumar teaches that after threshold detection, the discharge behavior transitions into the time-measurement phase used by TDC. This transition produces a second effective rate of voltage evolution associated with post-threshold timing measurement).
Regarding claim 11, Kumar teaches the method of claim 10, wherein the second rate is greater than the first rate (Kumar teaches a rapid timing detection mechanism following threshold crossing that drives TDC input, the post -threshold timing signal transition is faster than the pre-threshold analog discharge behavior, yielding a second rate is greater than the first rate).
Regarding claim 12, Kumar teaches the method of claim 8, wherein charging the sensing node comprises: charging the sensing node based on discharge rate of a bitline voltage of the bitline (para(53) of Kumar, “…multiple bitcells will be discharged together and the TDC can generate a digital code as an output to represent an amount of time it takes for the bitcells to be discharged to a low voltage reference…”)
Claim 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kumar US Patent 11048434 (hereinafter Kumar), in view of Lee US Patent 7596011 (hereinafter Lee).
Regarding claim 13, Kumar teaches the method of claim 8, but does not teach wherein connecting the charge integration circuit to the bitline comprises connecting the charge integration circuit to the bitline through a multiplexer.
However, shared bitline-to-sense amp multiplexing is a well -known in DRAM/SRAM design. For example, Lee teaches in figure 3 a 2:1 multiplxer (380 in figure 3 of Lee) that selects which bitline is connected to a sense amplifier (375 in figure 3 of Lee) for read out.
Kumar and Lee are analogous art because they address the same field of endeavor: memory storage apparatuses control circuit designs and control methods therefor. At the time of the effective filing, it would have been obvious to one of ordinary skill in the art, having the teachings of Kumar and Lee before him, to modify the time domain compute-in-memory scheme of Kumar of to include the multiplexer scheme of Lee, such that connecting the charge integration circuit to the bitline comprises connecting the charge integration circuit to the bitline through a multiplexer, in order to reduce area and reuse sense circuitry.
Regarding independent claim 14, the combination of Kumar and Lee teaches a method of Multiply-Accumulate (MAC) operation in a memory device, the method comprising: selecting a multiplexer of a plurality of multiplexers ((380 in figure 3 of Lee) of a memory device, wherein each of the plurality of multiplexers (380 in figure 3 of Lee) is associated with a predetermined number of bitlines (Lee teaches a 2:1 multiplexer) of the plurality of bitlines;
connecting, by the multiplexer, a bitline of the predetermined number of bitlines associated with the multiplexer to an associated Input/Output circuit (sense AMP 144 plus TDC 152 in figure 1A of Kumar); and
sensing, by the Input/Output circuit, a multiply-accumulate value for the bitline in a time domain (Kumar teaches in Abstract “CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value”, para (23)/(26) of Kumar, “…memory circuit includes CIM sense circuitry to sense a voltage for multiple memory cells triggered together. The CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value...use of time-domain based analog computation in memory instead of voltage domain…”).
Regarding claim 15, the combination of Kumar and Lee teaches the method of claim 14, wherein sensing, by the Input/Output circuit, a multiply-accumulate value for the bitline in the time domain comprises:
charging, by a charge integration circuit, a sensing node based on a decrease of the voltage on the bitline (Kumar teaches aggregate discharge of the bitline by multiple cells. The bitline capacitance inherently integrate this discharge to form a sensing voltage);
comparing, by a comparator (a TDC cannot operate without a threshold detection event, which is functionally a comparator, Kumar teaches in Abstract “CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value”, therefore, Kumar needs detection of a timing of a discharge event, that time is used as the start/stop signal for the TDC, that threshold-crossing detection, by circuit definition, is a comparator, see 230 in figure 2B of Kumar, or 375 in figure 3 of Lee) coupled to the charge integration circuit (Kumar inherently teach “charge integration circuit” at the bitline, as multiple cells are activated together, their combined discharge represents the aggregate compute value, the bitline capacitance integrates this current, the discharge time is converted to a digital compute results, therefore, the bitline inherently functions as a charge integration circuit), a sensing voltage of the sensing node with a reference voltage;
providing, by the comparator, an output voltage based on the comparison (Kumar teaches in Abstract “CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value”); and
converting, by a time-to-digital converter (TDC 152 in figure 1A of Kumar) coupled to the comparator, a time associated with the output voltage to a MAC value (para (23)/(26) of Kumar, “…memory circuit includes CIM sense circuitry to sense a voltage for multiple memory cells triggered together. The CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value…”).
Regarding claim 16, the combination of Kumar and Lee teaches the method of claim 15, wherein charging the sensing node comprises charging the sensing node at a first rate till the sensing voltage is pulled to a threshold voltage (para(53) of Kumar, “…multiple bitcells will be discharged together and the TDC can generate a digital code as an output to represent an amount of time it takes for the bitcells to be discharged to a low voltage reference…”)
Regarding claim 17, the combination of Kumar and Lee teaches the method of claim 16, wherein charging the sensing node comprises charging the sensing node at a second rate after the sensing voltage is pulled to the threshold voltage (Kumar teaches that after threshold detection, the discharge behavior transitions into the time-measurement phase used by TDC. This transition produces a second effective rate of voltage evolution associated with post-threshold timing measurement).
Regarding claim 18, the combination of Kumar and Lee teaches the method of claim 17, wherein the second rate is greater than the first rate (Kumar teaches a rapid timing detection mechanism following threshold crossing that drives TDC input, the post -threshold timing signal transition is faster than the pre-threshold analog discharge behavior, yielding a second rate is greater than the first rate).
Regarding claim 19, the combination of Kumar and Lee teaches the method of claim 15, wherein charging the sensing node comprises: charging the sensing node based on discharge rate of a bitline voltage of the bitline (para(53) of Kumar, “…multiple bitcells will be discharged together and the TDC can generate a digital code as an output to represent an amount of time it takes for the bitcells to be discharged to a low voltage reference…”)
Regarding claim 20, the combination of Kumar and Lee teaches the method of claim 15, wherein connecting the charge integration circuit to the bitline comprises connecting the charge integration circuit to the bitline through a multiplexer (380 in figure 3 of Lee, Lee teaches a multiplexer that selectively connects one bitline from a plurality of bitlines to a shared sense amplifer).
Conclusion
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824