DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I drawn to claims 1-15 in the reply filed on 8/26/2026 is acknowledged. The traversal is on the ground(s) that no serious search burden exists between Group I and Group II.
This is not found persuasive because determining the patentability of divergent subject matter from two different statutory categories of invention is a serious burden as established by the examiner in the Restriction mailed 7/7/2026, pp. 2-3. As noted in the restriction requirement, not only are the different inventions classified differently, the method could be performed by a different apparatus, and reasons (a)-(e) are provided, consistent with MPEP §808.02. The field of search is different, the search queries will be different, and the manner in which prior art applies to an apparatus or to a method will be different. Applicant has failed to set forth any evidence establishing the apparatus and method would have the same classification, the same filed of search, or employing the same search queries would result in art similarly applicable to each invention. The requirement is still deemed proper and is therefore made FINAL.
Claims 16-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected Group, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 8/26/2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4-5, 7, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bouche et al. (US 20150091093 A1), hereinafter referred to as Bouche, in view of Chu et al. (US 20210193816 A1) hereinafter referred to as Chu.
Regarding claim 1: Bouche teaches a method of forming an electrical contact in a semiconductor structure, comprising:
performing a cavity (recess) shaping process (prior to Fig. 1, “portions of semiconductor substrate 12 in the source/drain regions 30 may be removed to form recesses”, para. [0018]); to form a first cavity at an exposed surface of a p-MOS region (PFET area 14) within a first opening formed in a dielectric layer (spacer material 26) and a second cavity at an exposed surface of an n-MOS region (NFET area 16) within a second opening formed in the dielectric layer (“In this regard, formation of the spacers 26 may begin by conformally depositing a spacer material overlying the gate caps 22, gate structures 18 and semiconductor substrate 12. The spacer material is an appropriate insulator, such as silicon nitride”, para. [0017], first and second openings are made through the dielectric layer between the gate structures, leaving the spacers 26 behind, cavities are made within the openings as described in para. [0018], see annotated figure below);
performing a first deposition process to form a contact layer on an exposed surface of the first cavity and on an exposed surface of the second cavity (“semiconductor stressors may be re-grown in the resulting recesses”, para. [0018]);
performing a metallic liner deposition process (See Fig. 2) to form a metallic liner (First metal layer 40) on inner surfaces of the first opening and the second opening, and over the dielectric layer (See Fig. 2, metal layer 40 is shown to cover the side walls of the openings and the tops of spacers 26);
performing a patterning process to remove the metallic liner and the contact layer over the n-MOS region (See Fig. 4, para. [0023], “Other suitable etching process may be used provided they do not etch, or only slightly etch, gate caps 22, spacers 26, and source/drain regions 30.”, slightly etching the regions 30 is considered removal of the contact layer in the NFET region); and
performing a second deposition process to form a cap layer (second metal layer 60) on the inner surfaces of the first opening and the second opening (See Fig. 11).
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Fig. 1 From Bouche: First/second openings and first/second cavities along with contact layer 30 are formed before figure 1, as described in para. [0017-0018].
Bouche does not teach that the contact layer (top portions of elements 30) and the cap layer (second metal layer 60) are selectively deposited.
Chu teaches a method of selective epitaxial growth (“epitaxial fin regions 114A and 114B can be grown by selective epitaxial growth (SEG)”, para. [0039]) and selective deposition of a metal layer (“selectively depositing metal capping layers 131A”, para. [0095]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method taught by Bouche to selectively grow the epitaxial layers and selectively deposit the metal layer. This would have the predictable result of reducing the processing steps compared to conformally depositing the layer and then patterning the layer. Chu also teaches similar materials (“p-type epitaxial fin regions 114B can include SiGe”, para. [0044], “n-type epitaxial fin regions 114A can include Si”, para. [0041], “capping layers 131A can include a single layer or a stack of conductive materials such as, for example, TiN, Ti, Ni, TiSiN, TaN, Ta, or a combination thereof., para. [0065]), so such a modification could be made with a reasonable chance of success.
Regarding claim 4: In addition to the reasoning used to reject claim 1, Bouche teaches that the cap layer (second metal layer 60) comprises material selected from silicides of titanium (Ti), molybdenum (Mo), platinum (Pt), and nickel (Ni). (“an anneal may be performed, such as at a temperature of from about 600.degree. C. to about 850.degree. C. Under this heat treatment, the metal in the second metal layer 60 reacts preferentially with the semiconductor material of the source/drain regions 30 in the NFET areas 16 to form second silicide contacts 80.”, para. [0032]). The NFET regions contain silicon (“the semiconductor stressors in NFET areas 16 may comprise silicon.”, para. [0018]) and the second metal layer 60 is titanium (“An exemplary second metal layer 60 includes titanium.”, para. [0030].) therefore, the second metal layer comprises titanium silicide after the annealing step.
Regarding claim 5: In addition to the reasoning used to reject claim 1, Bouche teaches the metallic liner (first metal layer 40) comprises material selected from cobalt (Co), platinum (Pt), titanium (Ti), nickel (Ni), titanium nitride (TiN), and tantalum nitride (TaN). (“the first metal layer 40 may include nickel, other metals suitable for P-type contacts, or alloys of platinum, nickel, and/or the other suitable metals for P-type contacts.”, para. [0021]).
Regarding claim 7: In addition to the reasoning used to reject claim 1, Bouche teaches prior to the second selective deposition process, performing a removal process to remove the metallic liner. (See Fig. 5, first metal layer 40 is removed in the PFET region before second metal layer 60 is applied in Fig. 11).
Regarding claim 9: In addition to the reasoning used to reject claim 1, Bouche teaches that subsequent to the second selective deposition process, performing a metal fill process to form a first contact plug in the first opening and a second contact plug in the second opening. (See Figs. 12-14, “a fill metal 70 is deposited over the partially fabricated integrated circuit 10”, para. [0031]).
Claim(s) 2, 6, 10-11, 13 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bouche et al. (US 20150091093 A1), hereinafter referred to as Bouche, in view of Chu et al. (US 20210193816 A1) hereinafter referred to as Chu, and Jiang et al. (US 20210111067 A1) hereinafter referred to as Jiang.
Regarding claim 2: In addition to the reasoning used to reject claim 1, Bouche teaches forming a liner layer on the cap layer (“the second metal layer 60 may include a titanium nitride capping material”, para. [0030]). Bouche and Chu do not teach that prior to the second selective deposition process, performing a surface pre-clean process; and subsequent to the second selective deposition process, performing a liner deposition process to form a liner on the cap layer, wherein the surface pre-clean process, the second selective deposition process, and the liner deposition process are performed without breaking vacuum environment.
Jiang teaches a pre-cleaning process, a barrier layer deposition process, an interface layer deposition process and a gap filling layer deposition process may be formed in the cluster processing system without breaking vacuum (para. [0021]). Jiang also teaches titanium nitride as a barrier layer (“In one embodiment, the barrier layer 704 is a TaN, TiN, TaO, TiO, TaON or TiON layer”, para. [0090]). Jiang teaches the advantages of performing process steps without breaking vacuum (“so that the likelihood of contamination and pollution from the air or from the environment can be substantially eliminated.”, para. [0021]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, that performing the pre-clean process and the deposition steps without breaking vacuum would have the advantage of reducing contaminates and improving the quality of the device. The processing chamber taught by Jiang could be used to perform the method steps taught by Bouche with a reasonable chance of success, since the processing chamber methods of Jiang were well-known in the art.
Regarding claim 6: In addition to the reasoning used to reject claim 1, Bouche does not explicitly teach that prior to the cavity shaping process, performing a pre-clean process to clean the exposed surface of the p-MOS region and the exposed surface of the n-MOS region.
Jiang teaches a pre-cleaning process of a substrate, (See Fig. 6, step 604). And that the process performed at operation 604 may assist removing surface contaminations or surface native oxide from the substrate surface (para. [0084]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a pre-cleaning step, as taught by Jiang, into the method taught by Bouche and Chu to reduce contamination and improve the quality of the device. Pre-cleaning is a well-known and routine process in the semiconductor industry and would have predictable results.
Regarding claim 10: Bouche teaches a method of forming an electrical contact in a semiconductor structure, comprising: a p-MOS region (element 14), an n-MOS region (element 16), a dielectric layer (“spacer material, see para. [0017]) having a first opening over the p-MOS region and a second opening over the n-MOS region (openings are formed when depositing elements 30, prior to what is shown in Fig. 1 of Bouche);
performing a cavity (recess) shaping process to form a first cavity on an exposed surface of the p-MOS region (PFET area 14) within the first opening and a second cavity at an exposed surface of the n-MOS region (NFET area 16) within the second opening forming a contact layer on an exposed surface of the first cavity and on an exposed surface of the second cavity (prior to Fig. 1, “portions of semiconductor substrate 12 in the source/drain regions 30 may be removed to form recesses and semiconductor stressors may be re-grown in the resulting recesses”, para. [0018]);
performing a metallic liner deposition process (See Fig. 2) to form a metallic liner (First metal layer 40) on inner surfaces of the first opening and the second opening, and over the dielectric layer (See Fig. 2, spacers 26 are what remains of the dielectric layer after forming the first and second openings, first metal layer 40 is on the inner surfaces of the openings and on top of spacers 26);
performing a patterning process to remove the metallic liner over the n-MOS region (See Fig. 4, para. [0023]); performing a removal process to remove the metallic liner (See Fig. 5, first metal layer 40 is removed in the PFET region before second metal layer 60 is applied in Fig. 11); performing a second deposition process to form a cap layer (second metal layer 60) on the inner surfaces of the first opening and the second opening (See Fig. 11); and
performing a metal fill process to form a first contact plug in the first opening and a second contact plug in the second opening (See Figs. 12-14, “a fill metal 70 is deposited over the partially fabricated integrated circuit 10”, para. [0031]).
Bouche does not teach that the contact layer (top portions of elements 30) and the cap layer (second metal layer 60) are selectively deposited.
Chu teaches a method to selective epitaxial growth (“epitaxial fin regions 114A and 114B can be grown by selective epitaxial growth (SEG)”, para. [0039]) and selective deposition of a metal layer (“selectively depositing metal capping layers 131A”, para. [0095]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to modify the method taught by Bouche to selectively grow the epitaxial layers and selectively deposit the metal layer. This would have the predictable result of reducing the processing steps compared to conformally depositing the layer and then patterning the layer. Chu also teaches similar materials (“p-type epitaxial fin regions 114B can include SiGe”, para. [0044], “n-type epitaxial fin regions 114A can include Si”, para. [0041], “capping layers 131A can include a single layer or a stack of conductive materials such as, for example, TiN, Ti, Ni, TiSiN, TaN, Ta, or a combination thereof., para. [0065]), so such a modification could be made with a reasonable chance of success.
The methods of Bouche and Chu do not teach performing a pre-clean process to clean exposed surfaces of a semiconductor structure.
Jiang teaches a pre-cleaning process of a substrate, (See Fig. 6, step 604). And that the process performed at operation 604 may assist removing surface contaminations or surface native oxide from the substrate surface (para. [0084]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a pre-cleaning step, as taught by Jiang, into the method taught by Bouche and Chu to reduce contamination and improve the quality of the device. Pre-cleaning is a well-known and routine process in the semiconductor industry and would have predictable results.
Regarding claim 11: In addition to the reasoning used to reject claim 10, the method of Bouche and Chu do not teach prior to the second selective deposition process, performing a surface pre-clean process; and subsequent to the second selective deposition process, performing a liner deposition process to form a liner on the cap layer, wherein the surface pre-clean process, the second selective deposition process, and the liner deposition process are performed without breaking vacuum environment.
Jiang teaches a pre-cleaning process, a barrier layer deposition process, an interface layer deposition process and a gap filling layer deposition process may be formed in the cluster processing system without breaking vacuum (para. [0021]). Jiang also teaches titanium nitride as a barrier layer (“In one embodiment, the barrier layer 704 is a TaN, TiN, TaO, TiO, TaON or TiON layer”, para. [0090]). Jiang teaches the advantages of performing process steps without breaking vacuum (“so that the likelihood of contamination and pollution from the air or from the environment can be substantially eliminated.”, para. [0021]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, that performing the pre-clean process and the deposition steps without breaking vacuum would have the advantage of reducing contaminates and improving the quality of the device. The processing chamber taught by Jiang could be used to perform the method steps taught by Bouche and Chu with a reasonable chance of success, since the processing chamber methods of Jiang were well-known in the art.
Regarding claim 13: In addition to the reasoning used to reject claim 10, Bouche teaches that the cap layer (second metal layer 60) comprises material selected from silicides of titanium (Ti), molybdenum (Mo), platinum (Pt), and nickel (Ni). (“an anneal may be performed, such as at a temperature of from about 600.degree. C. to about 850.degree. C. Under this heat treatment, the metal in the second metal layer 60 reacts preferentially with the semiconductor material of the source/drain regions 30 in the NFET areas 16 to form second silicide contacts 80.”, para. [0032]). The NFET regions contain silicon (“the semiconductor stressors in NFET areas 16 may comprise silicon.”, para. [0018]) and the second metal layer 60 is titanium (“An exemplary second metal layer 60 includes titanium.”, para. [0030].) therefore, the second metal layer comprises titanium silicide after the annealing step.
Regarding claim 14: In addition to the reasoning used to reject claim 10, Bouche teaches the metallic liner comprises material selected from cobalt (Co), platinum (Pt), titanium (Ti), nickel (Ni), titanium nitride (TiN), and tantalum nitride (TaN). (“the first metal layer 40 may include nickel, other metals suitable for P-type contacts, or alloys of platinum, nickel, and/or the other suitable metals for P-type contacts.”, para. [0021]).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bouche et al. (US 20150091093 A1), hereinafter referred to as Bouche, in view of Chu et al. (US 20210193816 A1) hereinafter referred to as Chu816, and Chu et al. (US 20220375797 A1) hereinafter referred to as Chu797.
Regarding claim 3: In addition to the reasoning used to claim 1, Bouche teaches that the p-MOS region comprises silicon germanium doped with p-type dopants, the n-MOS region comprises silicon doped with n-type dopants, and the contact layer comprises silicon germanium doped with p-type dopants. (“exposed portions of semiconductor substrate 12 in the source/drain regions 30 may be removed to form recesses and semiconductor stressors may be re-grown in the resulting recesses. In an exemplary embodiment, the semiconductor stressors in PFET areas 14 may comprise silicon germanium (SiGe) and the semiconductor stressors in NFET areas 16 may comprise silicon.”, para. [0018]), (“An implantation or implantations are performed to introduce selected conductivity-determining ions into the semiconductor substrate 12 to form appropriately doped source/drain regions 30”, para. [0018]).
Bouche and Chu816 are silent on the ratio of germanium (Ge) to silicon (Si) and do not teach that the ratio of Ge to Si is between 60% and 100%.
Chu797 teaches a Ge-to-Si ratio larger than 3:2 (60% to 100%). Because Si and Ge have different lattice constants, the heteroepitaxial SiGe lattice is strained. (para. [0049]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to look to the prior art to determine the appropriate ratio of Ge to Si to produce the stressed channels taught by Bouche. Chu797 teaches that the ratio should be at least 3:2 Ge to Si, so a person of ordinary skill in the art would modify the method of Boche to include a Ge to Si ratio of between 60% and 100%. The methods of Bouche and Chu797 involve a similar device and the ratio of Ge to Si is for a similar purpose, so such a modification would have predictable results of applying stress to the channels.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bouche et al. (US 20150091093 A1), hereinafter referred to as Bouche, in view of Chu et al. (US 20210193816 A1) hereinafter referred to as Chu816, and Jiang et al. (US 20210111067 A1) hereinafter referred to as Jiang, and Chu et al. (US 20220375797 A1), hereinafter referred to as Chu797.
Regarding claim 12: In addition to the reasoning used to reject claim 10, Bouche teaches the p-MOS region comprises silicon germanium doped with p-type dopants, the n-MOS region comprises silicon doped with n-type dopants, and the contact layer comprises silicon germanium. (“exposed portions of semiconductor substrate 12 in the source/drain regions 30 may be removed to form recesses and semiconductor stressors may be re-grown in the resulting recesses. In an exemplary embodiment, the semiconductor stressors in PFET areas 14 may comprise silicon germanium (SiGe) and the semiconductor stressors in NFET areas 16 may comprise silicon.”, para. [0018]), (“An implantation or implantations are performed to introduce selected conductivity-determining ions into the semiconductor substrate 12 to form appropriately doped source/drain regions 30”, para. [0018]).
The methods of Bouche, Chu816, and Jiang are silent on the ratio of germanium (Ge) to silicon (Si) and do not teach that the ratio of Ge to Si is between 60% and 100%.
Chu797 teaches a Ge-to-Si ratio larger than 3:2 (60% to 100%). Because Si and Ge have different lattice constants, the heteroepitaxial SiGe lattice is strained. (para. [0049]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to look to the prior art to determine the appropriate ratio of Ge to Si to produce the stressed channels taught by Bouche. Chu797 teaches that the ratio should be at least 3:2 Ge to Si, so a person of ordinary skill in the art would modify the method of Boche to include a Ge to Si ratio of between 60% and 100%. The methods of Bouche and Chu797 involve a similar device and the the ratio of Ge to Si is for a similar purpose so such a modification would have predictable results.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bouche et al. (US 20150091093 A1), hereinafter referred to as Bouche, in view of Chu et al. (US 20210193816 A1) hereinafter referred to as Chu and O’Brien (US 6277743 B1) hereinafter referred to as O’Brien.
Regarding claim 8: In addition to the reasoning used to reject claim 7, Bouche and Chu do not teach wherein the removal process comprises dry etching using an anhydrous HF based salt formation and sublimation cycle or dilute hydrofluoric acid (dHF).
O’Brien teaches using dilute HF vapor to remove unwanted filaments from Nickel silicide (“etch the silicide with ultradilute or vapor HF to remove any unwanted filaments.”, [Col. 5, lines 10-15]). And that this method offers increased etching selectivity (“Advantages include simplicity of the removal of metal/nitride plus silicide filaments with selectivity and control for the silicides for titanium, cobalt, and nickel.”, [Col. 1, lines 65-67]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include the etching method taught by O’Brien into the methods taught by Bouche, specifically when removing the metal liner layer (first metal layer 40), to improve the selectivity and control of the removal. Since the metal liner layer (See Bouche, first metal layer 40) can be made of Ti or Ni (See Bouche, para. [0021]), the dilute HF could be incorporated into the etching step (See Bouche, Fig. 5, para. [0024]) with a reasonable chance of success.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bouche et al. (US 20150091093 A1), hereinafter referred to as Bouche, in view of Chu et al. (US 20210193816 A1) hereinafter referred to as Chu, and Jiang et al. (US 20210111067 A1) hereinafter referred to as Jiang, and O’Brien (US 6277743 B1), hereinafter referred to as O’Brien.
Regarding claim 15: In addition to the reasoning used to reject claim 10, Bouche, Chu, and Jiang do not teach the removal process comprises wet etching using an anhydrous HF based salt formation and sublimation cycle or dilute hydrofluoric acid (dHF).
O’Brien teaches using dilute HF to remove unwanted filaments from Nickel silicide (“etch the silicide with ultradilute or vapor HF to remove any unwanted filaments.”, [Col. 5, lines 10-15]) and that it may be a wet etching method (“The HF vapor may be either wet or anhydrous”, [Col. 5, lines 30-35]). O’Brien also teaches that this method offers increased etching selectivity (“Advantages include simplicity of the removal of metal/nitride plus silicide filaments with selectivity and control for the silicides for titanium, cobalt, and nickel.”, [Col. 1, lines 65-67]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include the etching method taught by O’Brien into the methods taught by Bouche, specifically when removing the metal liner layer (first metal layer 40), to improve the selectivity and control of the removal. Since the metal liner layer (See Bouche, first metal layer 40) can be made of Ti or Ni (See Bouche, para. [0021]), the dilute HF could be incorporated into the etching step (See Bouche, Fig. 5, para. [0024]) with a reasonable chance of success.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered relevant to the Applicant’s Disclosure: Ning et al. teaches (US 20110070701 A1) teaches a method for etching Tungsten and Platinum with HF. Xie et al. (US 9685384 B1) teaches removing the contact layer on just the NFET or PFET side of a CMOS device. Basker et al. (US 20180005903 A1) teaches forming a contact layer of the same material in the PFET and NFET regions, then removing the contact layer in just the NFET region.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT L STEWART whose telephone number is (571)-270-0853. The examiner can normally be reached M-F 8:00am-4:00pm.
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/ROBERT L STEWART/ Examiner, Art Unit 2898
/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898
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