Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/1/2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/26/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 7-11, and 15 and is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choung (WO 2022050983 A1).
Regarding claim 1, Choung discloses, in FIG. 1A, a display panel comprising “substrate” (base layer) 102 a “pixel defining layer structure” 126 which is disposed on the base layer and in which a light-emitting opening (see “sub pixels” 108a and 108b) is defined; a “inorganic overhang structure” (partition wall) which is disposed on the pixel defining layer and in which a partition wall opening corresponding to the light-emitting opening is defined (see the above sub-pixels 108a and 108b); and a light-emitting element comprising an anode, an intermediate layer, and a cathode “Each sub-pixel includes an anode, an organic light-emitting diode (OLED) material disposed over and in contact with the anode, a cathode disposed over the OLED material” (abstract) wherein the cathode 114 is in contact with the partition wall (FIG 1A), the light-emitting element (OLED material 112) being disposed in the partition wall opening, wherein the partition wall comprises: a “lower portion” (first partition wall layer) 110A disposed on the pixel defining layer and comprising transparent conductive material (“A first configuration of the inorganic overhang structures 110 includes . . . the lower portion 110A of a conductive inorganic material); and an “upper portion (second partition wall layer) disposed on the first partition wall layer and comprising a metal or silicon-based compound (“A first configuration of the inorganic overhang structures 110 includes the upper portion 110B of a non-conductive inorganic material” [0029], “The non-conductive inorganic material includes, but is not limited to, an inorganic silicon-containing material“ [0030], and “The conductive inorganic material includes, but is not limited to, . . . , indium tin oxide, indium zinc oxide” [0030], the examiner notes that ITO and ZO are both transparent conductive oxides) and the first partition wall layer comprises: a first portion disposed on the pixel defining layer (first partition wall layer); a second portion (second partition wall layer) spaced apart from the pixel defining layer and having a height difference with respect to the first portion; and a first side portion (sides of the first and second partition wall layers) that connects the first portion and the second portion.
Regarding claim 2, Choung further discloses, in FIG. 1A, that the partition wall opening comprises: a first area in which the light-emitting element is disposed; and a second area having a width less than a width of the first area, the first side portion of the first partition wall layer comprises a first outer surface that defines the first area, and the second portion of the first partition wall layer comprises a second outer surface that defines the second area.
Regarding claim 3, Choung further discloses, in FIG. 1A, that the cathode is in contact with the first side portion of the first partition wall layer.
Regarding claim 4, Choung further discloses, in FIG. 1A, a “first capping layer” 121 in which “The first capping layer 121 may include an organic material” [0034] (therefore, 121 is an organic film). FIG. 1A shows a portion of this organic layer (which is part of the partition wall) which is disposed between the first partition wall layer and the second partition wall layer (see annotated FIG. 1A below, organic film is identified, and a vertical dashed/dotted line marks the end of the first capping layer horizontally, note that a portion of the organic film is between the first and second partition wall layers).
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Regarding claim 5, Choung further discloses, in FIG. 1A that the first partition wall layer is directly disposed on the pixel defining layer.
Regarding claim 7, Choung further discloses, in FIG. 1A, that the second partition wall layer is disposed on the first portion and the organic film.
Regarding claim 8, Choung further discloses, in FIG. 1A, that an outer surface of the second portion and an outer surface of the second partition wall layer define an alignment surface. The examiner notes that an “alignment surface,” according to a broadest reasonable interpretation, is any surface in which some alignment occurs. The examiner further notes that no special definition (see MPEP 211.01 IV) has been provided in the present specification (see specification filed 3/26/2024 [0016], [00167]).
Regarding claim 9, Choung further discloses, in FIG. 1A, that the second partition wall layer is directly disposed on the first partition wall layer.
Regarding claim 10, Choung further discloses, in FIG. 1A, that the second partition wall layer comprises: a third portion disposed on the first portion; a fourth portion spaced apart from the first portion and having a height difference with respect to the third portion; and a second side portion that connects the third portion to the fourth portion (see attached annotated FIG. 1A below).
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Regarding claim 11, as explained above, Choung discloses that the first partition wall layer “The includes, but is not limited to, . . . , indium tin oxide, indium zinc oxide” [0030].
Regarding claim 15, Choung discloses, in FIG. 1A, “encapsulation layers” 116 (note that the use of the plural “layers,” indicating a plurality of thin films, thus making this a thin film encapsulation layer) which are disposed on the light-emitting element , wherein the thin film encapsulation layer comprises an encapsulation inorganic pattern (“The encapsulation layer 116 includes the non-conductive inorganic material, such as the silicon- containing material” [0033]) which covers the light-emitting element (“The encapsulation layer 116 of a respective sub-pixel is disposed over the cathode 114 (and OLED material 112) . . .” [0033]) and of which a portion is in contact with the partition wall (“. . . with the encapsulation layer 116 extending under at least a portion of each of the inorganic overhang structures 110 and along a sidewall of each of the inorganic overhang structures 110” [0033]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Choung (WO 2022050983 A1) in view of Kim (US 20130248867 A1).
Regarding claim 6, as shown above, Choung teaches the limitations of claim 4. Kim does not teach a gap in the partition wall defined by the first portion, the first side portion, and a portion of the second partition layer filled by an organic film.
Kim teaches, in FIG. 1, a display panel comprising a “pixel defining layer” 114, a “clamp unit” (lower partition wall layer of a partition wall), the partition wall having a second partition wall layer made of the material of “second electrode” 117 (see FIG. 1, second electrode material is disposed on top of the lower partition wall layer, and thus is an upper partition wall layer, this upper partition wall layer comprises a metal material, see [0084]). Further a gap defined by a first portion (the first partition wall layer), a first side portion (which connects the side surfaces of the first and second partition wall layers), and a portion of the second partition wall layer is defined in the partition wall, and an “organic film” is disposed to be filled into the gap (see FIG. 1).
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the device taught by Choung such that there is an organic layer between the first and second partition wall layers (thereby filling a gap therebetween, defined by the first portion, first side portion, and a portion of the second partition wall layer). One having ordinary skill in the art is motivated to do so in order to, for example, prevent excessive diffusion between the transparent conductive oxide of the first partition wall layer and the second partition wall layer, preventing the degradation of the material properties of the respective layers.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Choung (WO 2022050983 A1).
Regarding claim 12, Choung further discloses, in [0030] that the second partition wall layer “The non-conductive inorganic material includes [which the second partition layer is made of, see above] but is not limited to, an inorganic silicon-containing material. E.g., the silicon-containing material includes oxides or nitrides of silicon, or combinations thereof.” The examiner notes that one of ordinary skill in the art knows this to include silicon oxide, silicon nitride, and silicon oxynitride (see “combinations thereof”).
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the device taught by Choung such that the second partition layer comprises at least one of silicon oxide, silicon nitride, and silicon oxynitride, as taught by Choung. One having ordinary skill in the art is motivated to do so in order to, for example, utilize the excellent thermal, electrical insulating, and physical properties of silicon oxide, silicon nitride, and silicon oxynitride.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Choung (WO 2022050983 A1) in view of Nakatani (US 20110156079 A1).
Regarding claim 13, as explained above, Choung teaches the limitations of claim 1. Choung does not explicitly teach thicknesses for the first and second partition wall layers.
Nakatani teaches, in [0115], “Bank 102 is arranged on substrate 101, and covers a part or whole of the edge of pixel electrode 103. The thickness of bank 102 is preferably 10-100 nm.” The examiner notes that the “bank” in this case is analogous to a partition wall layer, and that 100 nm is 1000 Å.
Applicant has not disclosed that each of the first portion and the second portion having a specific thickness of about 1,000 Å or more and about 2,000 Å or less, and the second partition wall layer having a thickness of about 1,000 Å or more and about 2,000 Å or less provides an advantage, is used for a particular purpose, or solves a stated problem other than the well-known and unsurprising function of a partition wall.
Therefore, before the effective filing date of the claimed invention it would have been obvious to one of ordinary skill in the art to modify the partition wall layers of Choung with the thickness taught by Nakatani. This is because one of ordinary skill in the art would have expected the aforementioned thickness range to be one of several straightforward ways of constructing a partition wall because it has at least a sufficient height to perform its function. Also, the specification contains no disclosure of either the critical nature of the claimed thicknesses or any unexpected results arising therefrom. Where patentability is said to be based upon thicknesses or upon another variable recited in a claim, the Applicant must show that the thicknesses are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Choung (WO 2022050983 A1) in view of Yamazaki (US 20230009750 A1).
Regarding claim 14, as explained above, Choung teaches the limitations of claim 1. Choung does not teach a sacrificial pattern disposed between the anode and the pixel defining layer.
Yamazaki teaches, in FIG. 7C, a “mask layer 145” ([0063] acknowledges that a mask layer is a sacrificial layer: “. . . a mask layer (sacrificial pattern) . . .”) which is disposed between “pixel electrode” (which is an anode if given a negative charge, which one having ordinary skill in the art appreciates as within the scope of the disclosure, see MPEP 2183) and a “resin layer” (pixel defining layer, as the gaps between resin layers define the pixel areas where light emitting elements are disposed), wherein the sacrificial pattern defines a sacrificial opening overlapping a light-emitting opening.
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the display panel taught by Choung such that a sacrificial pattern which is disposed between the anode and the pixel defining layer and in which a sacrificial opening overlapping the light-emitting opening is defined, as taught by Yamazaki. One having ordinary skill in the art is motivated to do so because, for example, “the mask layer (sacrificial layer) functions as a layer protecting the EL layer in the steps of processing the EL layer” (Yamazaki [0063]).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Choung (WO 2022050983 A1) in view of Lee (US 20230046219 A1).
Regarding claim 16, Choung teaches in FIG. 1A, an electronic apparatus comprising a display device comprising a display area comprising “substrate” (base layer) 102 a “pixel defining layer structure” 126 which is disposed on the base layer and in which a light-emitting opening (see “sub pixels” 108a and 108b) is defined; a “inorganic overhang structure” (partition wall) which is disposed on the pixel defining layer and in which a partition wall opening corresponding to the light-emitting opening is defined (see the above sub-pixels 108a and 108b); and a light-emitting element comprising an anode, an intermediate layer, and a cathode “Each sub-pixel includes an anode, an organic light-emitting diode (OLED) material disposed over and in contact with the anode, a cathode disposed over the OLED material” (abstract) wherein the cathode 114 is in contact with the partition wall (FIG 1A), the light-emitting element (OLED material 112) being disposed in the partition wall opening, wherein the partition wall comprises: a “lower portion” (first partition wall layer) 110A disposed on the pixel defining layer and comprising transparent conductive material (“A first configuration of the inorganic overhang structures 110 includes . . . the lower portion 110A of a conductive inorganic material); and an “upper portion (second partition wall layer) disposed on the first partition wall layer and comprising a metal or silicon-based compound (“A first configuration of the inorganic overhang structures 110 includes the upper portion 110B of a non-conductive inorganic material” [0029], “The non-conductive inorganic material includes, but is not limited to, an inorganic silicon-containing material“ [0030], and “The conductive inorganic material includes, but is not limited to, . . . , indium tin oxide, indium zinc oxide” [0030], the examiner notes that ITO and ZO are both transparent conductive oxides) and the first partition wall layer comprises: a first portion disposed on the pixel defining layer (first partition wall layer); a second portion (second partition wall layer) spaced apart from the pixel defining layer and having a height difference with respect to the first portion; and a first side portion (sides of the first and second partition wall layers) that connects the first portion and the second portion. Choung further teaches a “first capping layer” 121 in which “The first capping layer 121 may include an organic material” [0034] (therefore, 121 is an organic film). FIG. 1A shows a portion of this organic layer (which is part of the partition wall) which is disposed between the first partition wall layer and the second partition wall layer (see annotated FIG. 1A above, attached to rejection of claim 4, organic film is identified, and a vertical dashed/dotted line marks the end of the first capping layer horizontally, note that a portion of the organic film is between the first and second partition wall layers).
Choung does not teach a first area through which an optical signal passes, and a non-display area.
Lee teaches, in FIG. 1, an electronic apparatus 1000 comprising a display device comprising a “transmitting area” (display area) TA comprising a first area DA1 through which an optical signal passes (“the first element area DA2 may include a light transmission area LTA” [0072], the examiner notes a light transmission area allows the transmission an optical signal), and a second area DA1 adjacent the first area, and a “blocking area” BA (non-display area) adjacent to the display area. Lee further teaches, in [0072], “The first element area DA2 may be an area overlapping at least partially with an optical element ES such as a camera or an optical sensor” (electrical module disposed below the display device to overlap the first area and receiving the optical signal).
It would have been obvious to one having ordinary skill in the art at the effective filing date to modify the device taught by Choung such that it includes a first area through which an optical signal passes, and a second area adjacent to the first area; and a non-display area adjacent to the display area; and an electronic module disposed below the display device to overlap the first area and receiving the optical signal, as taught by Lee. One having ordinary skill in the art is motivated to do so because “Display devices may be included in various electronic devices, such as mobile phones, navigation devices, digital cameras, electronic books, portable game machines, and terminals” (Lee [0003]), and these devices often benefit commercially from cameras and optical sensors (for photo-taking, light sensing for adaptive display brightness, etc.). See KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
J. Kim (US 20230403884 A1) – “The display device may further include a sacrificial layer between the bank buffer layer and the anode electrodes, wherein the bank buffer layer has an edge extending past the sacrificial layer” [0030]. Partition wall comprising component 131 in which “The bank buffer layer 131 may have a thickness of about 1,500 Å to about 2,000 Å” [0145].
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GABRIEL S MINNEY whose telephone number is (571)272-9688. The examiner can normally be reached Monday Friday, 8:30 a.m. 5 p.m. ET..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/G.S.M./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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