DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, directed to claims 1-11, in the reply filed on 07/08/2026 is acknowledged.
Claims 12-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected grouping, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 07/08/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3 and 7-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Theuss (US 20090309191 A1), hereinafter referred to as Theuss191.
Regarding claim 1: Theuss191 teaches a method for correcting distortion of a semiconductor substrate (“Embodiments provide a system and method for repairing a warped surface of a semiconductor wafer” para. [0023]), comprising: receiving a semiconductor substrate with distortion (“wafer 22 is fabricated or grown from a monocrystalline silicon source into a wafer cylinder that is sliced into wafers. Wafer 22 includes any suitable wafer configured for fabrication/processing to include a plurality of semiconductor chips or dies.”, para. [0026]); measuring the semiconductor substrate to identify the distortion in a plurality of positions on the semiconductor substrate (“optical scanning assembly 28 locates a region 32 of curvature on wafer 22 and communicates the located region 32 to laser 30 by communicating through a controller 34.”, para. [0025], see Fig. 3 irradiate points 52); and implanting into the semiconductor substrate a lattice configuration signature (“irradiated point 52 provides a polycrystalline silicon region having a local density that is lower than a density of non-laser irradiated portions of monocrystalline silicon wafer 22.”, para. [0034]) according to the identified distortion in the positions on the semiconductor substrate such that the identified distortion of the semiconductor substrate is corrected. (“Points 52 become amorphousized by a laser-induced stress that increases the local volume around point 52 to stress surface 24. The increase in the volume (corresponding to a decrease in density) in the wafer material in region 32 induces stress locally adjacent to surface 24 that stretches surface 24 to repair the concave curvature.”, para. [0033]).
Regarding claim 2: Theuss191 teaches the method of claim 1, wherein implanting into the semiconductor substrate the lattice configuration signature includes focusing a light beam with an amount of energy in the positions on the semiconductor substrate (“Points 52 become amorphousized by a laser-induced stress that increases the local volume around point 52 to stress surface 24.”, para. [0033]).
Regarding claim 3: Theuss191 teaches the method of claim 2, wherein focusing the light beam with the amount of energy includes focusing a laser light beam with an amount of laser energy. (“laser 30 is a Nd:YAG laser having a power between 5-100 watts and operates at a speed between 100-300 mm/s, although other suitable lasers operated at other powers and transport speeds are also acceptable.”, para. [0028]).
Regarding claim 7: Theuss191 teaches the method of claim 3, wherein the laser light beam is tuned to a material of the semiconductor substrate. (Theuss191 discloses at least one set of laser parameters that are suitable for use with a silicon substrate, “laser 30 is a Nd:YAG laser having a power between 5-100 watts and operates at a speed between 100-300 mm/s, although other suitable lasers operated at other powers and transport speeds are also acceptable.”, para. [0028], The examiner notes that a laser that performs the function of correcting a distortion in a semiconductor substrate is necessarily “tuned to” the material of that substrate).
Regarding claim 8: Theuss191 teaches the method of claim 3, wherein the laser light beam is tuned to a lattice of the semiconductor substrate. (Lattice is interpreted by the examiner to mean the degree of crystallinity in the substrate, Theuss191 discloses an embodiment using monocrystalline silicon as an example, “In one embodiment, wafer 22 includes a monocrystalline silicon and the laser irradiated point 52 provides a polycrystalline silicon region having a local density that is lower than a density of non-laser irradiated portions of monocrystalline silicon wafer 22.”, para. [0034]., The examiner notes that a laser that performs the function of correcting a distortion in a semiconductor substrate is necessarily “tuned to” the lattice of that substrate).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-6 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Theuss (US 20090309191 A1), hereinafter referred to as Theuss191, in view of Cheng et al. (US 20240412972 A1) hereinafter referred to as Chen972.
Regarding claims 4-6: Theuss191 teaches the method of claim 3. Theuss191 does not explicitly teach that the laser light beam has power, pulse duration, or pulse number that is adjusted according to the identified distortion in the positions.
Chen972 recognizes that the power, pulse duration, and pulse number can affect the defect regions caused by a laser pulse (“Depending on different requirements, the pulse frequency can be adjusted according to the material type and the lateral size of the defect regions. The pulse width can be 100 femtoseconds (fs) to 500 nanoseconds (ns), or 0.2 nanoseconds (i.e., 200 picoseconds) to 10 nanoseconds, but is not limited thereto. When the pulse width of the laser is shorter, such as 300 picoseconds (ps), it can be used with a higher pulse frequency, such as MHz or above. The pulse energy of the first laser process can be 600 μJ/pulse to 20 μJ/pulse. It should be noted that the term “pulse energy” in this invention refers to the energy transmitted by the laser during each pulse. The energy received by the irradiated surface of the wafer per unit of time is not only related to the pulse energy but also to the pulse width and pulse frequency. Specifically, the energy received by the irradiated surface of the wafer per unit of time (μJ/ns) can be obtained by dividing the pulse energy by the pulse width. For a laser device with a given power, increasing the pulse frequency will result in a decrease in pulse energy. Additionally, if the laser pulse width is adjusted from the nanosecond level to the picosecond or femtosecond level, the laser peak power will become higher, making it easier to create high-density arrays of defect regions. Besides, the laser pulse energy used to create the arrays of defect regions is also related to the surface roughness of the wafer.”, para. [0029]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adjust the power, pulse duration, and pulse number depending on the material of the substrate and the distortion, in Theuss191 for example, depending on the degree of curvature in the wafer, a longer or shorter pulse duration at a chosen laser power would be required to correct the distortion, furthermore, the power of the laser would be adjusted within the workable ranges depending upon the material used. As disclosed in Chen972 the pulse duration and pulse number also affect the laser peak power and therefore the precision of the laser pulse offering more control over the corrective stress applied to the wafer. (The examiner also notes that in the instant case, the laser power and energy are used interchangeably and the laser pulse number and pulse frequency are also used interchangeably in the specification).
Regarding claim 9: In addition to the reasoning used to reject claim 4 Theuss191 teaches that the laser light beam is tuned to an interface below the semiconductor substrate. (“In one embodiment, wafer 22 includes a silicon substrate and a polymeric dielectric coupled to the silicon substrate. The observed curvature can be located in either the silicon or the polymeric dielectric. The laser irradiation is employed to effectively repair the observed curvature in one or the other of the silicon substrate and the polymeric dielectric.”, para. [0035], ”Wafer 202 can be fabricated to provide chips that are usefully employed in power applications and have a metal layer 204 attached to backside 206. Upon singulation, each chip separated from wafer 202 has an electrically conductive backside provided by metal layer 204. It has been observed that processing wafer 202 to include metal layer 204 can lead to curvature along a front side 208 or along backside 206 of wafer 202. Embodiments of system 200 provide for correcting or reducing curvature in surfaces 206, 208.”, para. [0044], see Fig. 13).
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Theuss (US 20090309191 A1), hereinafter referred to as Theuss191, in view of Bencher et al. (US 20150371908 A1) hereinafter referred to as Bencher908.
Regarding claim 10: Theuss191 teaches the method of claim 1, Theuss191 does not explicitly teach the positions include XY positions.
Bencher908 teaches the positions include XY positions (“The detector 316 may linearly scan the substrate surface using a line of optical radiation 318 provided therefrom across a linear region 320 of the substrate 310. The detector 316 may also help to identify the coordinate, alignment, or orientation of the substrate 310. The detector 316 may scan the substrate 310 as the substrate 310 advances in an X-direction 325. Similarly, the detector 316 may scan the substrate 310 as the substrate 310 moves in a Y-direction 327 as the translation mechanism 324 moves the stage 302. The detector 316 may be coupled to a controller 344, so as to control movement and data transfer from the detector 316 or other detectors or computing system to the laser energy apparatus 300.”
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that a device used to communicate the positions of distortions on a two-dimensional surface would need to include x and y positions. While not stated explicitly in Theuss191, a person of ordinary skill in the art would recognize that bowing or warping of the semiconductor substrate would likely require laser pulses at various points with different x and y coordinates. This limitation is explicitly taught by Bencher908.
Regarding claim 11: Theuss191 does not explicitly teach that the distortion in the XY positions is identified by determining alignment mark registration, overlay mark registration and/or reference grid registration on the semiconductor substrate.
Bencher908 teaches measuring the distortions using such an overlay map (“In one embodiment, a method for correcting film stress/strain variations on a substrate includes performing a measurement process in a metrology tool on a substrate to obtain a substrate distortion or an overlay error map, determining dose of laser energy in a computing system to correct film stress/strain variations based on the overlay error map, and providing a laser energy treatment recipe to a laser energy apparatus based on the dose of laser energy determined to correct substrate distortion or film stress/strain variations.”, para. [0011], see Fig. 1)
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that a device that measures the location and nature of the distortions would have to know the intended alignment and shape of the wafer in order to recognize the distortion. Alignment mark registration, overlay mark registration and/or reference grid registration are well-known methods in the art for determining the alignment of the semiconductor substrate. This limitation is explicitly taught by Bencher908.
Citation of Pertinent Prior Art
The prior art made of record and not relied upon is considered relevant to the Applicant’s Disclosure:
Knerer et al. (US 20080026232 A1) teaches a method for correcting vacancy clusters ("crystal originated particles", COPs or Voids) or oxygen precipitates (also called "bulk micro defects", BMDs) within a semiconductor wafer using a laser, where the power density of the laser beam and the required duration of the irradiation are defined by the type and size of the defects to be resolved.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT L STEWART whose telephone number is (571)-270-0853. The examiner can normally be reached M-F 8:00am-4:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at (571)-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ROBERT L STEWART/ Examiner, Art Unit 2898
/JESSICA S MANNO/ SPE, Art Unit 2898
Prosecution Insights