DETAILED ACTION
This action is responsive to Applicant’s reply filed 8/10/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Species A (Fig. 1) in the reply filed on 8/10/2026 is acknowledged. Applicant asserts claims 1-20 read on the elected species, but the Examiner disagrees.
In the Examiner-initiated interview held 8/27/2026, Applicant’s representative James Bergstrom stated the election was supposed to be Species C (Fig. 3), without traverse. It was also agreed by both parties that claims 1-20 read on Species C. A summary of the interview is attached with this action.
Claim Status
Claims 1-20 are pending, and have been examined herein on the merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 14-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rocha-Alvarez (US Pub. 2014/0087489).
Regarding claim 14, Rocha-Alvarez teaches a semiconductor processing chamber ([0012] and Fig. 1, processing chamber #100) comprising: a pedestal configured to support a substrate during a semiconductor process ([0012] and Fig. 1, substrate support #104 for substrates), wherein the pedestal comprises a first electrode for a electrostatic chuck (ESC) ([0018] and Fig. 1, electrode #124); a radio-frequency (RF) RF ground that grounds RF power provided to a plasma in the semiconductor processing chamber (Fig. 1, ground for either #142 or #150); a first power source for the ESC ([0018] and Fig. 1, power source #150) that provides a DC chucking voltage to the first electrode ([0018]); and a filter circuit ([0018] and Fig. 1, filter #148) that is electrically connected to the first electrode, the RF ground, and the first power source for the ESC (see Fig. 1), wherein the filter circuit electrically isolates the first power source for the ESC from the RF ground (see Fig. 1, same as in instant Fig. 1).
Regarding claim 15, Rocha-Alvarez teaches wherein the filter circuit is also electrically connected to an RF power supply that provides the RF power to the plasma through the first electrode (Fig. 1, filter #148 connected to #150; [0018]: may be RF power source).
Regarding claim 16, Rocha-Alvarez teaches wherein the filter circuit isolates the RF power supply from the first power source for the ESC (see Fig. 1, same as in instant Fig. 1).
Claims 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rocha-Alvarez (US Pub. 2014/0087489), as applied to claims 14-16 above, with Banda (US Pub. 2022/0301913) as an evidentiary reference.
The limitations of claims 19-20 are set forth above.
Regarding claims 19-20, to clarify the record, the claims are merely an intended use and are given patentable weight to the extent that the prior art is capable of performing the intended use. A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. See MPEP 2114(II).
While not explicitly disclosed, the Examiner respectfully submits that the power source #150 of Rocha-Alvarez would be inherently capable of providing DC power greater than or about 1000 VDC and about 1500 VDC.
In support of this assertion of inherency, the Examiner submits the evidentiary reference Banda ([0033]: DC chucking voltage of about 200 – 2000 V).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-7 are rejected under 35 U.S.C. 103 as being unpatentable over Haller (US Pub. 2022/0248500) in view of Birang (US Patent 5,459,632).
Regarding claim 1, Haller teaches a semiconductor processing chamber ([0024] and Fig. 1, chamber #100) comprising: a pedestal configured to support a substrate during a semiconductor process ([0024] and Fig. 1, pedestal #104 for substrate #154), wherein the pedestal comprises a first electrode ([0027] and Fig. 1, first electrode #172) and a second electrode ([0027] and Fig. 1, second electrode #174) for a electrostatic chuck (ESC) ([0029]); a chamber body that encloses the pedestal to form a processing region in which the semiconductor process is performed ([0024] and Fig. 1, chamber body #102 with processing volume #120), a first power source for the ESC that is electrically connected to the first electrode ([0029] and Fig. 1, DC source #162 to #172), wherein the first power source and the first electrode are electrically isolated from the system ground (see Fig. 1, path not electrically connected to anything else in the same way as instant Fig. 1); and a second power source for the ESC that is electrically connected to the second electrode ([0029] and Fig. 1, DC source #164 to #174), wherein the second power source and the second electrode are electrically isolated from the system ground (see Fig. 1, path not electrically connected to anything else in the same way as instant Fig. 1).
Haller does not explicitly teach wherein the chamber body is electrically connected to a system ground (although the Examiner submits such a feature is ubiquitous in the art such that this feature may inherently be present).
However, Birang teaches wherein the chamber body is electrically connected to a system ground (Fig. 1, chamber walls #105 are grounded).
It would be obvious to one of ordinary skill in the art, before the effective filing date of the instant application, to modify the Haller apparatus to have a grounded chamber body in order to provide an electrically conductive path for a wafer during processing and/or chucking (Birang – C4, L13-19).
Regarding claims 2-3 and 6-7, the entire claims are merely an intended use and are given patentable weight to the extent that the prior art is capable of performing the intended uses. A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. See MPEP 2114(II).
The modified Haller apparatus would be capable of performing a PECVD process with a variety of materials and temperatures by virtue of the teachings of Haller ([0002]). Additionally, Haller does not mention arcing; a PHOSITA would recognize that arcing is an extremely undesirable side effect in any PECVD apparatus, thus every PECVD apparatus would strive to operate without any arcing.
Regarding claim 4, Haller teaches a top-feed RF power supply that provides RF power to a plasma in the processing region ([0025] and Fig. 1, electrode #108 can be coupled to RF generator), wherein the RF power is grounded through the first electrode and/or the second electrode (see Fig. 1, both first/second electrodes have a ground).
Regarding claim 5, Haller teaches a bottom-feed RF power supply that provides RF power to a plasma in the processing region ([0028] and Fig. 1, RF source #160), wherein the RF power is provided through the first electrode and/or the second electrode (see Fig. 1).
Claims 8-13 are rejected under 35 U.S.C. 103 as being unpatentable over Haller (US Pub. 2022/0248500) in view of Li (US Pub. 2022/0130704).
Regarding claim 8, Haller teaches an electrostatic chuck (Fig. 1, pedestal #104 and all connected elements) comprising: a first electrode ([0027] and Fig. 1, second electrode #174) and a second electrode ([0027] and Fig. 1, first electrode #172) embedded in a pedestal (Fig. 1, pedestal #104) configured to support a substrate during a semiconductor process ([0024] and Fig. 1, for substrate #154); a first power source comprising a positive output that is electrically connected to the first electrode ([0029] and Fig. 1, DC source #164 to #174), and a negative output (see Fig. 1); and a second power source comprising a negative output that is electrically connected to the second electrode ([0029] and Fig. 1, DC source #162 to #172), and a positive output (see Fig. 1).
Haller does not teach wherein the positive output is electrically connected to the negative output of the first power source, wherein a connection between the positive output of the second power source and the negative output of the first power source is floating relative to a system ground.
However, Li teaches this feature (Li – Fig. 4B, power supplies #435/#440 coupled with opposite polarities and are disconnected from ground.
It would be obvious to one of ordinary skill in the art, before the effective filing date of the instant application, to connect the first/second power sources of Haller as taught by Li in order to eliminate a relative voltage differential between electrodes and chamber surroundings that can cause arcing (Li – [0053], [0054]).
Regarding claim 9, Haller does not teach the added limitations of the claim.
However, Li teaches wherein a connection between the positive output of the second power source and the negative output of the first power source comprises a voltage offset that equalizes current through the first electrode and the second electrode resulting from a bias induced on the substrate (Li – Fig. 4B, when connecting the power sources of Haller as proposed in claim 8; would be connected in the same way as shown in instant Fig. 1, see also instant par. [0041] that describes where the presence of the node #304 can perform this function on its own).
It would be obvious to one of ordinary skill in the art, before the effective filing date of the instant application, to connect the first/second power sources of Haller as taught by Li in order to eliminate a relative voltage differential between electrodes and chamber surroundings that can cause arcing (Li – [0053], [0054]).
Regarding claim 10, Haller does not teach the added limitations of the claim.
However, Li teaches wherein the electrostatic chuck forms a continuous current path from the first power source, to the first electrode, to the second electrode, to the substrate, to the second power source, and back to the first power source (Li – Fig. 4B, when connecting the power sources of Haller as proposed in claim 8; would be connected in the same way as shown in instant Fig. 1).
It would be obvious to one of ordinary skill in the art, before the effective filing date of the instant application, to connect the first/second power sources of Haller as taught by Li in order to eliminate a relative voltage differential between electrodes and chamber surroundings that can cause arcing (Li – [0053], [0054]).
Regarding claim 11, Haller does not teach the added limitations of the claim.
However, Li teaches wherein the continuous current path is not connected to any free current paths to the system ground (Li – Fig. 4B, when connecting the power sources of Haller as proposed in claim 8; would be connected in the same way as shown in instant Fig. 1).
It would be obvious to one of ordinary skill in the art, before the effective filing date of the instant application, to connect the first/second power sources of Haller as taught by Li in order to eliminate a relative voltage differential between electrodes and chamber surroundings that can cause arcing (Li – [0053], [0054]).
Regarding claim 12, Haller teaches wherein the first electrode and the second electrode form a bipolar electrostatic chuck ([0029]).
Regarding claim 13, Haller teaches wherein the first power source provides a positive voltage to the first electrode, and the second power source provides an equal and opposite negative voltage to the second electrode (see Fig. 1, sources regarded as capable of delivering the same power as they are depicted/described as the same types of sources).
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Rocha-Alvarez (US Pub. 2014/0087489), as applied to claims 14-16 above, further in view of Haller (US Pub. 2022/0248500).
The limitations of claims 14-16 are set forth above.
Regarding claim 17, Rocha-Alvarez teaches wherein the filter circuit isolates the first power source for the ESC from the RF ground ([0018]).
Rocha-Alvarez does not teach a capacitor with a capacitance greater than about 15 nF.
However, Haller teaches this feature (Haller – [0029]: capacitors #166/#168 may be 50 nF).
It would be obvious to one of ordinary skill in the art, before the effective filing date of the instant application, to include the capacitors of Haller with the Rocha-Alvarez apparatus in order to block and/or isolate the DC voltage.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Rocha-Alvarez (US Pub. 2014/0087489), as applied to claims 14-16 above, further in view of Makhratchev (US Patent 6,714,033).
The limitations of claims 14-16 are set forth above.
Regarding claim 18, Rocha-Alvarez teaches wherein the filter circuit isolates the first power source for the ESC from the RF ground ([0018]).
Rocha-Alvarez does not teach a resistor with a resistance greater than about 1 MΩ.
However, Makhratchev teaches this limitation (Makhratchev – C4, L14-19 and Fig. 3, resistor #314 of 2MΩ).
It would be obvious to one of ordinary skill in the art, before the effective filing date of the instant application, to utilize the resistor of Makhratchev as an obvious matter of overlapping ranges. The courts have held that where claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. See In re Wertheim, 541 F.sd 257, 191 USPQ 90 (CCPA 1976), and MPEP 2144.05.
Alternatively/additionally, claims 19-20 are rejected under 35 U.S.C. 103 as unpatentable over Rocha-Alvarez (US Pub. 2014/0087489), as applied to claims 14-16 above, further in view of Banda (US Pub. 2022/0301913).
The limitations of claims 14-16 are set forth above.
Regarding claims 19-20, Rocha-Alvarez does not explicitly teach wherein the first power source for the ESC provides greater than or about 1000 VDC or about 1500 VDC to the first electrode for the ESC.
However, Banda teaches these limitations ([0033]: DC chucking voltage of about 200 – 2000 V).
It would be obvious to one of ordinary skill in the art, before the effective filing date of the instant application, to set the first power source of Rocha-Alvarez to the voltages of Banda as an obvious matter of overlapping ranges. The courts have held that where claimed ranges overlap or lie inside ranges disclosed by the prior art, a prima facie case of obviousness exists. See In re Wertheim, 541 F.sd 257, 191 USPQ 90 (CCPA 1976), and MPEP 2144.05.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Donde (US Patent 5,729,423) teaches a similar electrical connection structure (Fig. 3), as does Hausmann (US Patent 6,215,640, Fig. 1) and Burkhart (US Patent 6,488,820, Fig. 5).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kurt Sweely whose telephone number is (571)272-8482. The examiner can normally be reached Monday - Friday, 9:00am - 5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Gordon Baldwin can be reached at (571)-272-5166. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kurt Sweely/Primary Examiner, Art Unit 1718
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