DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a Non-Final office action based on application 18/617,303 filed March 26, 2024. Claim 1-20 are currently pending and have been considered below.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 18 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie (Pre-Grant Publication 2024/0203990).
Regarding claim 18, Xie discloses a semiconductor device comprising:
a semiconductor substrate (Fig. 3a, 21);
a plurality of sets of channel features (12) disposed on the semiconductor substrate in a first direction normal to the semiconductor substrate and spaced apart from one another in a second direction parallel to the semiconductor substrate and transverse to the first direction, each set of the channel features including an uppermost channel feature and a lowermost channel feature disposed between the uppermost channel feature and the semiconductor substrate in the first direction;
an intermediate isolation feature (31) which is disposed between the uppermost channel feature and the lowermost channel feature in the first direction and which includes a first dielectric material (Paragraph [0086]);
a gate feature (36) including a first gate portion disposed on the uppermost channel feature, a second gate portion disposed between the uppermost channel feature and the intermediate isolation feature, and a third gate portion disposed between the intermediate isolation feature and the lowermost channel feature;
a first pair of inner spacers (33) laterally covering the second gate portion and including a second dielectric material different from the first dielectric material (Paragraph [0033]);
a second pair of inner spacers (33) laterally covering the third gate portion and including a third dielectric material different from the first dielectric material (Paragraph 0033]);
a lower source/drain portion (32) disposed on the semiconductor substrate and between two adjacent sets of the channel features;
a middle isolation feature (39) disposed on the lower source/drain portion and connected to the intermediate isolation feature; and
an upper source/drain portion (34) disposed on the middle isolation feature opposite to the lower source/drain portions.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8 & 11, 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih (Pre-Grant Publication 2024/0312846) in view of Lee (Pre-Grant Publication 2024/0021704).
Regarding claim 1, 2, 4, 6, Shih discloses a semiconductor device comprising:
forming a plurality of stack portions (Fig. 2 & 3, 204T & 204B) on a semiconductor substrate (202) in a first direction normal to the semiconductor substrate, the stack portions being spaced apart from each other by a plurality of source/drain trenches (Fig. 5, 224) which are disposed to alternate with the stack portions in a second direction parallel to the semiconductor substrate and transverse to the first direction, each of the stack portions including a set of channel features (208) and a set of sacrificial features (206) disposed to alternate with the set of the channel features in the first direction, the set of the channel features including a lowermost channel feature (lowermost 208), an uppermost channel feature (uppermost 208), and at least one intermediate channel feature (206M) disposed between the lowermost channel feature and the uppermost channel feature, the set of the sacrificial features including a lowermost sacrificial feature (lowermost (206), an uppermost sacrificial feature (uppermost 206), and at least one intermediate sacrificial feature disposed between the lowermost sacrificial feature and the uppermost sacrificial feature, the set of the channel features including a first semiconductor material (Paragraph [0018]), the set of the sacrificial features including a second semiconductor material different from the first semiconductor material (Paragraph [0018]), so as to permit each sacrificial feature of the set of the sacrificial features to have an etching selectivity that is greater than an etching selectivity of each channel feature of the set of the channel features (Paragraph [0018]), the intermediate sacrificial feature of the set of the sacrificial features to have an etching selectivity that is greater than an etching selectivity of the other sacrificial features of the set of the sacrificial features (Paragraph [0018]);
forming a plurality of dummy poly gates (218) on the stack portions, respectively;
removing the one intermediate sacrificial feature to form a gap between the lowermost sacrificial feature and the uppermost sacrificial feature of each of the stack portions (Paragraph [0025]);
removing two opposite side portions of each of the other sacrificial features of the set of the sacrificial features to form a plurality of recesses, each pair of the recesses being formed at two opposite sides of a corresponding one sacrificial feature of the other sacrificial features of the set of the sacrificial features (Paragraph [0025]);
forming an intermediate isolation feature (Fig. 5, 226M) to fill the gap;
forming a plurality of inner spacers (226) to respectively fill the recesses;
forming a plurality of lower source/drain portions (Fig. 7, 230) in the source/drain trenches, respectively;
forming a plurality of middle isolation features (234) to cover the lower source/drain portions in the source/drain trenches, respectively; and
forming a plurality of upper source/drain portions (240) to cover the middle isolation features in the source/drain trenches, respectively.
Shih does not explicitly disclose a sacrificial feature including an n-type dopant, or p-type dopant, impurity or combination thereof to an sacrificial layer to have a greater etch selectivity than other sacrificial layers. However Lee discloses a semiconductor device comprising:
A stack pattern (Fig. 7a-7d, STP) having alternating sacrificial layers (SAL) and active layers (ACL) wherein the sacrificial layer can be formed with a dopant such as a p-type or n-type dopants (gallium, indium, phosphorus, arsenic, antimony) to adjust the etch selectivity to be greater than that of an undoped sacrificial layer (Paragraph 0094-0099]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the sacrificial layer with a p-type or n-type dopant because it will adjust the etch selectivity of the layer to be faster than an undoped sacrificial layer and will prevent epi defect from occurring due to different in lattice constant improving device reliability and ensure excellent electrical characteristics (Paragraph [0098 & 0099]).
Regarding claim 3, 5, 7-8, Shih and Lee disclose all of the limitations of claim 1, 2, 4, & 6 (addressed above). Lee further discloses:
The stacked pattern can included a dopant layer as sacrificial sublayer (SAL1) as shown in Fig. 7c-7d sandwiched between sacrificial layer (SAL2) wherein sacrificial SAL1 can be silicon-germanium-dopant layer including n-type or p-type dopants and the sacrificial layer SAL2 is silicon germanium (Paragraph [0104]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the sacrificial layer with a p-type or n-type dopant because it will adjust the etch selectivity of the layer and will prevent epi defect from occurring due to different in lattice constant improving device reliability and ensure excellent electrical characteristics (Paragraph [0098 & 0099]).
Regarding claim 11, Shih further discloses:
each sacrificial feature of the set of the sacrificial features includes silicon germanium and a concentration of germanium in the one intermediate sacrificial feature being greater than a concentration of germanium in each sacrificial feature of the other sacrificial features of the set of the sacrificial features (Paragraph [0018]).
Shih does not discloses the sacrificial layer including dopant which include boron, aluminum, gallium, indium or combinations thereof. However Lee discloses a semiconductor device comprising:
A stack pattern (Fig. 7a-7d, STP) having alternating sacrificial layers (SAL) and active layers (ACL) wherein the sacrificial layer can be formed with a dopant such as a p-type or n-type dopants (gallium, indium, phosphorus, arsenic, antimony) to adjust the etch selectivity to be greater than that of an undoped sacrificial layer (Paragraph 0094-0099]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the sacrificial layer with a p-type or n-type dopant because it will adjust the etch selectivity of the layer to be faster than an undoped sacrificial layer and will prevent epi defect from occurring due to different in lattice constant improving device reliability and ensure excellent electrical characteristics (Paragraph [0098 & 0099]).
Regarding claim 13 & 15, Shih discloses a semiconductor device comprising:
forming a plurality of stack portions (Fig. 2 & 3, 204T & 204B) on a semiconductor substrate (202) in a first direction normal to the semiconductor substrate, the stack portions being spaced apart from each other by a plurality of source/drain trenches (Fig. 5, 224) which are disposed to alternate with the stack portions in a second direction parallel to the semiconductor substrate and transverse to the first direction, each of the stack portions including a set of channel features (208) and a set of sacrificial features (206) disposed to alternate with the set of the channel features in the first direction, the set of the channel features including a lowermost channel feature (lowermost 208), an uppermost channel feature (uppermost 208), and at least one intermediate channel feature (206M) disposed between the lowermost channel feature and the uppermost channel feature, the set of the sacrificial features including a lowermost sacrificial feature (lowermost (206), an uppermost sacrificial feature (uppermost 206), and at least one intermediate sacrificial feature disposed between the lowermost sacrificial feature and the uppermost sacrificial feature, the set of the channel features including a first semiconductor material (Paragraph [0018]), the set of the sacrificial features including a second semiconductor material different from the first semiconductor material (Paragraph [0018]), so as to permit each sacrificial feature of the set of the sacrificial features to have an etching selectivity that is greater than an etching selectivity of each channel feature of the set of the channel features (Paragraph [0018]), the intermediate sacrificial feature of the set of the sacrificial features to have an etching selectivity that is greater than an etching selectivity of the other sacrificial features of the set of the sacrificial features (Paragraph [0018]);
forming a plurality of dummy poly gates (218) on the stack portions, respectively;
removing the one intermediate sacrificial feature to form a gap between the lowermost sacrificial feature and the uppermost sacrificial feature of each of the stack portions (Paragraph [0025]);
removing two opposite side portions of each of the other sacrificial features of the set of the sacrificial features to form a plurality of recesses, each pair of the recesses being formed at two opposite sides of a corresponding one sacrificial feature of the other sacrificial features of the set of the sacrificial features (Paragraph [0025]);
forming an intermediate isolation feature (Fig. 5, 226M) to fill the gap;
forming a plurality of inner spacers (226) to respectively fill the recesses;
forming a plurality of lower source/drain portions (Fig. 7, 230) in the source/drain trenches, respectively;
forming a plurality of middle isolation features (234) to cover the lower source/drain portions in the source/drain trenches, respectively; and
forming a plurality of upper source/drain portions (240) to cover the middle isolation features in the source/drain trenches, respectively.
Removing the dummy poly gates and the other sacrificial features of the set of the sacrificial features to form a plurality of cavities (Fig. 12 & 13; Paragraph [0031]).
Forming a gate feature (Fig. 26, 260/264) in each of the cavities.
Shih does not explicitly disclose a sacrificial feature including an n-type dopant, or p-type dopant, impurity or combination thereof to an sacrificial layer to have a greater etch selectivity than other sacrificial layers. However Lee discloses a semiconductor device comprising:
A stack pattern (Fig. 7a-7d, STP) having alternating sacrificial layers (SAL) and active layers (ACL) wherein the sacrificial layer can be formed with a dopant such as a p-type or n-type dopants (gallium, indium, phosphorus, arsenic, antimony) to adjust the etch selectivity to be greater than that of an undoped sacrificial layer (Paragraph 0094-0099]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the sacrificial layer with a p-type or n-type dopant because it will adjust the etch selectivity of the layer to be faster than an undoped sacrificial layer and will prevent epi defect from occurring due to different in lattice constant improving device reliability and ensure excellent electrical characteristics (Paragraph [0098 & 0099]).
Regarding claim 14, Shih further discloses:
the gap and the recesses are formed simultaneously, so that the intermediate isolation feature and the inner spacers are formed simultaneously (Paragraph [0025]).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shih (Pre-Grant Publication 2024/0312846) in view of Chen (Chinese Publication CN10326764).
Regarding claim 12, Shih disclose all of the limitations of claim 1 (addressed above). Shih does not disclose an impurity including carbon, nitrogen, oxygen or combinations thereof. However Chen discloses a semiconductor device comprising:
A sacrificial layer (Fig. 2, 110) comprising a carbon-doped silicon germanium material (Paragraph [0039]).
It would have been obvious to those having ordinary skill in the art at the time of invention to form the sacrificial layer to be doped with an impurity such carbon because it will allow for greater etch selectivity between the sacrificial layer and channel semiconductor layer and the channel layer will suffer less damage and fewer defects to reduce leakage current (Paragraph [0039]).
Claim(s) 19 & 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xie (Pre-Grant Publication 2024/0203990) in view of Van dal (Pre-Grant Publication 2024/0222429).
Regarding claim 19 & 20, Xie disclose all of the limitations of claim 18 (addressed above). Xie does not disclose the second dielectric material is different from the third dielectric material or the first pair of inner spacers has a first thickness and the second pair of the inner spacers has a second thickness that is different from the first thickness. However Van dal disclose a semiconductor device comprising:
Forming spacers (Fig. 21, 135) next to upper sacrificial layer (103b) and lower spacers (140) next to lower sacrificial layer (102b) wherein the spacers can be different materials from each other (Paragraph [0080]) and the spacers can be different dimensions such that the gate lengths can be independently tuned and the first pair can have a thickness different than second pair (Paragraph [0080]).
It would have been obvious o those having ordinary skill in the art at the time of invention to form second dielectric material of the first pair of the inner spacer to be different from the third dielectric material of the second pair and to form the spacers having different dimensions because it will allow the spacers to be independently and separately formed to improve the performance of the CFET device (Paragraph [0080]).
Allowable Subject Matter
Claims 9-10 & 16-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 9 is considered allowable because none of the prior art either alone or combination discloses the gap is formed before formation of the recesses, so that the intermediate isolation feature is formed before formation of the inner spacers. Claim 10 is also considered allowable based on its dependency from claim 9.
Claim 16 is considered allowable because none of the prior art either alone or combination discloses wherein each sacrificial feature of the other sacrificial features of the set of the sacrificial features includes the p-type dopant including boron, aluminum, gallium, indium, or combinations thereof, and a concentration of the p-type dopant in the uppermost sacrificial feature of the other sacrificial features of the set of the sacrificial features is higher than a concentration of the p-type dopant in remaining sacrificial features of the other sacrificial features of the set of the sacrificial features, so that one of the inner spacers formed to laterally cover the uppermost sacrificial feature has a thickness that is less than a thickness of each of the inner spacers formed to laterally cover the remaining sacrificial features of the other sacrificial features of the set of the sacrificial features.
Claim 17 is considered allowable because none of the prior art either alone or combination discloses wherein the at least one intermediate sacrificial feature includes a first intermediate sacrificial feature and a second intermediate sacrificial feature disposed between the uppermost sacrificial feature and the first intermediate sacrificial feature, each of the lowermost sacrificial feature and the first intermediate sacrificial feature including the p-type dopant which includes boron, aluminum, gallium, indium, or combinations thereof, the second intermediate sacrificial feature including the n-type dopant which includes phosphorus, arsenic, antimony, or combinations thereof, so that one of the inner spacers formed to laterally cover the uppermost sacrificial feature has a thickness which is greater than a thickness of one of the inner spacers formed to laterally cover the first intermediate sacrificial feature and which is greater than a thickness of one of the inner spacers formed to laterally cover the lowermost sacrificial feature.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shen (Pre-Grant Publication 2025/0234623) discloses a gate all around having a multiple gate lengths.
Kim (Pre-Grant Publication 2024/0266350) discloses a CFET device comprising a barrier layer wherein the barrier layer can have a thicker portion between an lower and upper source/drain region.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRANDON C FOX whose telephone number is (571)270-5016. The examiner can normally be reached M-F 9:00AM-6:00PM.
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/BRANDON C FOX/Examiner, Art Unit 2818
/DAVID VU/Primary Examiner, Art Unit 2818
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