DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot.
Claim 18 does not claim multiple vias in the dielectric layer coupled to a common pad.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 18,20-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 20160379915 A1; Lee).
Regarding claim 18, Lee discloses a semiconductor device comprising: a redistribution structure comprising: a first external connector (Fig. 1, 122; ¶31) at a first side (top) of the redistribution structure (Fig. 1, 113; ¶31); a first dielectric layer (Fig. 1, 111; ¶30) at a second side (bottom) of the redistribution structure opposite to the first side of the redistribution structure; a first conductive via (Fig. 2A, 112; ¶60) and a second conductive via (Fig. 2A, second 112; ¶60) extending through the first dielectric layer; one or more seed layers (Fig. 2A, 117a; ¶60) contacting the first conductive via (Fig. 2A, 112; ¶60) and the second conductive via (Fig. 2A, second 112; ¶60); and a conductive pad (Figs.1/ 2A, 117; ¶60) contacting the one or more seed layers, wherein the conductive pad and the first conductive via are disposed on opposing sides of the one or more seed layers (Fig. 2A, 117a; ¶60); a first semiconductor component (Fig. 1, 120; ¶26) bonded to the first external connector (Fig. 1, 122; ¶31); and an encapsulant (Fig. 1, 140; ¶26) encapsulating the first semiconductor component.
Regarding claim 20, Lee discloses the semiconductor device of claim 18, wherein the first dielectric layer (Fig. 1, 111; ¶30) overlaps a surface of the conductive pad (Figs.1/ 2A, 117; ¶60) that is in contact with the one or more seed layers. (Fig. 2A, 117a; ¶60)
Regarding claim 21, Lee discloses the semiconductor device of claim i8, wherein the first conductive via (Fig. 2A, 112; ¶60) has a first width at an interface between the first conductive via and the one or more seed layers (Fig. 2A, 117a; ¶60), wherein the conductive pad (Figs.1/ 2A, 117; ¶60) has a second width at an interface between the conductive pad and the one or more seed layers, and wherein the second width is greater than the first width.
Allowable Subject Matter
Claims 1-17 are allowed.
The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14).
The art discloses the claimed dielectric layer on the bottom of a redistribution structure comprising a plurality of conductive vias , where each via is connected to a respective pad. In light of the disclosure it is clear that the claims should be interpreted as multiple vias in the claimed dielectric layer on a common conductive pad. The relevant art does not discloses this feature in combination with the rest of the claimed limitations.
Regarding claim 1, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " and a conductive pad connected to each of the plurality of conductive vias, wherein a dielectric material of the first dielectric layer is disposed between the plurality of conductive vias;”, as recited in Claim 1, with the remaining features.
Regarding claim 11, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to the skilled artisan, the instant invention regarding: " a first conductive via and a second conductive via extending through the first dielectric layer; and a conductive pad connected to the first conductive via and to the second conductive via”, as recited in Claim 11, with the remaining features.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAWRENCE C TYNES JR. whose telephone number is (571)270-7606. The examiner can normally be reached 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at 571-272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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