DETAILED ACTION
Election/Restriction
Restriction to one of the following inventions is required under 35 U.S.C. 121:
I. Claims 1-10, drawn to a semiconductor structure, classified in H10D84/83.
II. Claims 11-20, drawn to a manufacturing method of a semiconductor structure, classified in H10W20/42.
The inventions are independent or distinct, each from the other because:
Inventions II and I are related as process of making and product made. The inventions are distinct if either or both of the following can be shown: (1) that the process as claimed can be used to make another and materially different product or (2) that the product as claimed can be made by another and materially different process (MPEP § 806.05(f)). In the instant case the process as claimed can be used to make another and materially different product such the product claims recite the first conductive layer does not extend into the low voltage, but process claims fail to teach steps.
Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not required because one or more of the following reasons apply:
Applicant is advised that the reply to this requirement to be complete must include (i) an election of an invention to be examined even though the requirement may be traversed (37 CFR 1.143) and (ii) identification of the claims encompassing the elected invention.
The election of an invention may be made with or without traverse. To reserve a right to petition, the election must be made with traverse. If the reply does not distinctly and specifically point out supposed errors in the restriction requirement, the election shall be treated as an election without traverse. Traversal must be presented at the time of election in order to be considered timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are added after the election, applicant must indicate which of these claims are readable upon the elected invention.
Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention.
(a) the inventions have acquired a separate status in the art in view of their different classification;
(b) the inventions have acquired a separate status in the art due to their recognized divergent subject matter;
(c) the inventions require a different field of search (for example, searching different classes/subclasses or electronic resources, or employing different search queries);
(d) the prior art applicable to one invention would not likely be applicable to another invention;
(e) the inventions are likely to raise different non-prior art issues under 35 U.S.C. 101 and/or 35 U.S.C. 112, first paragraph.
During a telephone conversation with Mr. Roger Chen on July 14, 2026 a provisional election was made without traverse to prosecute the invention of II, claims 1-10. Affirmation of this election must be made by applicant in replying to this Office action. Claims 11-20 are withdrawn from further consideration by the examiner, 37 CFR 1.142(b), as being drawn to a non-elected invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 8-10are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sengupta et al. (Sengupta, US 2020/0135735 A1).
Regarding claim 1, Sengupta shows a semiconductor structure (FIGS. 3-5 and [0071]) comprising a substrate (substrate 202 as shown in FIG. 2B), on which a first medium high voltage device region (transistor 244 and 208-VDD in FIG. 5 and [0071]) and a low voltage device region (transistor 239 and 208-GND in FIG. 5 and [0071]) are defined adjacent to each other (see FIG. 3-5 respectively), wherein the first medium high voltage device region comprises a first gate contact ([0068-0072] and FIG. 3-5) and a first source/drain contact ([0071]), and the low voltage device region comprises two second source/drain contacts and a second gate contact ([0071]), wherein the second gate contact is located between the two second source/drain contacts and directly contacts the two second source/drain contacts ([0071] and FIG. 3-5); a first conductive layer (conductive layer 234 in FIG. 4) located in the first medium/high voltage device region and electrically connected to the first gate contact or the first source/drain contact ([0071]), wherein the first conductive layer does not extend into the low voltage device region (see FIG. 4); and a second conductive layer (conductive layer 28 as shown in FIG. 2B) located above the first conductive layer and spanning the first medium high voltage device region and the low voltage device region, wherein the second conductive layer is electrically connected with the first conductive layer (see FIG. 2B with respect to FIG. 3-5).
Regarding claim 2, Sengupta shows a semiconductor structure (FIGS. 3-5 and [0071]) comprising, wherein the first medium/high voltage device (transistor 244 and 208-VDD in FIG. 5 and [0071]) region further comprises a first gate structure spanning a diffusion region ([0058]), wherein the first gate contact is electrically connected to the first gate structure, and the first source/drain contact ([0071]) is electrically connected to the diffusion region 9[0058]).
Regarding claim 3, Sengupta shows a semiconductor structure (FIGS. 3-5 and [0071]) comprising, wherein the low voltage device region further comprises a second gate structure (see FIG. 4) spanning a plurality of fin structures, and the second source/drain contact ([0071]) is electrically connected with the plurality of fin structures (see FIG. 4).
Regarding claim 4, Sengupta shows a semiconductor structure (FIGS. 3-5 and [0071]) comprising, wherein a top surface of the second gate contact (FIG. 4) is aligned with the top surfaces of the two second source/drain contacts ([0071]).
Regarding claim 5, Sengupta shows a semiconductor structure (FIGS. 3-5 and [0071]) comprising, wherein a conductive material layer is not included in the low voltage device region (transistor 239 and 208-GND in FIG. 5 and [0071]) at the same level as the first conductive layer (see FIG. 4).
Regarding claim 6, Sengupta shows a semiconductor structure (FIGS. 3-5 and [0071]) comprising, wherein the second conductive layer extends into the low voltage device region and is located directly above at least one second source/drain contact ([0071]).
Regarding claim 8, Sengupta shows a semiconductor structure (FIGS. 3-5 and [0071]) further comprising a second medium/high voltage device region ([0071]), wherein the low voltage device region is located between the first medium/high voltage device region and the second medium/high voltage device region ( FIG. 4-5), and the low voltage device region is directly adjacent to the first medium/high voltage device region and the second medium/high voltage device region ([0071] and [FIG. 4-5).
Regarding claim 9, Sengupta shows a semiconductor structure (FIGS. 3-5 and [0071]) comprising, wherein the devices comprised in the second medium high voltage device region and the devices comprised in the first medium/high voltage device region are arranged in mirror images with each other ([0071]).
Regarding claim 10, Sengupta shows a semiconductor structure (FIGS. 3-5 and [0071]) comprising, wherein the first source/drain contact in the first medium/high voltage device region is directly adjacent to one of the second source/drain contacts ([0071] and FIG. 3-5) in the low voltage device region when viewed from a cross section (see FIG. 3-5).
Allowable Subject Matter
Claims 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ELIAS ULLAH/ Primary Examiner, Art Unit 2893
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