DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 8-10are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sengupta et al. (Sengupta, US 2020/0135735 A1).
Regarding claim 1, Sengupta shows a semiconductor structure (FIGS. 3-5 and [0071]) comprising a substrate (substrate 202 as shown in FIG. 2B), on which a first medium high voltage device region (transistor 244 and 208-VDD in FIG. 5 and [0071]) and a low voltage device region (transistor 239 and 208-GND in FIG. 5 and [0071]) are defined adjacent to each other (see FIG. 3-5 respectively), wherein the first medium high voltage device region comprises a first gate contact ([0068-0072] and FIG. 3-5) and a first source/drain contact ([0071]), and the low voltage device region comprises two second source/drain contacts and a second gate contact ([0071]), wherein the second gate contact is located between the two second source/drain contacts and directly contacts the two second source/drain contacts ([0071] and FIG. 3-5); a first conductive layer (conductive layer 234 in FIG. 4) located in the first medium/high voltage device region and electrically connected to the first gate contact or the first source/drain contact ([0071]), wherein the first conductive layer does not extend into the low voltage device region (see FIG. 4); and a second conductive layer (conductive layer 28 as shown in FIG. 2B) located above the first conductive layer and spanning the first medium high voltage device region and the low voltage device region, wherein the second conductive layer is electrically connected with the first conductive layer (see FIG. 2B with respect to FIG. 3-5).
Regarding claim 2, Sengupta shows a semiconductor structure (FIGS. 3-5 and [0071]) comprising, wherein the first medium/high voltage device (transistor 244 and 208-VDD in FIG. 5 and [0071]) region further comprises a first gate structure spanning a diffusion region ([0058]), wherein the first gate contact is electrically connected to the first gate structure, and the first source/drain contact ([0071]) is electrically connected to the diffusion region 9[0058]).
Regarding claim 3, Sengupta shows a semiconductor structure (FIGS. 3-5 and [0071]) comprising, wherein the low voltage device region further comprises a second gate structure (see FIG. 4) spanning a plurality of fin structures, and the second source/drain contact ([0071]) is electrically connected with the plurality of fin structures (see FIG. 4).
Regarding claim 4, Sengupta shows a semiconductor structure (FIGS. 3-5 and [0071]) comprising, wherein a top surface of the second gate contact (FIG. 4) is aligned with the top surfaces of the two second source/drain contacts ([0071]).
Regarding claim 5, Sengupta shows a semiconductor structure (FIGS. 3-5 and [0071]) comprising, wherein a conductive material layer is not included in the low voltage device region (transistor 239 and 208-GND in FIG. 5 and [0071]) at the same level as the first conductive layer (see FIG. 4).
Regarding claim 6, Sengupta shows a semiconductor structure (FIGS. 3-5 and [0071]) comprising, wherein the second conductive layer extends into the low voltage device region and is located directly above at least one second source/drain contact ([0071]).
Regarding claim 8, Sengupta shows a semiconductor structure (FIGS. 3-5 and [0071]) further comprising a second medium/high voltage device region ([0071]), wherein the low voltage device region is located between the first medium/high voltage device region and the second medium/high voltage device region ( FIG. 4-5), and the low voltage device region is directly adjacent to the first medium/high voltage device region and the second medium/high voltage device region ([0071] and [FIG. 4-5).
Regarding claim 9, Sengupta shows a semiconductor structure (FIGS. 3-5 and [0071]) comprising, wherein the devices comprised in the second medium high voltage device region and the devices comprised in the first medium/high voltage device region are arranged in mirror images with each other ([0071]).
Regarding claim 10, Sengupta shows a semiconductor structure (FIGS. 3-5 and [0071]) comprising, wherein the first source/drain contact in the first medium/high voltage device region is directly adjacent to one of the second source/drain contacts ([0071] and FIG. 3-5) in the low voltage device region when viewed from a cross section (see FIG. 3-5).
Allowable Subject Matter
Claims 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed on 8/18/ 2026 have been fully considered but they are not persuasive. In the remarks page 4, Applicants assert that the reference of the record does not disclose different operating voltage level more specifically medium/high voltage. However, the terms of operating voltage of medium/high are considered to be any range without defining specific voltage value. It also noted that applicants’ limitations may be appearing in the specification but not recited in the claim should not be read into the claim. E-Pass Techs., Inc. v. 3Com Corp., 343 F.3d1364, 1369, 67 USPQ2d 1947, 1950 (Fed. Cir. 2003) (claims must be interpreted “in view of the specification” without importing limitations from the specification into the claims unnecessarily). In re Prater, 415 F.2d 1393, 1404-05, 162 USPQ 541, 550-551 (CCPA 1969). See also In re Zletz, 893 F.2d 319, 321-22, 13 USPQ2d 1320, 1322 (Fed. Cir. 1989). See MPEP 2111.04.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST.
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/ELIAS ULLAH/ Primary Examiner, Art Unit 2893
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