Prosecution Insights
Last updated: July 17, 2026
Application No. 18/617,963

METHOD FOR FORMING CAULKING LAYER, METHOD OF MANUFACTURING ELECTRONIC DEVICE AND SEMICONDUCTOR DEVICE THEREOF

Non-Final OA §103
Filed
Mar 27, 2024
Examiner
NGUYEN, KHIEM D
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
1911 granted / 2229 resolved
+25.7% vs TC avg
Moderate +12% lift
Without
With
+12.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
54 currently pending
Career history
2272
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
69.9%
+29.9% vs TC avg
§102
17.2%
-22.8% vs TC avg
§112
9.0%
-31.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 2229 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: Method for forming a caulking layer including irradiating the caulking layer with ultraviolet rays or heating, method of manufacturing electronic device and semiconductor device thereof. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1 and 3-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over TW-1223869-B in view of Komino (U.S. Pub. 2001/0054484). In re claim 1, TW-1223869-B discloses a method for forming a caulking layer, comprising placing a substrate 101 and the substrate 101 has a patterned recess (151,152) (see page 2 and figs. 1-2); using a caulking device to inject or deposit a flowable sealant 201 into the patterned recess (151,152) to form a caulking layer (see page 2 and fig. 2); and irradiating the caulking layer 201 with ultraviolet rays or heating the caulking layer 201 to solidify the caulking layer 201 in the patterned recess (baked and hardened) (see page 2 and fig. 2). PNG media_image1.png 442 680 media_image1.png Greyscale TW-1223869-B is silent to wherein placing the substrate including placing a substrate into a processing chamber, wherein the processing chamber comprises a carrying platform and a caulking device, the carrying platform is configured to carry a substrate. However, Komino discloses a method for forming a caulking layer, including, inter-alia, placing a substrate W into a processing chamber (3a-3d), wherein the processing chamber (3a-3d) comprises a carrying platform 4a-4d and a caulking device (for deposition), the carrying platform 4a-4d is configured to carry a substrate W (see paragraphs [0033], [0040], [0041] and figs. 1 and 2A-B). Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Komino into the method for forming the caulking layer of TW-1223869-B in order to enable the step of placing a substrate into a processing chamber, wherein the processing chamber comprises a carrying platform and a caulking device, the carrying platform is configured to carry a substrate in TW-1223869-B to be performed because Komino suggested that it is well-known in the art to use a processing chamber that comprises a carrying platform that is configured to carrier the substrate and a caulking device for depositing the caulking layer. Additionally, the technique provides an improvement of deposition properties of the substrate (see paragraphs [0007], [0009] of Komino). Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id. In re claim 3, as applied to claim 1 above, TW-1223869-B in combination with Komino discloses wherein the caulking device comprises a vapor deposition device, and the flowable sealant is formed on the substrate by a flowable chemical vapor deposition method (see paragraph [0071] of Komino). In re claim 4, as applied to claim 1 above, TW 1223869 in combination with Komino discloses wherein the flowable sealant comprises light-curable sealant (see page 2 and fig. 2 of TW-1223869-B). In re claim 5, as applied to claim 1 above, TW 1223869 in combination with Komino discloses wherein the flowable sealant comprises a thermal-curable sealant (see page 2 and fig. 2 of TW-1223869-B). Claim(s) 7-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pan et al. (U.S. Pub. 2022/0320088) in view of TW-1223869-B). In re claim 7, Pan discloses a method of manufacturing an electronic device, comprising forming a semiconductor device (gate-all around transistors) on a substrate 206 (see paragraphs [0016], [0061] and fig. 8); covering the semiconductor device with a patterned dielectric layer 260, the patterned dielectric layer 260 having a patterned recess 230A-230C, a depth of the patterned recess 230A-230C being greater than a width of the patterned recess (see paragraphs [0026], [0028] and fig. 8); injecting or depositing a flowable sealant 280 into the patterned recess 230A-230C (see paragraph [0031] and figs. 8 and 29). PNG media_image2.png 766 869 media_image2.png Greyscale Pan is silent to injecting or depositing a flowable sealant into the patterned recess to form a caulking layer; and irradiating the caulking layer with ultraviolet rays or heating the caulking layer to solidify the caulking layer in the patterned recess. However, TW-1223869-B discloses in a same field of endeavor, a method of manufacturing an electronic device 100, including, inter-alia, injecting or depositing a flowable sealant 201 into the patterned recess (151,152) to form a caulking layer; and irradiating the caulking layer 201 with ultraviolet rays or heating the caulking layer 201 to solidify the caulking layer in the patterned recess (151,152) (baked and hardened) (see page 2 and fig. 2). Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by TW-1223869-B into the method of manufacturing the semiconductor device of Pan in order to enable the process of injecting or depositing a flowable sealant into the patterned recess to form a caulking layer; and irradiating the caulking layer with ultraviolet rays or heating the caulking layer to solidify the caulking layer in the patterned recess in Pan to be performed because in order to make the surface of the caulking layer a hydrophilic surface and further to improve performance of the semiconductor device. Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id. In re claim 8, as applied to claim 7 above, Pan in combination with TW-1223869-B discloses wherein the flowable sealant is formed on the substrate by spin coating (see paragraph [0017] of Pan). In re claim 9, as applied to claim 7 above, Pan in combination with TW-1223869-B discloses wherein the flowable sealant is formed on the substrate by a flowable chemical vapor deposition method (see paragraph [0021] of Pan). In re claim 10, as applied to claim 7 above, Pan in combination with TW-1223869-B discloses wherein the flowable sealant comprises a light-curable sealant (see page 2 and fig. 2 of TW-1223869-B). In re claim 11, as applied to claim 7 above, Pan in combination with TW-1223869-B discloses wherein the flowable sealant comprises a thermal-curable sealant (see page 2 and fig. 2 of TW-1223869-B). In re claim 12, as applied to claim 7 above, Pan in combination with TW-1223869 -B discloses wherein the semiconductor device comprises at least one fin 206’ (see paragraph [0016] and figs. 2 and 29 of Pan) and a gate structure 370 disposed on the fin 206’ (see paragraph [0053] and figs. 24 and 29 of Pan), the gate structure 370 comprises a trench, and the patterned recess and the caulking layer 280 are formed in the trench (see paragraphs [0031], [0065] and figs. 24 and 29 of Pan). In re claim 13, as applied to claim 12 above, Pan in combination with-TW 1223869-B discloses wherein the patterned dielectric layer 260 serves as a cut metal gate isolation structure (see paragraph [0026] and figs. 7 and 29 of Pan). In re claim 14, as applied to claim 12 above, Pan in combination with-TW 1223869-B discloses wherein the gate structure comprises a gate electrode layer 374, the trench exposes two opposite sidewalls and a bottom surface of the gate electrode layer 374, and the patterned recess is disposed along the two opposite sidewalls of the gate electrode layer 374 and covers the bottom surface (see paragraph [0053] and figs. 24 and 29 of Pan). In re claim 15, as applied to claim 14 above, Pan in combination with TW-1223869-B discloses wherein the patterned dielectric layer 260 serves as a cut metal gate isolation structure (see paragraph [0026] and figs. 7 and 29 of Pan). In re claim 16, Pan discloses a semiconductor device, comprising a substrate 206 having a fin 206’ (see paragraph [0016] and figs. 2 and 29); a gate structure disposed on the fin 206’, the gate structure comprising a gate electrode layer 370 (see paragraph [0053] and figs. 24 and 29), a plurality of semiconductor layers 220 (see paragraph [0017] and figs. 2 and 29) and a plurality of gate dielectric layers 372 (see paragraph [0053] and figs. 24 and 29), wherein the semiconductor layers 220 are disposed in the gate electrode layer 370, and the semiconductor layers 220 are stacked on each other and arranged at intervals, the gate dielectric layers 372 cover the semiconductor layers 220 and are electrically isolated between the gate electrode layer 370 and the semiconductor layers 220, wherein the gate electrode layer 370 has a trench extended downward from a top of the gate electrode layer 370 to expose two opposite sidewalls and a bottom surface of the gate electrode layer 370 (see paragraph [0053] and figs. 24 and 29); a patterned dielectric layer 260 disposed along the opposite sidewalls of the gate electrode layer 370 and covers the bottom surface of the gate electrode layer 370 (see paragraphs [0026] and figs. 7 and 29). Pan is silent to wherein a flowable sealant injected or deposited into the trench to form a caulking layer. However, TW-1223869-B discloses in a same field of endeavor, a semiconductor device, including, inter-alia, wherein a flowable sealant 201 injected or deposited into the trench to form a caulking layer (see page 2 and fig. 2). Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by TW-1223869-B into the semiconductor device of Pan in order to enable wherein a flowable sealant injected or deposited into the trench to form a caulking layer in Pan to be performed in order to make the surface of the caulking layer a hydrophilic surface and further to improve performance of the semiconductor device. Furthermore, it would have been obvious because all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the invention. KSR International Co. v. Teleflex Inc. (KSR), 550 U.S. 398 (2007). “If a technique has been used to improve one device, and a person of ordinary skill in the art would recognize that it would improve similar devices in the same way, using the technique is obvious unless its actual application is beyond that person’s skill.” Id. In re claim 17, as applied to claim 16 above, Pan in combination with TW-1223869-B discloses wherein the caulking layer is irradiated with ultraviolet rays or heated to solidify the caulking layer (baked and hardened) (see fig. 2 and related texts of TW-1223869-B). In re claim 18, as applied to claim 16 above, Pan in combination with TW-1223869-B discloses wherein the caulking layer is made of a light-curable or thermal-curable organic polymer insulation material (see fig. 2 and related texts of TW-1223869-B). In re claim 19, as applied to claim 16 above, Pan in combination with TW-1223869-B discloses wherein the patterned dielectric layer 260 serves as a cut metal gate isolation structure (see paragraph [0026] and figs. 7 and 29 of Pan). In re claim 20, as applied to claim 16 above, Pan in combination with TW-1223869-B discloses wherein the flowable sealants is selected from a group consisting of epoxy resin, polyester resin, vinyl ester, bismaleamide, thermosetting polyimide and cyanate ester (see page 2 and fig. 2 of TW-1223869-B). Additionally, it has been held to be within the general skill of a worker in the art to select a known material on the basis of it suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416. Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over TW-1223869-B in view of Komino (U.S. Pub. 2001/0054484), as applied to claim 1 above, and further in view of Cui et al. (U.S. Pub. 2022/0080758). In re claim 2, as applied to claim 1 above, TW-1223869-B and Komino are silent to wherein the caulking device comprises a glue dispenser, and the flowable sealant is formed on the substrate by spin coating. However, Cui discloses in a same field of endeavor, a method for forming a caulking layer, including, inter-alia, wherein the caulking device comprises a glue dispenser (see paragraphs [0002], [0007], [0032]), and the flowable sealant is formed on the substrate by spin coating (see paragraph [0003]). Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Cui into the method for forming a caulking layer in TW-1223869-B in order to enable wherein the caulking device comprises a glue dispenser, and the flowable sealant is formed on the substrate by spin coating in TW-1223869-B to be performed because in doing so the glue dispensing air pressure and the glue dispensing amount can be effectively controlled (see paragraph [0032] of Cui). Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over TW-1223869-B in view of Komino (U.S. Pub. 2001/0054484), as applied to claim 1 above, and further in view of Pan (U.S Pub. 2022/0320088). In re claim 6, as applied to claim 1 above, TW-1223869-B and Komino are silent to wherein the method for forming a caulking layer further comprising forming a liner in the patterned recess before injecting or depositing the flowable sealant. However, Pan discloses in a same field of endeavor, a method for forming a caulking layer, including, inter-alia, forming a liner 235 in the patterned recess before injecting or depositing the flowable sealant 250 (see paragraphs [0021], [0022] and figs. 24 and 29). Therefore, it is respectfully submitted that it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to be motivated to incorporate the technique as taught by Pan into the method for forming a caulking layer in TW-1223869-B in order to enable wherein the method for forming a caulking layer further comprising forming a liner in the patterned recess before injecting or depositing the flowable sealant in TW-1223869-B to be performed in order to protect the sidewalls of the patterned recess. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Amepalli et al. (U.S. Patent 10,017,856) discloses a method for forming a caulking layer, including, inter-alia, placing a substrate 301 into a processing chamber 1001 (see col. 6, lines 2-15 and fig. 5A), wherein the processing chamber comprises a carrying platform and a caulking device, the carrying platform is configured to carry a substrate 301, and the substrate has a patterned recess; using the caulking device to inject or deposit a flowable sealant 310-1 into the patterned recess to form a caulking layer (see col. 7, lines 44-55 figs. 3A, 3B, and 3C). Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)272-1865. The examiner can normally be reached Monday-Friday 8:00 AM - 6:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /KHIEM D NGUYEN/Primary Examiner, Art Unit 2892
Read full office action

Prosecution Timeline

Mar 27, 2024
Application Filed
Jun 30, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12683557
AI-ASSISTED POWER AMPLIFIER OPTIMIZATION
4y 0m to grant Granted Jul 14, 2026
Patent 12685208
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
3y 0m to grant Granted Jul 14, 2026
Patent 12685190
SEMICONDUCTOR PACKAGES AND METHODS FOR FABRICATING THE SAME
2y 11m to grant Granted Jul 14, 2026
Patent 12676582
DE-SKEWING OF DIFFERENTIAL SIGNALS
2y 11m to grant Granted Jul 07, 2026
Patent 12676581
OUTPHASING AMPLIFIER
2y 6m to grant Granted Jul 07, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
98%
With Interview (+12.5%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 2229 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month