DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election with traverse of Invention Group I (encompassing claims 1-13) in the reply filed on 03/27/2024 is acknowledged. The traversal is on the ground(s) that there would not be a serious burden on the examiner if restriction was not made (see remarks mailed on 08/14/2026). This is not found persuasive because, as presented in Requirement for Restriction/Election mailed on 07/14/2026 in section 4, there are at least five reasons why there would be a serious search and/or examination burden on examiner if restriction were not required.
Thus, the requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park (US 2019/0165121 A1).
With respect to claim 1, Park discloses, in Figs.1-32, a semiconductor structure, comprising: a dielectric layer (150, 132, 133) (see Par.[0035] wherein a first interlayer insulating film 150 and a second interlayer insulating film 250); a conductive layer (166) disposed in the dielectric layer (150, 132, 134) (see Par.[0049] wherein the first gate structure G1 may include a first interface film 162, a first gate insulating film 164 and a first gate electrode 166); and at least one support pillar (164) disposed in the dielectric layer (150) and outside the conductive layer (166) (e.g., see Figs.21-32 wherein pillar 164 are formed in an outside area adjacent to conductive).
With respect to claim 2, Park discloses, in Figs.1-32, the semiconductor structure, wherein a material removal rate of the dielectric layer (150, 132, 133) is greater than a material removal rate of the support pillar (164) (see Par.[0154] wherein Referring to FIGS. 21 and 22, a first etching process having a larger etching rate with respect to the first gate structure G1 (etching rate is used for etching gate G1 and pillar 164 (see Fig.22)) than the first spacer 132 is performed).
Moreover, regarding the limitation “material removal rate”, it is submitted that such limitation does not further define the structure as instantly claimed, nor serve to distinguish over Park because it is related to the process step of “removal a material”. Therefore, the said limnitation is a “product by process” limitation. Applicant attention is thereby directed to the fact that a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al, 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Note that Applicant has the burden of proof in such cases, as the above case law make clear.
With respect to claim 3, Park discloses, in Figs.1-32, the semiconductor structure, wherein in a top view, the support pillar forms a closed pattern (see Figs.21-23).
With respect to claim 4, Park discloses, in Figs.1-32, the semiconductor structure, wherein in a top view, the support pillar forms a discontinuous pattern that comprises a plurality of segments (see Figs.21-23).
With respect to claim 5, Park discloses, in Figs.1-32, the semiconductor structure, further comprising a plurality of support pillars (164), wherein the support pillars are arranged in sequence from inside to outside with the conductive layer as a center (see Figs.21-23).
With respect to claim 9, Park discloses, in Figs.1-32, the semiconductor structure, wherein a material removal rate of the surface treatment layer is greater than a material removal rate of the dielectric layer (see Par.[0167] wherein referring to FIGS. 25 and 26, after performing the second etching process, a third etching process having a larger etching rate with respect to the first gate structure G1 than the first spacer 132 is performed).
Moreover, regarding the limitation “material removal rate”, it is submitted that such limitation does not further define the structure as instantly claimed, nor serve to distinguish over Park because it is related to the process step of “removal a material”. Therefore, the said limnitation is a “product by process” limitation. Applicant attention is thereby directed to the fact that a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al, 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Note that Applicant has the burden of proof in such cases, as the above case law make clear.
Claims 1-8 and 11-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lin et al. (US 2021/0036127 A1 hereinafter referred to as “Lin”).
With respect to claim 1, Lin discloses, in Figs.1A-7, a semiconductor structure, comprising: a dielectric layer (118, 114) (see Par.[0033]-[0034] wherein the dielectric layer 118 may be made of silicon oxide, silicon oxynitride, tetraethoxysilane, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), hydrogen silsesquioxane (HSQ), other applicable dielectric materials, or a combination thereof; see Par.[0031] wherein the sidewall spacers 114 are made of silicon nitride, silicon oxide, other applicable materials, or a combination thereof); a conductive layer (122, 128) disposed in the dielectric layer (118, 114) (see Par.[0073]-[0074] wherein the metal element of the gate electrode layer 122 may react with the oxygen of the surface of the gate dielectric layer (e.g., the surface 120a of the gate dielectric layer 120), forming a ferroelectric dead layer (not shown in the figures) between the gate dielectric layer 120 and the gate electrode layer 122; see Par.[0086]-[0090] wherein the conductive material 128 includes cobalt, titanium, aluminum, copper, tantalum, platinum, molybdenum, silver, manganese, zirconium, ruthenium, another applicable conductive material, or a combination thereof); and at least one support pillar (120) disposed in the dielectric layer (118, 114) and outside the conductive layer (122).
With respect to claim 2, Lin discloses, in Figs.1A-7, the semiconductor structure, wherein a material removal rate of the dielectric layer (118, 114) is greater than a material removal rate of the support pillar (120) (see Par.[0080] wherein in the etching process for forming the trenches O2, the etching rate of the sidewall spacers 114 is lower than the etching rate of the treated gate dielectric layers 120′ and the etching rate of the gate electrode layers 122).
Moreover, regarding the limitation “material removal rate”, it is submitted that such limitation does not further define the structure as instantly claimed, nor serve to distinguish over Lin because it is related to the process step of “removal a material”. Therefore, the said limnitation is a “product by process” limitation. Applicant attention is thereby directed to the fact that a "product by process" claim is directed to the product per se, no matter how actually made, In re Hirao, 190 USPQ 15 at 17 (footnote 3). See also In re Brown, 173 USPQ 685; In re Luck, 177 USPQ 523; In re Fessmann, 180 USPQ 324; In re Avery, 186 USPQ 161; In re Wertheim, 191 USPQ 90 (209 USPQ 554 does not deal with this issue); In re Marosi et al, 218 USPQ 289; and particularly In re Thorpe, 227 USPQ 964, all of which make it clear that it is the patentability of the final product per se which must be determined in a "product by process" claim, and not the patentability of the process, and that an old or obvious product produced by a new method is not patentable as a product, whether claimed in "product by process" claims or not. Note that Applicant has the burden of proof in such cases, as the above case law make clear.
With respect to claim 3, Lin discloses, in Figs.1A-7, the semiconductor structure, wherein in a top view, the support pillar forms a closed pattern (see Fig.2K).
With respect to claim 4, Lin discloses, in Figs.1A-7, the semiconductor structure, wherein in a top view, the support pillar (120) forms a discontinuous pattern that comprises a plurality of segments (see Fig.2G).
With respect to claim 5, Lin discloses, in Figs.1A-7, the semiconductor structure, further comprising a plurality of support pillars (120), wherein the support pillars (120) are arranged in sequence from inside to outside with the conductive layer (120) as a center (see Fig.2G).
With respect to claim 6, Lin discloses, in Figs.1A-7, the semiconductor structure, further comprising: an isolation layer (106) disposed below the dielectric layer (118, 114), wherein the support pillar (120) is connected to the isolation layer (106) (see Fig.3 wherein support pillar 120 connect to isolation 106).
With respect to claim 7, Lin discloses, in Figs.1A-7, the semiconductor structure, further comprising: an isolation layer (106) disposed below the dielectric layer (118, 114), wherein the support pillar (120) is separated from the isolation layer (106) (see Fig.2K).
With respect to claim 8, Lin discloses, in Figs.1A-7, the semiconductor structure, further comprising: a surface treatment layer (114) disposed between the conductive layer (128) and the support pillar (128) (see Fig.2K).
With respect to claim 11, Lin discloses, in Figs.1A-7, the semiconductor structure, wherein a top surface of the conductive layer is higher than a top surface of the support pillar or is aligned with the top surface of the support pillar (see Fig.2K).
With respect to claim 12, Lin discloses, in Figs.1A-7, the semiconductor structure, wherein in a top view, a shortest distance between an outermost periphery of the support pillar and the conductive layer is greater than or equal to 100 nm (see Par.[0057] wherein the gate dielectric layer 120 is relatively thin (e.g., having a thickness in a range from 10 angstrom to about 30 angstrom), the gate dielectric layer 120 may be severely negatively affected by the ferroelectric dead layer).
With respect to claim 13, Lin discloses, in Figs.1A-7, the semiconductor structure, wherein a depth of the support pillar is from 100 nm to 200 nm (see Par.[0093] wherein at least partially due to the treatment T2, the treated gate dielectric layer 120′ has a fluorine concentration profile peaking at the depth D2 from the treated surface 120a′ of the treated gate dielectric layer 120′; the ratio of the depth D2 to the thickness A2 of treated gate dielectric layer 120′ may be in a range from about 0.1 to about 0.5; the peak fluorine concentration C2 at the depth D2 may be in a range from about 3 at % to about 5 at %; the depth D2 may be in a range from about 3 angstrom to about 7 angstrom (e.g., 5 angstrom)).
Claims 1, 3-6, 8, 10-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chang et al. (US 2022/0013364 A1 hereinafter referred to as “Chang”).
With respect to claim 1, Chang discloses, in Figs.6A-22C, a semiconductor structure, comprising: a dielectric layer (66) (see Par.[0034]-[0037] wherein in FIGS. 3A through 3C, an inter-layer dielectric (ILD) 66 (e.g., ILDO layer) is deposited over the substrate 50; the ILD 66 may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, PECVD, or flowable CVD (FCVD)); a conductive layer (106) disposed in the dielectric layer (66) (see Par.[0060] wherein FIGS. 12A-12C illustrate a cut-metal gate (CMG) etching process performed to remove the exposed portions of the areas of the etch stop layer 80 and to remove the one or more target portions of the gate stacks 74 (may be referred to as the cut metal gate region of the gate stacks 74), the associated gate spacers 62 and portions of the ILD 66 in order to form CMG trenches 94; see Par.[0083] wherein CMG plugs 106 are formed from remaining material of the barrier layer 100, the silicon layer 102 (if any), and the fill material 104 disposed within the ILD 66); and at least one support pillar (62) disposed in the dielectric layer (66) and outside the conductive layer (106) (see Par.[0028]-[0030] wherein the gate spacers 62 are formed, for example, by blanket depositing a spacer layer on the previously formed structure; the spacer layer may comprise SiCON, SiN, oxynitride, SiC, SiON, SiOC, oxide, or the like and may be formed by any suitable methods to form such a layer, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), sputter, and any other suitable methods).
With respect to claim 3, Chang discloses, in Figs.6A-22C, the semiconductor structure, wherein in a top view, the support pillar (62) forms a closed pattern (see Figs.16A, 19A, 20).
With respect to claim 4, Chang discloses, in Figs.6A-22C, the semiconductor structure, wherein in a top view, the support pillar forms a discontinuous pattern that comprises a plurality of segments (see Figs.16A, 19A, 20).
With respect to claim 5, Chang discloses, in Figs.6A-22C, the semiconductor structure, further comprising a plurality of support pillars (62), wherein the support pillars are arranged in sequence from inside to outside with the conductive layer as a center (see Figs.16A, 19A, 20).
With respect to claim 6, Chang discloses, in Figs.6A-22C, the semiconductor structure, further comprising: an isolation layer (56) disposed below the dielectric layer (66), wherein the support pillar (62) is connected to the isolation layer (56) (see Par.[0020], [0028]-[0029] wherein the spacer layer may comprise a different material with different etch characteristics or the same material as the dielectric material within the STI regions 56).
With respect to claim 8, Chang discloses, in Figs.6A-22C, the semiconductor structure, further comprising: a surface treatment layer (200) disposed between the conductive layer (106/206) and the support pillar (62) (see Par.[0085]-[0086] wherein the materials and processes used to form the barrier layer 200 may be similar to the barrier layer 100 described above and the description is not repeated herein; FIGS. 17A-17C further illustrate the silicon layer 202 deposited conformally over the barrier layer 200. The silicon layer 202 may be deposited to a thickness in the range of about 5 Å to about 10 Å, on each side of the CMG trenches 94; FIGS. 17A-17C, the silicon layer 202 is deposited to a thickness of greater than or equal to about 5 Å. The materials and processes used to form the silicon layer 202 may be similar to the silicon layer 102 described above and the description is not repeated herein).
With respect to claim 10, Chang discloses, in Figs.6A-22C, the semiconductor structure, further comprising: a barrier layer (202) disposed between the conductive layer (206) and the surface treatment layer (200) (see Par.[0085]-[0086] wherein the materials and processes used to form the barrier layer 200 may be similar to the barrier layer 100 described above and the description is not repeated herein; FIGS. 17A-17C further illustrate the silicon layer 202 deposited conformally over the barrier layer 200. The silicon layer 202 may be deposited to a thickness in the range of about 5 Å to about 10 Å, on each side of the CMG trenches 94; FIGS. 17A-17C, the silicon layer 202 is deposited to a thickness of greater than or equal to about 5 Å. The materials and processes used to form the silicon layer 202 may be similar to the silicon layer 102 described above and the description is not repeated herein).
With respect to claim 11, Chang discloses, in Figs.6A-22C, the semiconductor structure, wherein a top surface of the conductive layer (206) is higher than a top surface of the support pillar or is aligned with the top surface of the support pillar (see Fig.18A).
Citation of Pertinent Prior Art
The prior art made of record (e.g., see PTO-892) and not relied upon is considered pertinent to applicant's disclosure.
Examiner’s Telephone/Fax Contacts
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF W NATALINI can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818
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