DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1, 4, 7-8, 10, and 15-18 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 21-40 of copending Application No. 19/264,924 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because application claims 1, 4, 7-8, 10, and 15-18 are anticipated by claims 21-40 of the copending Application, and it is not patentably distinct from claims 21-40 of the copending Application.
Under Examination Claims
copending Application Claims
1. A semiconductor device, comprising: a semiconductor channel;
a first source/drain electrode and a second source/drain electrode that are at a first side of the semiconductor channel and that are electrically coupled respectively to different portions of the semiconductor channel;
a gate electrode at a second side of the semiconductor channel, opposite the first side of the semiconductor channel;
a gate dielectric layer between the gate electrode and the semiconductor channel; and
a hydrogen absorption layer adjacent to the gate electrode, the first source/drain electrode, the second source/drain electrode, or a combination thereof.
Anticipated by copending Application Claim 21:
21. (New) A semiconductor device, comprising:
a first source/drain electrode and a second source/drain electrode spaced over a semiconductor substrate at a first elevation above the semiconductor substrate;
a gate electrode spaced over the semiconductor substrate at a second elevation above the semiconductor substrate;
a semiconductor channel between the first source/drain electrode and the gate electrode and between the second source/drain electrode and the gate electrode;
a gate dielectric layer between the gate electrode and the semiconductor channel; and
a first hydrogen absorption layer between the first source/drain electrode and the semiconductor channel.
4. The semiconductor device of claim 1, wherein the hydrogen absorption layer is between the gate electrode and the gate dielectric layer and shares a width with the gate electrode.
Anticipated by copending Application Claim 24:
24. (New) The semiconductor device according to claim 21, further comprising: a second hydrogen absorption layer between the gate electrode and the gate dielectric layer, wherein the second hydrogen absorption layer and the gate dielectric layer share a common width, which is greater than a width of the gate electrode and a width of the semiconductor channel.
7. The semiconductor device of claim 1, wherein the hydrogen absorption layer is between the semiconductor channel and one of the first and second source/drain electrodes and further extends along sidewalls of the one of the first and second source/drain electrodes.
Anticipated by copending Application Claims 21 and 22:
21. (New) A semiconductor device, comprising:
a first hydrogen absorption layer between the first source/drain electrode and the semiconductor channel (as claimed in claim 21) and
22. (New) The semiconductor device according to claim 21, wherein the first hydrogen absorption layer is on a sidewall of the first source/drain electrode.
8. An integrated circuit (IC) comprising a semiconductor device, wherein the semiconductor device comprises: a semiconductor channel, a gate electrode, and a gate dielectric layer that are stacked with the gate dielectric layer separating the gate electrode from the semiconductor channel; a first source/drain electrode and a second source/drain electrode respectively on different portions of the semiconductor channel; and a hydrogen absorption layer adjacent to the gate electrode and the gate dielectric layer.
Anticipated by copending Application Claim 21:
21. (New) A semiconductor device, comprising:
a first source/drain electrode and a second source/drain electrode spaced over a semiconductor substrate at a first elevation above the semiconductor substrate;
a gate electrode spaced over the semiconductor substrate at a second elevation above the semiconductor substrate;
a semiconductor channel between the first source/drain electrode and the gate electrode and between the second source/drain electrode and the gate electrode;
a gate dielectric layer between the gate electrode and the semiconductor channel; and
a first hydrogen absorption layer between the first source/drain electrode and the semiconductor channel.
10. The IC according to claim 8, further comprising: an interconnect structure overlying a semiconductor substrate and comprising a plurality of wire levels and a plurality of via levels alternatingly stacked away from the semiconductor substrate, wherein at least one of the plurality of wire levels separates the semiconductor substrate from the semiconductor device.
Anticipated by copending Application Claim 27:
27. (New) The semiconductor device according to claim 21, further comprising: an interconnect structure comprising a plurality of wire levels and a plurality of via levels that are alternatingly stacked, wherein a portion of the interconnect structure separates the first and second source/drain electrodes and the gate electrode from the semiconductor substrate.
15. A method for forming a semiconductor device, comprising:
forming a gate electrode and a hydrogen absorption layer bordering each other;
depositing a gate dielectric layer overlying the gate electrode and the hydrogen absorption layer;
depositing a semiconductor layer overlying the gate dielectric layer;
patterning the semiconductor layer to form a semiconductor channel overlying the gate electrode and the hydrogen absorption layer; and
forming a first source/drain electrode and a second source/drain electrode atop the semiconductor channel, laterally spaced from each other.
Anticipated by copending Application Claim 28:
28. (New) A method for forming a semiconductor device, comprising:
forming a dielectric layer over a substrate;
patterning the dielectric layer to form an opening;
depositing a multi-layer film overlying the dielectric layer and in the opening, wherein the multi-layer film comprises a first conductive layer, a second conductive layer, and a hydrogen absorption layer between the first and second conductive layers;
performing a planarization to clear the multi-layer film from atop the dielectric layer and to form a gate electrode in the opening, wherein a portion of the hydrogen absorption layer is embedded in the gate electrode;
depositing a gate dielectric layer over the gate electrode;
depositing a semiconductor layer over the gate dielectric layer;
patterning the semiconductor layer to form a semiconductor channel; and
forming a pair of source/drain electrodes on the semiconductor channel.
Note: the copending Application claim limitation of “a pair of source/drain electrodes” is equivalent to the claimed limitation of “a pair of source/drain electrodes.”
16. The method according to claim 15, further comprising: patterning a dielectric layer to form a gate opening, wherein the gate electrode is formed filling the gate opening, and wherein the hydrogen absorption layer is formed overlying the gate electrode and the dielectric layer.
Anticipated by copending Application Claim 28:
28. (New) A method for forming a semiconductor device, comprising:
forming a dielectric layer over a substrate; patterning the dielectric layer to form an opening; depositing a multi-layer film overlying the dielectric layer and in the opening, wherein the multi-layer film comprises a first conductive layer, a second conductive layer, and a hydrogen absorption layer between the first and second conductive layers;
performing a planarization to clear the multi-layer film from atop the dielectric layer and to form a gate electrode in the opening, wherein a portion of the hydrogen absorption layer is embedded in the gate electrode; depositing a gate dielectric layer over the gate electrode; depositing a semiconductor layer over the gate dielectric layer;
patterning the semiconductor layer to form a semiconductor channel; and
forming a pair of source/drain electrodes on the semiconductor channel.
Note: the copending Application claim limitation of “a pair of source/drain electrodes” is equivalent to the claimed limitation of “a pair of source/drain electrodes.”
17. The method according to claim 15, wherein the forming of the gate electrode and the hydrogen absorption layer comprises:
patterning a dielectric layer to form a gate opening;
depositing a barrier layer overlying the dielectric layer and lining the gate opening;
depositing the hydrogen absorption layer overlying the barrier layer and lining the gate opening;
depositing a conductive layer filling the gate opening over the hydrogen absorption layer; and
performing a planarization into the barrier layer, the hydrogen absorption layer, and the conductive layer to expose a top surface of the dielectric layer.
Anticipated by copending Application Claim 28:
28. (New) A method for forming a semiconductor device, comprising:
forming a dielectric layer over a substrate; patterning the dielectric layer to form an opening; depositing a multi-layer film overlying the dielectric layer and in the opening, wherein the multi-layer film comprises a first conductive layer, a second conductive layer, and a hydrogen absorption layer between the first and second conductive layers;
performing a planarization to clear the multi-layer film from atop the dielectric layer and to form a gate electrode in the opening, wherein a portion of the hydrogen absorption layer is embedded in the gate electrode; depositing a gate dielectric layer over the gate electrode; depositing a semiconductor layer over the gate dielectric layer;
patterning the semiconductor layer to form a semiconductor channel; and
forming a pair of source/drain electrodes on the semiconductor channel.
Note: the copending Application claim limitation of “a pair of source/drain electrodes” is equivalent to the claimed limitation of “a pair of source/drain electrodes.”
18. The method according to claim 15, wherein the forming of the gate electrode and the hydrogen absorption layer comprises:
patterning a dielectric layer to form a gate opening;
depositing the hydrogen absorption layer overlying and directly contacting the dielectric layer and further lining the gate opening;
depositing a conductive layer filling the gate opening over the hydrogen absorption layer; and
performing a planarization into the hydrogen absorption layer and the conductive layer to expose a top surface of the dielectric layer.
Anticipated by copending Application Claim 28:
28. (New) A method for forming a semiconductor device, comprising:
forming a dielectric layer over a substrate; patterning the dielectric layer to form an opening; depositing a multi-layer film overlying the dielectric layer and in the opening, wherein the multi-layer film comprises a first conductive layer, a second conductive layer, and a hydrogen absorption layer between the first and second conductive layers;
performing a planarization to clear the multi-layer film from atop the dielectric layer and to form a gate electrode in the opening, wherein a portion of the hydrogen absorption layer is embedded in the gate electrode; depositing a gate dielectric layer over the gate electrode; depositing a semiconductor layer over the gate dielectric layer;
patterning the semiconductor layer to form a semiconductor channel; and
forming a pair of source/drain electrodes on the semiconductor channel.
Note: the copending Application claim limitation of “a pair of source/drain electrodes” is equivalent to the claimed limitation of “a pair of source/drain electrodes.”
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 7-8, 11, 13-15, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bai (CN 115662999 A, hereinafter refer to Bai).
CN 115662999 A, (hereinafter refer to Bai) is relied upon solely for the English language translation of CN 115662999 A.
Regarding Claim 1: Bai discloses a semiconductor device (see Bai, Figs.3 and 5 as shown below and ¶ [0001]), comprising:
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a semiconductor channel (102/b) (see Bai, Figs.3 and 5 as shown above);
a first source/drain electrode and a second source/drain electrode that are at a first side of the semiconductor channel (102/b) and that are electrically coupled respectively to different portions of the semiconductor channel (102/b) (s see Bai, Figs.3 and 5 as shown above);
a gate electrode (g2/301) at a second side of the semiconductor channel (102/b), opposite the first side of the semiconductor channel (102/b) (see Bai, Figs.3 and 5 as shown above);
a gate dielectric layer (401) between the gate electrode (g2/301) and the semiconductor channel (102/b) (see Bai, Figs.3 and 5 as shown above); and
a hydrogen absorption layer (H2) adjacent to the gate electrode (g2/301), the first source/drain electrode, the second source/drain electrode, or a combination thereof (see Bai, Figs.3 and 5 as shown above).
Regarding Claim 2: Bai discloses a semiconductor device as set forth in claim 1 as above. Bai further teaches wherein the hydrogen absorption layer (H2) is embedded in the gate electrode (g2/301) (see Bai, Figs.3 and 5 as shown above).
Regarding Claim 3: Bai discloses a semiconductor device as set forth in claim 1 as above. Bai further teaches wherein the hydrogen absorption layer (H2) is in direct contact with the gate dielectric layer (401) (see Bai, Figs.3 and 5 as shown above).
Regarding Claim 7: Bai discloses a semiconductor device as set forth in claim 1 as above. Bai further teaches wherein the hydrogen absorption layer (H2) is between the semiconductor channel (102/b) and one of the first and second source/drain electrodes and further extends along sidewalls of the one of the first and second source/drain electrodes (see Bai, Figs.3 and 5 as shown above).
Regarding Claim 8: Bai discloses an integrated circuit (IC) comprising a semiconductor device (see Bai, Figs.3 and 5 as shown above and ¶ [0001]), wherein the semiconductor device comprises:
a semiconductor channel (102/b), a gate electrode (g2/301), and a gate dielectric layer (401) that are stacked with the gate dielectric layer (401) separating the gate electrode (g2/301) from the semiconductor channel (102/b) (see Bai, Figs.3 and 5 as shown above);
a first source/drain electrode and a second source/drain electrode respectively on different portions of the semiconductor channel (102/b) (see Bai, Figs.3 and 5 as shown above); and
a hydrogen absorption layer (H2) adjacent to the gate electrode (g2/301) and the gate dielectric layer (401) (see Bai, Figs.3 and 5 as shown above).
Regarding Claim 11: Bai discloses an integrated circuit (IC) comprising a semiconductor device as set forth in claim 8 as above. Bai further teaches wherein the semiconductor channel (102) comprises a metal-oxide semiconductor material, and wherein the hydrogen absorption layer (H2) comprises an n-type metal oxide comprising indium (see Bai, Figs.3 and 5 as shown above, ¶ [0064]- ¶ [0066], and ¶ [0070]).
Regarding Claim 13: Bai discloses an integrated circuit (IC) comprising a semiconductor device as set forth in claim 8 as above. Bai further teaches wherein the semiconductor channel (102/b) overlies a semiconductor substrate (101), and wherein the semiconductor channel (102/b), the gate electrode (g2/301), and the gate dielectric layer (401) are vertically stacked with the gate electrode (g2/301) vertically between the gate dielectric layer (401) and the semiconductor substrate (101) (see Bai, Figs.3 and 5 as shown above).
Regarding Claim 14: Bai discloses an integrated circuit (IC) comprising a semiconductor device as set forth in claim 8 as above. Bai further teaches wherein the semiconductor channel (102/b) overlies a semiconductor substrate (101), and wherein the semiconductor channel (102/b), the gate electrode (g2/301), and the gate dielectric layer (401) are vertically stacked with semiconductor channel (102/b) vertically between the gate electrode (g2/301) and the semiconductor substrate (101) (see Bai, Figs.3 and 5 as shown above).
Regarding Claim 15: Bai discloses a method for forming a semiconductor device (see Bai, Figs.3 and 5 as shown above and ¶ [0001]), comprising:
forming a gate electrode (g2/301) and a hydrogen absorption layer (H2) bordering each other (see Bai, Figs.3 and 5 as shown above);
depositing a gate dielectric layer (401) overlying the gate electrode (g2/301) and the hydrogen absorption layer (H2) (see Bai, Figs.3 and 5 as shown above);
depositing a semiconductor layer (102) overlying the gate dielectric layer (401) (see Bai, Figs.3 and 5 as shown above);
patterning the semiconductor layer (102) to form a semiconductor channel (102/b) overlying the gate electrode (g2/301) and the hydrogen absorption layer (H2) (see Bai, Figs.3 and 5 as shown above); and
forming a first source/drain electrode and a second source/drain electrode atop the semiconductor channel (102/b), laterally spaced from each other (see Bai, Figs.3 and 5 as shown above).
Regarding Claim 20: Bai discloses a method for forming a semiconductor device as set forth in claim 15 as above. Bai further teaches wherein the forming of the gate electrode (g2/301) and the hydrogen absorption layer (H2) comprises:
depositing a film comprising a plurality of conductive layers (103/301) (see Bai, Figs.3 and 5 as shown above),
the hydrogen absorption layer (H2), and an additional hydrogen absorption layer (H1), wherein the conductive layers (103/301) are deposited alternatingly stacked with the hydrogen absorption layer (H2) and the additional hydrogen absorption layer (H1) (see Bai, Figs.3 and 5 as shown above); and
patterning the film into the gate electrode (see Bai, Figs.3 and 5 as shown above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Murray et al. (U.S. 2022/0246767 A1, hereinafter refer to Murray) in view of Bai (CN 115662999 A, hereinafter refer to Bai).
CN 115662999 A, (hereinafter refer to Bai) is relied upon solely for the English language translation of CN 115662999 A.
Regarding Claim 4: Bai discloses a semiconductor device as set forth in claim 1 as above. Bai further teaches wherein the hydrogen absorption layer (H1) is between the gate electrode (g1/103) and the gate dielectric layer and shares a width with the gate electrode (g1/103) (see Bai, Figs.3 and 5 as shown above).
Regarding Claim 6: Bai discloses a semiconductor device as set forth in claim 1 as above. Bai further teaches wherein an additional hydrogen absorption layer (H1) (see Bai, Fig.4); and
a plurality of conductive layers (103/301) alternatingly stacked with the hydrogen absorption layer (H2) and the additional hydrogen absorption layer (H1), wherein the plurality of conductive layers (103/301) form the gate electrode (g1/g2) (see Bai, Fig.4).
Claim(s) 5 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Bai (CN 115662999 A, hereinafter refer to Bai) as applied to claims 1 and 8 above, and further in view of Kawakita (JP 200269505 A, hereinafter refer to Kawakita).
CN 115662999 A, (hereinafter refer to Bai) is relied upon solely for the English language translation of CN 115662999 A.
JP 200269505 A, (hereinafter refer to Kawakita) is relied upon solely for the English language translation of JP 200269505 A.
Regarding Claim 5: Bai discloses a semiconductor device as applied to claim 1 above. Bai further teaches wherein the hydrogen absorption layer (H1) is between the gate electrode (g1/103) and the gate dielectric layer (see Bai, Fig.1).
Bai is silent upon explicitly disclosing wherein the hydrogen absorption layer further extends along sidewalls of the gate electrode.
For support see Kawakita, which teaches wherein the hydrogen absorption layer (14) further extends along sidewalls of the gate electrode (13) (see Kawakita, Fig.7 as shown below and abstract).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Bai and Kawakita to enable the hydrogen absorption layer of Bai to extend along sidewalls of the gate electrode as taught by Kawakita in order to enhance conductivity in a semiconductor layer.
Regarding Claim 9: Bai discloses an integrated circuit (IC) comprising a semiconductor device as applied to claim 8 above. Bai is silent upon explicitly disclosing wherein the gate electrode comprises a conductive body and a barrier layer, which lines sidewalls of the conductive body and a surface of the conductive body facing away from the gate dielectric layer, and wherein the hydrogen absorption layer separates the conductive body from the barrier layer.
For support see Kawakita, which teaches wherein the gate electrode (23/13) comprises a conductive body (13) and a barrier layer (23), which lines sidewalls of the conductive body (13) and a surface of the conductive body (13) facing away from the gate dielectric layer (12), and wherein the hydrogen absorption layer (14) separates the conductive body from the barrier layer (23) (see Kawakita, Fig.7 as shown above and abstract).
Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Bai and Kawakita to enable the gate electrode of Bai to comprise a conductive body and a barrier layer, which lines sidewalls of the conductive body and a surface of the conductive body facing away from the gate dielectric layer, and wherein the hydrogen absorption layer separates the conductive body from the barrier layer as taught by Kawakita in order to enhance conductivity in a semiconductor layer.
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Bai (CN 115662999 A, hereinafter refer to Bai) as applied to claim 8 above, and further in view of Murray et al. (U.S. 2022/0246767 A1, hereinafter refer to Murray).
CN 115662999 A, (hereinafter refer to Bai) is relied upon solely for the English language translation of CN 115662999 A.
Regarding Claim 10: Bai discloses an integrated circuit (IC) comprising a semiconductor device as applied to claim 8 above. Bai is silent upon explicitly disclosing wherein an interconnect structure overlying a semiconductor substrate and comprising a plurality of wire levels and a plurality of via levels alternatingly stacked away from the semiconductor substrate, wherein at least one of the plurality of wire levels separates the semiconductor substrate from the semiconductor device.
For support see Murray, which teaches wherein an interconnect structure overlying a semiconductor substrate (8) and comprising a plurality of wire levels and a plurality of via levels alternatingly stacked away from the semiconductor substrate (8), wherein at least one of the plurality of wire levels separates the semiconductor substrate (8) from the semiconductor device (40) (see Murray, Figs.14 and 28 as shown below and ¶ [0183]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Bai and Murray to enable an interconnect structure overlying a semiconductor substrate and comprising a plurality of wire levels and a plurality of via levels alternatingly stacked away from the semiconductor substrate, wherein at least one of the plurality of wire levels separates the semiconductor substrate from the semiconductor device as taught by Murray in order to maintain the device characteristics of the thin film transistor constant throughout the operational lifetime of the thin film transistor.
Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable over Bai (CN 115662999 A, hereinafter refer to Bai) as applied to claim 8 above, and further in view of Kim et al. (U.S. 2020/0075887 A1, hereinafter refer to Kim).
CN 115662999 A, (hereinafter refer to Bai) is relied upon solely for the English language translation of CN 115662999 A.
Regarding Claim 12: Bai discloses an integrated circuit (IC) comprising a semiconductor device as applied to claim 8 above. Bai further teaches wherein the semiconductor channel comprises a metal-oxide semiconductor material (see Bai, Figs.3 and 5 as shown above, ¶ [0064]- ¶ [0066], and ¶ [0070]).
Bai is silent upon explicitly disclosing wherein the hydrogen absorption layer comprises a noble metal.
For support see Kim, which teaches wherein the hydrogen absorption layer (180) comprises a noble metal (see Kim, ¶ [0074]).
Bai discloses the claimed invention except for the material of hydrogen absorption layer. Thus, it would have been obvious to one having ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Bai and Kim to enable the known noble metal material as taught by Kim in order to form a hydrogen absorption layer, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Claim(s) 16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Bai (CN 115662999 A, hereinafter refer to Bai) as applied to claim 15 above, and further in view of Yamazaki et al. (U.S. 2023/0027402 A1, hereinafter refer to Yamazaki) and Lee (U.S. 2021/0202910 A1, hereinafter refer to Lee).
CN 115662999 A, (hereinafter refer to Bai) is relied upon solely for the English language translation of CN 115662999 A.
Regarding Claim 16: Bai discloses a method for forming a semiconductor device as applied to claim 15 above. Bai is silent upon explicitly disclosing wherein patterning a dielectric layer to form a gate opening, wherein the gate electrode is formed filling the gate opening, and wherein the hydrogen absorption layer is formed overlying the gate electrode and the dielectric layer.
For support see Yamazaki, which teaches patterning a dielectric layer (216) to form a gate opening, wherein the gate electrode (205b) is formed filling the gate opening, and wherein the hydrogen absorption layer (205a or 205c) is formed overlying the gate electrode (205b) and the dielectric layer (216) (note: the material of layer 205a and 205c such as titanium (Ti) and tantalum (Ta) were known as hydrogen absorption layer material, for support see Lee, ¶ [0034], ¶ [0057]) (see Yamazaki, Figs.6-10 as shown below and ¶ [0144]- ¶ [0149]).
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Thus, it would have been within the scope of one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Bai, Yamazaki, and Lee to enable the gate electrode and hydrogen absorption layer of Bai to be performed according to the teachings of Yamazaki because one of ordinary skill in the art before effective filing date of the claimed invention would have been motivated to look to alternative suitable methods of performing the disclosed gate electrode and hydrogen absorption layer of Bai and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Regarding Claim 18: Bai discloses a method for forming a semiconductor device as applied to claim 15 above. Bai is silent upon explicitly disclosing wherein the forming of the gate electrode and the hydrogen absorption layer comprises:
patterning a dielectric layer to form a gate opening;
depositing the hydrogen absorption layer overlying and directly contacting the dielectric layer and further lining the gate opening;
depositing a conductive layer filling the gate opening over the hydrogen absorption layer; and
performing a planarization into the hydrogen absorption layer and the conductive layer to expose a top surface of the dielectric layer.
For support see Yamazaki, which teaches wherein the forming of the gate electrode (205b and/or 205c) and the hydrogen absorption layer (205a) (note: the material of layer 205a and 205c such as titanium (Ti) and tantalum (Ta) were known as hydrogen absorption layer material, for support see Lee, ¶ [0034], ¶ [0057]) (see Yamazaki, Figs.6-10 as shown above and ¶ [0144]- ¶ [0149]) comprises:
patterning a dielectric layer (216) to form a gate opening (see Yamazaki, Figs.6-10 as shown above and ¶ [0144]- ¶ [0149]);
depositing the hydrogen absorption layer (205a) overlying and directly contacting the dielectric layer (216) and further lining the gate opening (see Yamazaki, Figs.6-10 as shown above and ¶ [0144]- ¶ [0149]);
depositing a conductive layer (205b and/or 205c) filling the gate opening over the hydrogen absorption layer (205a) (see Yamazaki, Figs.6-10 as shown above and ¶ [0144]- ¶ [0149]); and
performing a planarization into the hydrogen absorption layer (205a) and the conductive layer (205b and/or 205c) to expose a top surface of the dielectric layer (216) (see Yamazaki, Figs.6-10 as shown above and ¶ [0144]- ¶ [0149]).
Thus, it would have been within the scope of one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Bai, Yamazaki, and Lee to enable the gate electrode and hydrogen absorption layer of Bai to be performed according to the teachings of Yamazaki because one of ordinary skill in the art before effective filing date of the claimed invention would have been motivated to look to alternative suitable methods of performing the disclosed gate electrode and hydrogen absorption layer of Bai and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Claim(s) 17 is rejected under 35 U.S.C. 103 as being unpatentable over Bai (CN 115662999 A, hereinafter refer to Bai) as applied to claim 15 above, and further in view of Yamazaki et al. (U.S. 2023/0027402 A1, hereinafter refer to Yamazaki) and Kim et al. (U.S. 2020/0075887 A1, hereinafter refer to Kim).
CN 115662999 A, (hereinafter refer to Bai) is relied upon solely for the English language translation of CN 115662999 A.
Regarding Claim 17: Bai discloses a method for forming a semiconductor device as applied to claim 15 above. Bai is silent upon explicitly disclosing wherein the forming of the gate electrode and the hydrogen absorption layer comprises: patterning a dielectric layer to form a gate opening;
depositing a barrier layer overlying the dielectric layer and lining the gate opening; depositing the hydrogen absorption layer overlying the barrier layer and lining the gate opening;
depositing a conductive layer filling the gate opening over the hydrogen absorption layer; and
performing a planarization into the barrier layer, the hydrogen absorption layer, and the conductive layer to expose a top surface of the dielectric layer.
For support see Yamazaki, which teaches wherein the forming of the gate electrode (205c) and the hydrogen absorption layer (205b) (note: the material of layer 205b such as aluminum (Al) and copper (Cu) were known as hydrogen absorption layer material, for support see Kim, ¶ [0074]) (see Yamazaki, Figs.6-10 as shown above and ¶ [0144]- ¶ [0149]) comprises:
patterning a dielectric layer (216) to form a gate opening (see Yamazaki, Figs.6-10 as shown above and ¶ [0144]- ¶ [0149]);
depositing a barrier layer (205a) overlying the dielectric layer (216) and lining the gate opening (see Yamazaki, Figs.6-10 as shown above and ¶ [0144]- ¶ [0149]);
depositing the hydrogen absorption layer (205b) overlying the barrier layer (205a) and lining the gate opening (see Yamazaki, Figs.6-10 as shown above and ¶ [0144]- ¶ [0149]);
depositing a conductive layer (205c) filling the gate opening over the hydrogen absorption layer (205b) (see Yamazaki, Figs.6-10 as shown above and ¶ [0144]- ¶ [0149]); and
performing a planarization into the barrier layer (205a), the hydrogen absorption layer (205b), and the conductive layer (205c) to expose a top surface of the dielectric layer (216) (see Yamazaki, Figs.6-10 as shown above and ¶ [0144]- ¶ [0149]).
Thus, it would have been within the scope of one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Bai, Yamazaki, and Kim to enable the gate electrode and hydrogen absorption layer of Bai to be performed according to the teachings of Yamazaki because one of ordinary skill in the art before effective filing date of the claimed invention would have been motivated to look to alternative suitable methods of performing the disclosed gate electrode and hydrogen absorption layer of Bai and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Claim(s) 19 is rejected under 35 U.S.C. 103 as being unpatentable over Bai (CN 115662999 A, hereinafter refer to Bai) as applied to claim 15 above, and further in view of Kawakita (JP 200269505 A, hereinafter refer to Kawakita).
CN 115662999 A, (hereinafter refer to Bai) is relied upon solely for the English language translation of CN 115662999 A.
JP 200269505 A, (hereinafter refer to Kawakita) is relied upon solely for the English language translation of JP 200269505 A.
Regarding Claim 19: Bai discloses a method for forming a semiconductor device as applied to claim 15 above. Bai is silent upon explicitly disclosing wherein the forming of the gate electrode and the hydrogen absorption layer comprises:
depositing a conductive layer over a dielectric layer;
patterning the conductive layer into the gate electrode; and
depositing the hydrogen absorption layer over the gate electrode and extending along sidewalls of the gate electrode.
For support see Kawakita, which teaches wherein the forming of the gate electrode (13) and the hydrogen absorption layer (14) (see Kawakita, Fig.7 as shown above and abstract) comprises:
depositing a conductive layer (13) over a dielectric layer (12) (see Kawakita, Fig.7 as shown above and abstract);
patterning the conductive layer (13) into the gate electrode (see Kawakita, Fig.7 as shown above and abstract); and
depositing the hydrogen absorption layer (14) over the gate electrode (13) and extending along sidewalls of the gate electrode (13) (see Kawakita, Fig.7 as shown above and abstract).
Thus, it would have been within the scope of one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Bai and Kawakita to enable the gate electrode and hydrogen absorption layer of Bai to be performed according to the teachings of Kawakita because one of ordinary skill in the art before effective filing date of the claimed invention would have been motivated to look to alternative suitable methods of performing the disclosed gate electrode and hydrogen absorption layer of Bai and art recognized suitability for an intended purpose has been recognized to be motivation to combine. MPEP § 2144.07.
Conclusion
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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