Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 8 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Allowable Subject Matter
Claims 26-27 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “wherein the hydrogen absorption layer comprises an n-type metal oxide comprising indium, the n-type metal oxide having a carrier concentration from about 1E19 atoms/cm3 to about 1E21 atoms/cm3”, as recited in claim 26.
The primary reason for the allowance of the claims is the inclusion of the limitation, along with the other claimed features, “a hydrogen blocking layer on the first side of the semiconductor channel and sharing the common width with the hydrogen absorption layer and the gate dielectric layer, wherein the hydrogen absorption layer is more absorptive of hydrogen than the hydrogen blocking layer, and wherein the first and second source/drain electrodes extend through the hydrogen blocking layer respectively to the different portions of the semiconductor channel”, as recited in claim 27.
Claims 1, 4, 7, 15, 21-24, and 28-31 are allowed.
The following is an examiner’s statement of reasons for allowance:
In re Claim 1, Watakabe et al. (U.S. 2025/0015189 A1, hereinafter refer to Watakabe) teaches a semiconductor device (see Watakabe, Fig.1 and ¶ [0002]), comprising:
a semiconductor channel (140) (see Watakabe, Fig.1);
a first source/drain electrode (201/200) and a second source/drain electrode (203/200) that are at a first side of the semiconductor channel (140) and that are electrically coupled respectively to different portions of the semiconductor channel (140) (see Watakabe, Fig.1);
a gate electrode (105) comprising a first conductive layer, wherein the first and conductive layers are both at a second side of the semiconductor channel (140), opposite the first side of the semiconductor channel (140) (see Watakabe, Fig.1);
a gate dielectric layer (110/120) separating the first and second conductive layers (105) from the semiconductor channel (140) (see Watakabe, Fig.1).
Watakabe is silent upon explicitly disclosing wherein a gate electrode comprising a first conductive layer and a second conductive layer overlying the first conductive layer, wherein the first and second conductive layers;
a first hydrogen absorption layer between the first and second conductive layers at the second side of the semiconductor channel.
For support see Kawakita (JP 200269505 A, hereinafter refer to Kawakita) which teaches wherein a gate electrode (13/14/23) comprising a first conductive layer (13) and a second conductive layer (23) overlying the first conductive layer (13), wherein the first and second conductive layers (23) (see Kawakita, Fig.7 and abstract);
a first hydrogen absorption layer (14) between the first and second conductive layers (13/23) at the second side of the semiconductor channel (11) (see Kawakita, Fig.7 and abstract).
The prior arts of record do not anticipate and do not render obvious such limitations of Claim 1 as: "a second hydrogen absorption layer between the second conductive layer and the gate dielectric layer at the second side of the semiconductor channel.”
Claims 4, 7, and 21-24 are allowed for the same reasons as claim 1, from which they depend.
In re Claim 15, Yamazaki et al. (U.S. 2023/0027402 A1, hereinafter refer to Yamazaki) teaches method for forming a semiconductor device (see Yamazaki, Figs.2B and 6B-10 and ¶ [0001]), comprising:
patterning a dielectric layer (216) to form a gate opening (see Yamazaki, Fig.6);
depositing a multi-layer film overlying the dielectric layer (216) and lining the gate opening, wherein the multi-layer film comprises a barrier layer (205a), a hydrogen absorption layer (205c) over the barrier layer (205a), and a conductive layer (205b) (see Yamazaki, Figs.2B and 6B-10 and ¶ [0147]);
performing a planarization into the multi-layer film to form a gate electrode (205) that comprises a portion of the barrier layer (205a) and a portion of the conductive layer (205b) (see Yamazaki, Figs.2B and 6B-10);
depositing a gate dielectric layer (222) overlying the gate electrode (205) and the portion of the hydrogen absorption layer (205c) after the planarization (see Yamazaki, Figs.2B and 6B-10);
depositing a semiconductor layer (230) overlying the gate dielectric layer (222) (see Yamazaki, Figs.2B and 6B-10).
Yamazaki is silent upon explicitly disclosing wherein patterning the semiconductor layer to form a semiconductor channel overlying the gate electrode and the portion of the hydrogen absorption layer; and
forming a first source/drain electrode and a second source/drain electrode atop the semiconductor channel, laterally spaced from each other.
For support see Tamaru et al. (U.S. 2024/0088302 A1, hereinafter refer to Tamaru), which teaches wherein patterning the semiconductor layer (140) to form a semiconductor channel overlying the gate electrode (105) and the portion of the hydrogen absorption layer (130) (see Tamaru, Figs.1 and 4-10); and
forming a first source/drain electrode (201/200) and a second source/drain electrode (203/200) atop the semiconductor channel (140), laterally spaced from each other (see Tamaru, Figs.1 and 4-10).
The prior arts of record do not anticipate and do not render obvious such limitations of Claim 15 as: "wherein the multi-layer film comprises a barrier layer, a hydrogen absorption layer over the barrier layer, and a conductive layer over the hydrogen absorption layer;
a portion of the conductive layer separated by a portion of the hydrogen absorption layer in the gate opening, wherein a top surface of the barrier layer, a top surface of the hydrogen absorption layer, a top surface of the conductive layer, and a top surface of the dielectric layer are concurrently exposed at completion of the planarization.”
Claims 28-31 are allowed for the same reasons as claim 15, from which they depend.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. 2021/0066505 A1, hereinafter refer to Lee) in view of Tamaru et al. (U.S. 2024/0088302 A1, hereinafter refer to Tamaru).
Regarding Claim 8: Lee discloses an integrated circuit (IC) comprising a semiconductor device (see Lee, Fig.1B as shown below and ¶ [0002]),
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wherein the semiconductor device (see Lee, Fig.1B as shown above) comprises:
a semiconductor channel (106), a gate electrode (132), and a gate dielectric layer (104) that are stacked with the gate dielectric layer (104) separating the gate electrode (132) from the semiconductor channel (106) (see Lee, Fig.1B as shown above);
a first source/drain electrode (124) and a second source/drain electrode (134) extending respectively to different portions of the semiconductor channel (106) and on a first side of the semiconductor channel (106) (see Lee, Fig.1B as shown above); and
a hydrogen absorption layer (134) that is adjacent to the gate electrode (132) and the gate dielectric layer (104) and that separates the gate electrode (132) from the gate dielectric layer (104) and from the semiconductor channel (106) on a second side of the semiconductor channel (106), opposite the first side of the semiconductor channel (106) (see Lee, Fig.1B as shown above).
Lee is silent upon explicitly disclosing wherein the hydrogen absorption layer and the gate dielectric layer share a common width greater than a width of the gate electrode.
For support see Tamaru, which teaches wherein the hydrogen absorption layer (130) and the gate dielectric layer (110/120) share a common width greater than a width of the gate electrode (105) (see Tamaru, Fig.1 as shown below and ¶ [0033]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Lee and Tamaru to enable the hydrogen absorption layer and the gate dielectric layer of Lee to share a common width greater than a width of the gate electrode as taught by Tamatu in order to obtain a highly reliable semiconductor device having high mobility.
Regarding Claim 13: Lee discloses an integrated circuit (IC) comprising a semiconductor device as set forth in claim 8 as above. The combination of Lee and Tamaru further teaches wherein the semiconductor channel (140) overlies a semiconductor substrate (100), and wherein the semiconductor channel (140), the gate electrode (105), and the gate dielectric layer (110/120) are vertically stacked with the gate electrode (105) vertically between the gate dielectric layer (110/120) and the semiconductor substrate (100) (see Tamaru, Fig.1 as shown above, ¶ [0033], and ¶ [0051]).
Claim(s) 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. 2021/0066505 A1, hereinafter refer to Lee) and Tamaru et al. (U.S. 2024/0088302 A1, hereinafter refer to Tamaru) as applied to claim 8 above, and further in view of Murray et al. (U.S. 2022/0246767 A1, hereinafter refer to Murray).
Regarding Claim 10: Lee discloses an integrated circuit (IC) comprising a semiconductor device as applied to claim 8 above. The combination of Lee and Tamaru is silent upon explicitly disclosing wherein an interconnect structure overlying a semiconductor substrate and comprising a plurality of wire levels and a plurality of via levels alternatingly stacked away from the semiconductor substrate, wherein at least one of the plurality of wire levels separates the semiconductor substrate from the semiconductor device.
For support see Murray, which teaches wherein an interconnect structure overlying a semiconductor substrate (8) and comprising a plurality of wire levels and a plurality of via levels alternatingly stacked away from the semiconductor substrate (8), wherein at least one of the plurality of wire levels separates the semiconductor substrate (8) from the semiconductor device (40) (see Murray, Figs.14 and 28 as shown below and ¶ [0183]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Lee, Tamaru, and Murray to enable an interconnect structure overlying a semiconductor substrate and comprising a plurality of wire levels and a plurality of via levels alternatingly stacked away from the semiconductor substrate, wherein at least one of the plurality of wire levels separates the semiconductor substrate from the semiconductor device as taught by Murray in order to maintain the device characteristics of the thin film transistor constant throughout the operational lifetime of the thin film transistor.
Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. 2021/0066505 A1, hereinafter refer to Lee) and Tamaru et al. (U.S. 2024/0088302 A1, hereinafter refer to Tamaru) as applied to claim 8 above, and further in view of Bai (CN 115662999 A, hereinafter refer to Bai).
Regarding Claim 11: Lee discloses an integrated circuit (IC) comprising a semiconductor device as applied to claim 8 above. The combination of Lee and Tamaru further teaches wherein the semiconductor channel (106) comprises a metal-oxide semiconductor material (see Lee, Fig.1B as shown above and ¶ [0047]).
The combination of Lee and Tamaru is silent upon explicitly disclosing wherein the hydrogen absorption layer comprises an n-type metal oxide comprising indium.
For support see Bai, which teaches wherein the hydrogen absorption layer (H2) comprises an n-type metal oxide comprising indium (see Bai, Figs.3 and 5, abstract. ¶ [0064],- ¶ [0066], and ¶ [0070]).
The combination of Lee and Tamaru teaches the claimed invention except for the material of hydrogen absorption layer. Thus, it would have been obvious to one having ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Lee, Tamaru, and Bai to enable hydrogen absorption layer to comprise an n-type metal oxide comprising indium as taught by Bai in order to improve the reliability of the oxide thin film transistor, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Claim(s) 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. 2021/0066505 A1, hereinafter refer to Lee) and Tamaru et al. (U.S. 2024/0088302 A1, hereinafter refer to Tamaru) as applied to claim 8 above, and further in view of Kim et al. (U.S. 2020/0075887 A1, hereinafter refer to Kim).
Regarding Claim 12: Lee discloses an integrated circuit (IC) comprising a semiconductor device as applied to claim 8 above. The combination of Lee and Tamaru further teaches wherein the semiconductor channel comprises a metal-oxide semiconductor material (see Lee, Fig.1B as shown above and ¶ [0047]).
The combination of Lee and Tamaru is silent upon explicitly disclosing wherein the hydrogen absorption layer comprises a noble metal.
For support see Kim, which teaches wherein the hydrogen absorption layer (180) comprises a noble metal (see Kim, ¶ [0074]).
The combination of Lee and Tamaru discloses the claimed invention except for the material of hydrogen absorption layer. Thus, it would have been obvious to one having ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Lee, Tamaru, and Kim to enable the known noble metal material as taught by Kim in order to form a hydrogen absorption layer, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Claim(s) 25 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. 2021/0066505 A1, hereinafter refer to Lee) and Tamaru et al. (U.S. 2024/0088302 A1, hereinafter refer to Tamaru) as applied to claim 8 above, and further in view of Sharma et al. (U.S. 2021/0408291 A1, hereinafter refer to Sharma).
Regarding Claim 25: Lee discloses an integrated circuit (IC) comprising a semiconductor device as applied to claim 8 above. The combination of Lee and Tamaru is silent upon explicitly disclosing wherein the width of the gate electrode is greater than a width of the semiconductor channel.
For support see Sharma, which teaches wherein the width of the gate electrode (102) is greater than a width of the semiconductor channel (106) (see Sharma, Fig.1 as shown below and ¶ [0037]).
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Thus, it would have been obvious to one of ordinary skill in the art before effective filing date of the claimed invention to combine the teachings of Lee, Tamaru, and Sharma to enable the width of the gate electrode to be greater than a width of the semiconductor channel as taught by Sharma in order to reduce in off state leakage.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BITEW A DINKE whose telephone number is (571)272-0534. The examiner can normally be reached M-F 7 a.m. - 5 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571)272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BITEW A DINKE/Primary Examiner, Art Unit 2812
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