DETAILED ACTION
This action is responsive to the application No. 18/618,312, filed on March 27, 2024.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, corresponding to claims 1-17 and 21-23, in the reply filed on is acknowledged.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the after the etch back operation, the first portion of the semiconductor layer remains only on the plurality of portions of the insulator layer must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 22 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 22 recites “…after the etch back operation, the first portion of the semiconductor layer remains only on the plurality of portions of the insulator layer…”, having no written description support. Fig. 3G shows the state of the device after the etch back and the semiconductor layer 308 is clearly on both of the insulator and on the substrate 202. While ¶56 of the specification states (emphasis added): “As shown in Fig. 3G, an etch back operation may be performed on the first portion 308 of the semiconductor layer 232 such that the first portion 308 of the semiconductor layer 232 remains only on the first portions 306 of the insulator layer 230.” This statement in the specification is not accurate: 308 is on 202 and 308 is also on 306.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 22 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 22 recites “…after the etch back operation, the first portion of the semiconductor layer remains only on the plurality of portions of the insulator layer…”. This limitation is confusing in view of the specification, in Fig. 3G, after the etch back and the semiconductor layer 308 is clearly on both of the insulator and on the substrate 202. It is unclear what Applicant intends by “only on” since 308 is not “only on” 306.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 21 and 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al. (US 2015/0060960).
(Re Claim 21) Xie teaches a method, comprising: forming a plurality of recesses in a semiconductor on insulator (SOI) region of a bulk semiconductor substrate; forming a plurality of portions of an insulator layer in lower portions of the plurality of recesses such that semiconductor material of sidewalls of unfilled portions of the plurality of recesses remains exposed; and epitaxially growing a first portion of a semiconductor layer on the semiconductor material of the sidewalls of the unfilled portions of the plurality of recesses and over the plurality of portions of the insulator layer; and (Re Claim 23) wherein epitaxially growing the first portion of the semiconductor layer comprises: performing an epitaxial deposition operation to deposit material of the first portion of the semiconductor layer; and performing an anneal operation to reduce formation of voids in the first portion of the semiconductor layer (see Figs. 3B-3C, substrate 102 is SOI substrate, recesses between fins 106 have dielectric isolation 107, epi is grown on the exposed sidewalls of the fins in Fig. 3C and subsequently annealed, ¶¶34-41).
Allowable Subject Matter
Claims 1-17 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 1 is allowable for at least the reasons of “…forming, in the bulk semiconductor substrate, a second plurality of portions of the insulator layer after forming the first portion of the merged semiconductor layer; and forming a second portion of the merged semiconductor layer on the insulator layer after forming the second plurality of portions of the insulator layer”, as set forth in the claimed combination. These features of the method of claim 1 are not anticipated or rendered obvious by the prior art known to the Examiner. Claims 2-8 depend from claim 1 and are allowable for at least these reasons.
Claim 9 is allowable for at least the reasons of “…forming, in the SOI region, a second plurality of dielectric regions in between the first plurality of dielectric regions, wherein the first plurality of dielectric regions and the second plurality of dielectric regions merge to form an insulator layer in the SOI region; epitaxially growing a second portion of the semiconductor layer on the insulator layer”, as set forth in the claimed combination. These features of the method of claim 9 are not anticipated or rendered obvious by the prior art known to the Examiner. Claims 10-17 depend from claim 9 and are allowable for at least these reasons.
The closest prior art is from Xie et al. (US 2015/0060960), Moder et al. (US 2017/0154808), Schaeffer et al. (US 2018/0166324), Adusumilli et al. (US 2019/0312142), Tsai et al. (US 2019/0096740), Adusumilli et al. (US 2020/0176304), and Adusumilli et al. (US 2022/0108951), however none teach the …forming, in the bulk semiconductor substrate, a second plurality of portions of the insulator layer after forming the first portion of the merged semiconductor layer; and forming a second portion of the merged semiconductor layer on the insulator layer after forming the second plurality of portions of the insulator layer…of claim 1, or the forming, in the SOI region, a second plurality of dielectric regions in between the first plurality of dielectric regions, wherein the first plurality of dielectric regions and the second plurality of dielectric regions merge to form an insulator layer in the SOI region; epitaxially growing a second portion of the semiconductor layer on the insulator layer of claim 9.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional cited art teaches methods similar to Xie et al., similarly applicable in rejections, related SOI processes, and processes for forming recesses followed by forming dielectrics in recesses, and then forming semiconductor materials on the dielectrics.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK T. K. PETERSON whose telephone number is (571)272-3997. The examiner can normally be reached M-F, 9-5 pm (CST).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIK T. K. PETERSON/ Primary Examiner, Art Unit 2898
Prosecution Insights