DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 claims that the sum of the thickness is between 10-20 micrometers. However, that contradicts with the claim it’s dependent on, claim 1, in which it has already been claimed that the combined thickness of the first and second oxide layer is between 11-20 micrometers. This claim fails to narrow the scope of the claim it’s dependent on and instead broadens it. Therefore, it conflicts with the dependent claim, and it is left unclear how this claim is further limiting the scope of the application.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 7 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends.
Claim 7 states that the sum of the thickness of the two oxide layers is between 10-20 micrometers. However, claim 1, which claim 7 depends upon, states that this thickness is between 11-20 micrometers. As the range is narrower in claim 1, claim 7 doesn’t add anything further to the limitations stated in claim 1. Therefore, claim 7 fails to narrow the scope of the application.
Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-7, 11-12, 15, 17-18, & 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Erk et al. (US 2019/0019721) in view of Moore et al. (US 6,093,956) and Yamazaki (2011/0127522 A1).
Regarding Claim 1: Erk et al. teaches a method comprising:
Forming a thermal oxide layer on a first surface and a second surface on a semiconductor wafer (Paragraph 44 describes oxidizing both the front and backside of the wafer, 100, to create a thermal oxide layer on both sides, 200 in Fig 3)
Forming a tensile nitride layer (300, Paragraph 110 describes a nitride layer which would broadly be a tensile nitride layer as it has layers on both the top and bottom of it which is able to provide a tensile force, see also paragraph 50) on the first surface of the semiconductor wafer on top of the thermal oxide layer (Fig 3 shows the tensile nitride layer on top of the thermal oxide layer, 200)
Forming a first oxide layer (400, Paragraph 110) on top of the tensile nitride layer (Figure 3 shows the first oxide layer, 400, on top of the nitride layer, 300, and the thermal oxide layer, 200)
Wherein a thickness of the first oxide layer is below 10 micrometers (Paragraph 41 states that an individual dielectric layer, including the oxide layer is within the range of 10-10000 nm, the maximum of this range being equal to 10 micrometers. Therefore, the oxide layer is capable of being within 1-9 micrometers of thickness).
Erk et al. does not explicitly teach forming a compressive nitride layer on the second surface of the semiconductor wafer on top of the thermal oxide layer; and forming a second oxide layer on top of the first oxide layer, where there is a sum of thicknesses of the first and second oxide layer between 11-20 micrometers.
Moore et al. teaches a nitride layer (24a, which can be compressive as described in column 2, lines 58-60) that is formed on a second surface of the wafer (16, Column 3 lines 55-61 describes the silicon nitride layer on the second opposing surface)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Erk et al. to form a compressive nitride layer on the second (bottom) surface of the semiconductor wave on top of the thermal oxide layer as taught by Moore et al. in order to equalize a stress across the substrate to prevent deformation (Moore et al. – col 2 lines 11-18) allowing the semiconductor to enhance durability.
However, Erk et al., as modified, still does not disclose a second oxide layer on top of the first oxide layer, where the sum of the thickness of the first and second oxide layer is between 11-20 micrometers
Yamazaki teaches a second oxide layer on top of the first oxide layer (Paragraph 0197 describes a second oxide layer, 104a, that is formed above a first oxide layer, 102b).
Wherein a sum of a thickness of the first oxide layer and the second oxide layer is 11-20 micrometers (Paragraph 0197 of Yamazaki states that the thickness of the second oxide layer is greater than or equal to 1 micrometer. Combined with the range of the oxide layer in Erk et al., which has a maximum thickness of 10 micrometers, the combined thickness of these two oxide layers fits within the range of 11-20 micrometers).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Erk et al. to form an additional/second buffer layer that is an oxide layer as taught by Yamazaki in order to provide protection as well having an extra
layer that will help manage strain which would extend the life of the wafer.
It would have further been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Erk et al. to have the sum of the thicknesses for first and the second oxide layer be between 11-20 micrometers, as taught in Yamazaki, because having a combined thickness of 11-20 micrometers for the two oxide layers results in both of the oxide layers being thicker, which makes it easier to maintain uniformity during the manufacturing process, which reduces defects. Furthermore, as the first oxide layer is below 10 micrometers in length, having the combined thickness be within 11-20 micrometers would allow for the two oxide layers to be similar in size, which would result in better uniformity within the wafer.
Regarding claim 6, Erk et al., as modified teaches a thermal oxide layer that has a thickness of 10-100 nm (Paragraph 43 describes the that each layer can have a thickness between 10-10,000 nm, which the range of 10-100 nm fits within).
Regarding claim 7, Erk et al., as modified, teaches the sum of the thickness of the first oxide layer and the second oxide layer being between 10-20 micrometers (See explanation for the rejection of dependent claim 1. As it has been taught in a claim that claim 7 is dependent on that the combined thickness of the first and second oxide layer is between 11-20 micrometers, it is already within the range of thickness between 10-20 micrometers).
Regarding claim 11, Erk et al., as modified, teaches a thickness of the tensile nitride layer chosen
based on a desired thickness of the first oxide layer and the second oxide layer (Thickness of the nitride
layer is chosen by the inventor so it was chosen based on a desired thickness of the oxide layers),
wherein the tensile nitride layer imparts a tensile stress on the first surface of the semiconductor wafer to compensate for the desired thickness of the first oxide layer and the second
oxide layer (Erk et al. Paragraph 50).
Regarding claim 12, Erk et al. does not explicitly teach a method wherein the thickness of the
tensile nitride layer is chosen by calculating a tensile stress offset of the tensile nitride layer.
Moore et al. teaches the thickness of the tensile layer being chosen by calculating a tensile
stress offset of the tensile nitride layer (Column 5, lines 47-49).
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to modify Erk et al., as modified, to adjust the thickness of the tensile layer based
off of the stress of the layer, as taught by Moore et al., because this will make sure that the compressive
and tensile forces balance out and, therefore, make the wafer less likely to warp, (Moore et al. Column
5, lines 51-55).
Regarding claim 15, Erk et al., as modified, discloses wherein the tensile nitride layer (Erk et al.
paragraph 43 states the range is 10-10,000 nm) has a larger thickness than the compressive nitride layer
(Compressive nitride layer taught in from Moore et al. as seen in the rejection to claim 1 above has the
layer being 1000 angstroms - col 5 lines 55-56, in the instances where the tensile nitride layer is above
100 nm the tensile nitride layer will have a larger thickness).
Regarding claim 17, Erk et al., as modified, teaches that the tensile nitride layer and the
compressive nitride layer imparts a positive bow on the semiconductor wafer to offset a negative bow
from the first oxide layer and the second oxide layer (Erk et al. modified has all the same layers as the application on the same side of the wafer, therefore the layers with a positive and a negative bow
would offset in the same manner).
Regarding Claim 18, Erk et al. teaches a method comprising:
Forming a thermal oxide layer on a first surface and a second surface on a semiconductor wafer
(Paragraph 44 describes oxidizing both the front and backside of the wafer, 100 to create a thermal
oxide layer on both sides, 200 in Fig 3)
Forming a first nitride layer having one of a tensile stress and a compressive stress on the first
surface of the semiconductor (300, Paragraph 110 describes a nitride layer which has the capability of
bringing compressive or tensile stress to the wafer) on the first surface of the semiconductor wafer (300
on the top surface of the wafer 100).
Forming a first oxide layer (400, Paragraph 110) on top of the first nitride layer (Figure 3 shows
the first oxide layer, 400, on top of the nitride layer, 300).
Wherein a thickness of the first oxide layer is below 10 micrometers (Paragraph 41 states that an individual dielectric layer, including the oxide layer is within the range of 10-10000 nm, the maximum of this range being equal to 10 micrometers. Therefore, the oxide layer is capable of being within 1-9 micrometers of thickness).
Erk et al. does not explicitly teach forming a second nitride layer on the second surface of the
semiconductor wafer having the other of a tensile stress or compressive stress; and forming a second
oxide layer on top of the first oxide layer, where there is a sum of thicknesses of the first and second
oxide layer.
Moore et al. teaches a nitride layer (24a, which can be compressive or tensile as described in
column 2, lines 58-60) that is formed on a second surface of the wafer (16, Column 3 lines 55-63
describes the silicon nitride layer on the second opposing surface).
Yamazaki teaches a second oxide layer on top of the first oxide layer (Paragraph 0197 describes a second oxide layer, 104a, that is formed above a first oxide layer, 102b).
Wherein a sum of a thickness of the first oxide layer and the second oxide layer is 11-20 micrometers (Paragraph 0197 of Yamazaki states that the thickness of the second oxide layer is greater than or equal to 1 micrometer. Combined with the range of the oxide layer in Erk et al., which has a maximum thickness of 10 micrometers, the combined thickness of these two oxide layers fits within the range of 11-20 micrometers).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Erk et al. to form an additional/second buffer layer that is an oxide layer as taught by Yamazaki in order to provide protection as well having an extra
layer that will help manage strain which would extend the life of the wafer.
It would have further been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Erk et al. to have the sum of the thicknesses for first and the second oxide layer be between 11-20 micrometers, as taught in Yamazaki, because having a combined thickness of 11-20 micrometers for the two oxide layers results in both of the oxide layers being thicker, which makes it easier to maintain uniformity during the manufacturing process, which reduces defects. Furthermore, as the first oxide layer is below 10 micrometers in length, having the combined thickness be within 11-20 micrometers would allow for the two oxide layers to be similar in size, which would result in better uniformity within the wafer.
Regarding claim 21, Erk et al., as modified, teaches the compressive nitride layer is formed after the forming of the first oxide layer (As the compressive nitride layer is added to the modified Erk et al. through Moore et al. in the dependent claim 1, the modification of forming the first compressive nitride layer would be made after the formation of the first oxide layer in Erk et al.), and
the second oxide layer is formed after the forming of the compressive nitride layer (As the second oxide layer is added to the modified Erk et al. through Yamazaki in the dependent claim 1, the modification of forming the second nitride layer would be made after the modification of adding the compressive nitride layer through Moore et al.).
Regarding claim 22, Erk et al., as modified, teaches the first oxide layer and the second oxide layer are deposited or grown separately (As the second oxide layer is added to the modified Erk et al. in the dependent claim 1, the two oxide layers are deposited onto the wafer separately), and the first oxide layer is deposited by chemical vapor deposition, atomic layer deposition, or a combination thereof (Paragraph 0076 states that the oxide layer is deposited through chemical vapor deposition).
Erk et al. doesn’t explicitly teach the second oxide layer being deposited by chemical vapor deposition (As the second oxide layer comes from the modification made with Yamazaki).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to also have the second oxide layer deposited by chemical vapor deposition when it is introduced by Yamazaki, as done by Erk et al. for the first oxide layer, because chemical vapor deposition allows for the oxide layers to be deposited with better precision and uniformity, which improves the overall quality of the semiconductor device.
Claims 2-5 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Erk et al. (US
2019/0019721), Moore et al. (US 6,093,956), Yamazaki (2011/0127522 A1) as applied to claims 1 and 18,
respectively, above, and further in view of Shih et al. (US 8,951,884).
Regarding claim 2, Erk et al., as modified, does not explicitly teach a protective layer formed on
top of the first oxide layer before forming the compressive nitride layer.
Shih et al. teaches a protective layer (18) on top of the first oxide layer before the forming the
compressive nitride layer (Column 2, lines 51-53. The protective layer would be fully formed before
forming the modification of Moore et al. done in claim 1)
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to modify Erk et al., as modified, to form a protective layer over the first oxide
layer, as taught in Shih et al., to protect the first oxide layer from damage during the process of forming
the compressive nitride layer.
Regarding claim 3, Erk et al., as modified, does not explicitly teach removing the protective layer
on top of the first oxide layer after the forming the compressive nitride layer and before the forming the
second oxide layer.
Shih et al. teaches removing the protective layer on the top of the first oxide layer after forming
compressive nitride layer (The protective layer would be fully removed after forming the modification of
Moore et al. done in claim 1) and before forming the second oxide layer (Column 3, line 37-40 describes
the protective layer, 18, being removed followed by the formation of the second oxide layer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to modify Erk et al., as modified, to remove the protective layer after forming the
compressive nitride layer, as taught in Shih et al., since the first oxide layer would no longer need to be
protected once the compressive nitride layer is formed.
Regarding claim 4, Erk et al., as modified, does not explicitly teach the protective layer
comprising of an amorphous carbon or a nitride.
Shih et al. teaches a protective layer comprising an amorphous carbon or a nitride (Column 2,
line 54-55 states that the protective layer, 18, is a silicon nitride).
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to modify Erk et al., as modified, to form the protective layer of a nitride, as
taught in Shih et al., because a silicon nitride protective layer has high selectivity so when the protective
layer is removed the first oxide layer will not be ruined by the process (Shih et al., Column 1 lines 61-67).
Regarding claim 5, Erk et al. as modified is silent as to the specific thickness of protective layer
being 0.1 – 1 micrometers (but note Shih et al. where the protective layer is introduced teaches that the
devices would have many different thicknesses - see col 1 lines 7-10 and col 2 lines 44-50.)
MPEP 2144.05 IIB states that a particular parameter must first be recognized as a result effective
variable, i.e., a variable which achieves a recognizable result, before the determination of the optimum
or workable ranges of said variable might be characterized as routine experimentation. In re Antonie,
559 F.2d 618, 195 USPQ 6 (CCPA 1977).
It would be obvious to one of ordinary skill in the art before the effective filing date of the
claimed invention to further modify Erk et al. as modified to include the protective layer in the range of
0.1 - 1 micrometer in order to provide adequate protection for all the layers based on routine
optimization to maximize the functionality of the device by minimizing potential damage.
Regarding claim 19, Erk et al., as modified, does not explicitly teach a protective layer formed on
top of the first oxide layer before the forming the second nitride layer.
Shih et al. teaches a protective layer (18) on top of the first oxide layer before the forming the
second nitride layer (Column 2, lines 51-53. The protective layer would be fully formed before forming
the modification of Moore et al. done in claim 18)
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to modify Erk et al., as modified, to form a protective over the first oxide layer, as
taught in Shih et al., to protect the first oxide layer from damage during the process of forming the
second nitride layer.
Regarding claim 20, Erk et al., as modified, does not explicitly teach removing the protective
layer on top of the first oxide layer after the forming the second nitride layer and before the forming the
second oxide layer.
Shih et al. teaches removing the protective layer on the top of the first oxide layer after forming
second nitride layer (The protective layer would be fully removed after forming the modification of
Moore et al. done in claim 18) and before forming the second oxide layer (Column 3, line 37-40
describes the protective layer, 18, being removed followed by the formation of the second oxide layer)
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to modify Erk et al., as modified, to remove the protective layer after forming the
second nitride layer, as taught in Shih et al., since the first oxide layer would no longer need to be
protected once the second nitride layer is formed.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Erk et al. (US
2019/0019721), Moore et al. (US 6,093,956), Yamazaki (2011/0127522 A1), as applied to claims 1 and
18, respectively, above, and further in view of Zhou et al. (US 2022/0415649 A1).
Regarding claim 8, Erk et al., as modified, does not teach flipping the semiconductor wafer after
the forming the first oxide layer in order to expose the second surface onto which the compressive
nitride layer is formed, thus allowing for a smaller more compact device.
Zhou et al. teaches flipping the semiconductor wafer after the forming the first oxide layer in
order to expose the second surface onto which the compressive nitride layer is formed (Paragraph 6
describes the process of flipping the substrate over to deposit the backside layer. Paragraph 21 states
that the backside layer is a silicon nitride layer. Paragraph 0028 states that the backside film layer can
have compressive stress).
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to modify Erk et al., as modified, to flip the substrate, as taught in Zhou et al.,
because it is less costly and requires less additional materials than the alternative, which is depositing it
from underneath the substrate (Zhou et al. Paragraph 0004)
Regarding claim 9, Erk et al., as modified, does not teach flipping the semiconductor wafer after
the forming the compressive nitride layer in order to expose the first oxide layer.
Zhou et al teaches flipping the semiconductor wafer after forming the compressive nitride layer
in order to expose the first oxide layer (Paragraph 42, the exposed oxide layer comes from modified Erk
et al. in claim 1 before the addition of Yamazaki)
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to modify Erk et al., as modified, to flip the substrate back, as taught in Zhou et
al., because it less costly and requires less additional materials than the alternative, which is depositing
the following layer from underneath the substrate, especially since the substrate has been flipped
already (Zhou et al. Paragraph 0004).
Regarding claim 10, Erk et al., as modified, does not explicitly teach a bow of the semiconductor
wafer following the forming the second oxide layer is within ± 250 µm.
Zhou et al. teaches a bow of the semiconductor wafer following the forming of the second oxide
layer is within ± 250 µm (Paragraph 29 states that the bow is around 200 µm).
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to modify Erk et al., as modified, to have a semiconductor wafer with a bow
within ± 250 µm, as taught in Zhou et al., because excessive bowing can result in several issues including
misalignment, mechanical stress, pattern distortion.
Claims 13, 14, & 16 are rejected under 35 U.S.C. 103 as being unpatentable over Erk et al. (US
2019/0019721), Moore et al. (US 6,093,956), Yamazaki (2011/0127522 A1), as applied to claim 1 above, and further in view of Porter et al. (US 2023/0136819).
Regarding claim 13, Erk et al., as modified, does not teach a thickness of the compressive nitride
layer adjusted based on a bow of the semiconductor wafer following the forming the first oxide layer
and a desired thickness of the first oxide layer and the second oxide layer,
wherein the compressive nitride layer imparts a compressive stress on the second surface of the
semiconductor wafer to compensate for the desired thickness of the first oxide layer and the second
oxide layer.
Porter et al. teaches a thickness of the compressive nitride layer adjusted based on a bow of the
semiconductor wafer following the forming of the first oxide layer and a desired thickness of the first
oxide layer and the second oxide layer (Paragraph 9 describes adding more layers on the backside of the
wafer, comprising of nitride layers, till the desired bow is achieved).
Wherein the compressive nitride layer imparts a compressive stress on the second surface of
the semiconductor to compensate for the desired thickness of the first oxide layer and the second oxide
layer (A compressive nitride layer formed on the second surface will impart a compressive stress on the
second surface which will compensate for the first and oxide layer on the opposing surface).
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to modify Erk et al., as modified, to add compressive nitride layers to offset the
thickness of the oxide layer till a desired bow is achieved, as taught in Porter et a., because the
compressive nitride layer offsets the bow of the oxide layer, therefore adding compressive nitride layers
on the backside will decrease the bow of the wafer up to the point where a desired bow is achieved.
Regarding claim 14, Erk et al., as modified, does not explicitly teach a method wherein the
thickness of the compressive nitride layer is chosen by calculating a compressive stress offset of the
compressive nitride layer.
Moore et al. teaches the thickness of the compressive layer being chosen by calculating a
compressive stress offset of the compressive nitride layer (Column 5, lines 47-49)
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to modify Erk et al., as modified, to adjust the thickness of the compressive layer
based off of the stress of the layer, as taught by Moore et al., because this will make sure that the
compressive and tensile forces balance out and, therefore, make the wafer less likely to warp (Moore et
al. Column 5, lines 51-55).
Regarding claim 16, Erk et al., as modified, forming an additional compressive nitride layer and
forming an additional oxide layer until a desired total oxide layer thickness is achieved.
Porter et al. teaches forming an additional compressive nitride layer and forming an additional
oxide layer until a desired total oxide layer thickness is achieved (Paragraph 9 describes adding layers on the both sides of the wafer till a desired thickness is achieved. These layers can be oxide layers or nitride
layers)
It would have been obvious to one of ordinary skill in the art before the effective filing date of
the claimed invention to modify Erk et al., as modified, to add additional compressive nitride layers and
oxide layers till the desired oxide thickness is formed, as taught by Porter et al., because the oxide and
compressive nitride layer counteract the bow of the other so one would have to add both to thicken the
oxide layer to ensure that the bow doesn’t increase as you add thickness to the wafer.
Response to Arguments
Applicant’s arguments filed September 1st 2026, with respect to the rejections of claims 1 & 18 regarding the second oxide layer and the combined thickness of the two oxide layers have been fully considered and are persuasive. However, upon further search and consideration, a new ground of rejection was found made in view of Yamazaki which teaches the amended limitation. Therefore, Yu is no longer being used within the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
As all the applicant’s arguments are made in response to Yu (US 2009/0020791 A1) which is not used in the final rejection, the arguments made are no longer relevant to the above rejections.
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLOTTE ELIZABETH HARBOTTLE whose telephone number is (571)270-0644. The examiner can normally be reached Monday-Friday 7:30-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.E.H./Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
Prosecution Insights