CTNF 18/618,354 CTNF 102049 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Drawings 06-22 AIA The drawings are objected to because Figure 3A depicts an unlabeled 250 nm oxide layer between the thermal oxide layer and the tensile nitride layer that is not described in the specifications. This can be corrected by either properly labeling the oxide layer or removing the layer from the figure . Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Specification 07-29 AIA The disclosure is objected to because of the following informalities: Paragraph [0057] has no reference to the 250 nm oxide layer depicted in figure 3A. Either remove it from the figure or describe what it is within the specifications . Appropriate correction is required. Claim Objections 07-29-01 AIA Claim s 2-3, 8-10, 13, & 18-20 objected to because of the following informalities: In claims 2-3, 8-10, 13, & 19-20 “the forming the” should be “the forming of the” . Appropriate correction is required. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1, 6-7, 11-12, 15, & 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Erk et al. (US 2019/0019721) in view of Moore et al. (US 6,093,956) and Yu et al. (US 2009/0020791) Regarding Claim 1: Erk et al. teaches a method comprising: Forming a thermal oxide layer on a first surface and a second surface on a semiconductor wafer (Paragraph 44 describes oxidizing both the front and backside of the wafer, 100, to create a thermal oxide layer on both sides, 200 in Fig 3) Forming a tensile nitride layer (300, Paragraph 110 describes a nitride layer which would broadly be a tensile nitride layer as it has layers on both the top and bottom of it which is able to provide a tensile force, see also paragraph 50) on the first surface of the semiconductor wafer on top of the thermal oxide layer (Fig 3 shows the tensile nitride layer on top of the thermal oxide layer, 200) Forming a first oxide layer (400, Paragraph 110) on top of the tensile nitride layer (Figure 3 shows the first oxide layer, 400, on top of the nitride layer, 300, and the thermal oxide layer, 200) A sum of a thickness of the first oxide layer and the thickness of the second oxide layer is greater than or equal to 10 micrometers (While this reference does not teach a second oxide layer, Paragraph 41 states that an individual dielectric layer, including the oxide layer, is able to be 10000 nm which is equivalent to 10 micrometers even without the second oxide layer). Erk et al. does not explicitly teach forming a compressive nitride layer on the second surface of the semiconductor wafer on top of the thermal oxide layer; and forming a second oxide layer on top of the first oxide layer, where there is a sum of thicknesses of the first and second oxide layer. Moore et al. teaches a nitride layer (24a, which can be compressive as described in column 2, lines 58-60) that is formed on a second surface of the wafer (16, Column 3 lines 55-61 describes the silicon nitride layer on the second opposing surface) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Yu et al. to form a compressive nitride layer on the second (bottom) surface of the semiconductor wave on top of the thermal oxide layer as taught by Moore et al. in order to equalize a stress across the substrate to prevent deformation (Moore et al. - col 2 lines 11-18) allowing the semiconductor to enhance durability. However, Erk et al., as modified, still does not disclose a second oxide layer on top of the first oxide layer, where there is a sum of thicknesses of the first and second oxide layer. Yu et al. teaches a second oxide layer (160) on top of the first oxide layer (Fig 1D shows the second oxide layer formed on top of a first oxide layer 140, which is on top of a tensile nitride layer, 130) Wherein a sum of a thickness of the first oxide layer and the thickness of the second oxide layer is greater than or equal to 10 micrometers (As the thickness of the first oxide layer in Erk et al. is already greater than 10 micrometers, the addition of the second oxide layer will not affect this). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Erk et al. to form an additional/second buffer layer that is an oxide layer as taught by Yu et al. in order to provide protection as well having an extra layer that will help manage strain (including if any additional layers wanted to be added above the oxide layer - see Yu et al. end of paragraph 43) which would extend the life of the wafer. Noting: that for the last limitation of claim 1, the combination now has a second oxide layer that would add to the sum which is already greater than 10 micrometers. Regarding claim 6, Erk et al., as modified teaches a thermal oxide layer that has a thickness of 10-100 nm (Paragraph 43 describes the that each layer can have a thickness between 10-10,000 nm, which the range of 10-100 nm fits within) Regarding claim 7, Erk et al., as modified, teaches the sum of the thickness of the first oxide layer and the second oxide layer being between 10-20 micrometers (Paragraph 43 in Erk et al. has the range of the first oxide layer between 10-10,000 nm which the highest number fits in the given range, meanwhile Yu et al., as described in Paragraph 37, has the second oxide layer within the range of 30-200 angstroms. These two lengths combine fit within the range of 10-20 micrometers.) Regarding claim 11, Erk et al., as modified, teaches a thickness of the tensile nitride layer chosen based on a desired thickness of the first oxide layer and the second oxide layer (Thickness of the nitride layer is chosen by the inventor so it was chosen based on a desired thickness of the oxide layers), wherein the tensile nitride layer imparts a tensile stress on the first surface of the semiconductor wafer to compensate for the desired thickness of the first oxide layer and the second oxide layer (Erk et al. Paragraph 50). Regarding claim 12, Erk et al. does not explicitly teach a method wherein the thickness of the tensile nitride layer is chosen by calculating a tensile stress offset of the tensile nitride layer. Moore et al. teaches the thickness of the tensile layer being chosen by calculating a tensile stress offset of the tensile nitride layer (Column 5, lines 47-49) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Erk et al., as modified, to adjust the thickness of the tensile layer based off of the stress of the layer, as taught by Moore et al., because this will make sure that the compressive and tensile forces balance out and, therefore, make the wafer less likely to warp, (Moore et al. Column 5, lines 51-55). Regarding claim 15, Erk et al., as modified, discloses wherein the tensile nitride layer (Erk et al. paragraph 43 states the range is 10-10,000 nm) has a larger thickness than the compressive nitride layer (compressive nitride layer taught in from Moore et al. as seen in the rejection to claim 1 above has the layer being 1000 angstroms - col 5 lines 55-56, in the instances where the tensile nitride layer is above 100 nm the tensile nitride layer will have a larger thickness). Regarding claim 17, Erk et al., as modified, teaches that the tensile nitride layer and the compressive nitride layer impart a positive bow on the semiconductor wafer to offset a negative bow from the first oxide layer and the second oxide layer (Erk et al. modified has all the same layers as the application on the same side of the wafer, therefore the layers with a positive and a negative bow would offset in the same manner). Regarding Claim 18: Erk et al. teaches a method comprising: Forming a thermal oxide layer on a first surface and a second surface on a semiconductor wafer (Paragraph 44 describes oxidizing both the front and backside of the wafer, 100 to create a thermal oxide layer on both sides, 200 in Fig 3) Forming a first nitride layer having one of a tensile stress and a compressive stress on the first surface of the semiconductor (300, Paragraph 110 describes a nitride layer which has the capability of bringing compressive or tensile stress to the wafer) on the first surface of the semiconductor wafer (300 on the top surface of the wafer 100) Forming a first oxide layer (400, Paragraph 110) on top of the first nitride layer (Figure 3 shows the first oxide layer, 400, on top of the nitride layer, 300) A sum of a thickness of the first oxide layer and the thickness of the second oxide layer is greater than or equal to 10 micrometers (While this reference does not teach a second oxide layer, Paragraph 41 states that an individual dielectric layer, including the oxide layer, is able to be 10000 nm which is equivalent to 10 micrometers even without the second oxide layer) Erk et al. does not explicitly teach forming a second nitride layer on the second surface of the semiconductor wafer having the other of a tensile stress or compressive stress; and forming a second oxide layer on top of the first oxide layer, where there is a sum of thicknesses of the first and second oxide layer. Moore et al. teaches a nitride layer (24a, which can be compressive or tensile as described in column 2, lines 58-60) that is formed on a second surface of the wafer (16, Column 3 lines 55-63 describes the silicon nitride layer on the second opposing surface) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device described in Yu et al. to form a second nitride layer on the second (bottom) surface of the semiconductor wave as taught by Moore et al. in order to equalize a stress across the substrate to prevent deformation (Moore et al. - col 2 lines 11-18) allowing the semiconductor to enhance durability. However, Erk et al., as modified, still does not disclose a second oxide layer on top of the first oxide layer, where there is a sum of thicknesses of the first and second oxide layer. Yu et al. teaches a second oxide layer (160) on top of the first oxide layer (Fig 1D shows the second oxide layer formed on top of a first oxide layer 140, which is on top of a tensile nitride layer, 130) Wherein a sum of a thickness of the first oxide layer and the thickness of the second oxide layer is greater than or equal to 10 micrometers (As the thickness of the first oxide layer in Erk et al. is already greater than 10 micrometers, the addition of the second oxide layer will not affect this). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Erk et al. to form an additional/second buffer layer that is an oxide layer as taught by Yu et al. in order to provide protection as well having an extra layer that will help manage strain (including if any additional layers wanted to be added above the oxide layer - see Yu et al. end of paragraph 43) which would extend the life of the wafer. Noting: that for the last limitation of claim 1, the combination now has a second oxide layer that would add to the sum which is already greater than 10 micrometers . 07-22-aia AIA Claim s 2-5 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Erk et al. (US 2019/0019721), Moore et al. (US 6,093,956), Yu et al. (US 2009/0020791) as applied to claim s 1 and 18, respectively , above, and further in view of Shih et al. (US 8,951,884) . Regarding claim 2, Erk et al., as modified, does not explicitly teach a protective layer formed on top of the first oxide layer before the forming the compressive nitride layer. Shih et al. teaches a protective layer (18) on top of the first oxide layer before the forming the compressive nitride layer (Column 2, lines 51-53. The protective layer would be fully formed before forming the modification of Moore et al. done in claim 1) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Erk et al., as modified, to form a protective layer over the first oxide layer, as taught in Shih et al., to protect the first oxide layer from damage during the process of forming the compressive nitride layer. Regarding claim 3, Erk et al., as modified, does not explicitly teach removing the protective layer on top of the first oxide layer after the forming the compressive nitride layer and before the forming the second oxide layer. Shih et al. teaches removing the protective layer on the top of the first oxide layer after forming compressive nitride layer (The protective layer would be fully removed after forming the modification of Moore et al. done in claim 1) and before forming the second oxide layer (Column 3, line 37-40 describes the protective layer, 18, being removed followed by the formation of the second oxide layer). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Erk et al., as modified, to remove the protective layer after forming the compressive nitride layer, as taught in Shih et al., since the first oxide layer would no longer need to be protected once the compressive nitride layer is formed. Regarding claim 4, Erk et al., as modified, does not explicitly teach the protective layer comprising of an amorphous carbon or a nitride. Shih et al. teaches a protective layer comprising an amorphous carbon or a nitride (Column 2, line 54-55 states that the protective layer, 18, is a silicon nitride). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Erk et al., as modified, to form the protective layer of a nitride, as taught in Shih et al., because a silicon nitride protective layer has high selectivity so when the protective layer is removed the first oxide layer will not be ruined by the process (Shih et al., Column 1 lines 61-67). Regarding claim 5, Erk et al. as modified is silent as to the specific thickness of protective layer being 0.1 – 1 micrometers (but note Shih et al. where the protective layer is introduced teaches that the devices would have many different thicknesses - see col 1 lines 7-10 and col 2 lines 44-50.) MPEP 2144.05 IIB states that a particular parameter must first be recognized as a result effective variable, i.e., a variable which achieves a recognizable result, before the determination of the optimum or workable ranges of said variable might be characterized as routine experimentation. In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977). It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify Erk et al. as modified to include the protective layer in the range of 0.1 - 1 micrometer in order to provide adequate protection for all the layers based on routine optimization to maximize the functionality of the device by minimizing potential damage. Regarding claim 19, Erk et al., as modified, does not explicitly teach a protective layer formed on top of the first oxide layer before the forming the second nitride layer. Shih et al. teaches a protective layer (18) on top of the first oxide layer before the forming the second nitride layer (Column 2, lines 51-53. The protective layer would be fully formed before forming the modification of Moore et al. done in claim 18) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Erk et al., as modified, to form a protective over the first oxide layer, as taught in Shih et al., to protect the first oxide layer from damage during the process of forming the second nitride layer. Regarding claim 20, Erk et al., as modified, does not explicitly teach removing the protective layer on top of the first oxide layer after the forming the second nitride layer and before the forming the second oxide layer. Shih et al. teaches removing the protective layer on the top of the first oxide layer after forming second nitride layer (The protective layer would be fully removed after forming the modification of Moore et al. done in claim 18) and before forming the second oxide layer (Column 3, line 37-40 describes the protective layer, 18, being removed followed by the formation of the second oxide layer) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Erk et al., as modified, to remove the protective layer after forming the second nitride layer, as taught in Shih et al., since the first oxide layer would no longer need to be protected once the second nitride layer is formed . 07-22-aia AIA Claim s 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Erk et al. (US 2019/0019721), Moore et al. (US 6,093,956), Yu et al. (US 2009/0020791), ) as applied to claim s 1 and 18, respectively , above, and further in view of Zhou et al. (US 2022/0415649 A1) . Regarding claim 8, Erk et al., as modified, does not teach flipping the semiconductor wafer after the forming the first oxide layer in order to expose the second surface onto which the compressive nitride layer is formed, thus allowing for a smaller more compact device. Zhou et al. teaches flipping the semiconductor wafer after the forming the first oxide layer in order to expose the second surface onto which the compressive nitride layer is formed (Paragraph 6 describes the process of flipping the substrate over to deposit the backside layer. Paragraph 21 states that the backside layer is a silicon nitride layer. Paragraph 0028 states that the backside film layer can have compressive stress). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Erk et al., as modified, to flip the substrate, as taught in Zhou et al., because it is less costly and requires less additional materials than the alternative, which is depositing it from underneath the substrate (Zhou et al. Paragraph 0004) Regarding claim 9, Erk et al., as modified, does not teach flipping the semiconductor wafer after the forming the compressive nitride layer in order to expose the first oxide layer. Zhou et al teaches flipping the semiconductor wafer after forming the compressive nitride layer in order to expose the first oxide layer (Paragraph 42, the exposed oxide layer comes from modified Erk et al. in claim 1 before the addition of Yu et al.) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Erk et al., as modified, to flip the substrate back, as taught in Zhou et al., because it less costly and requires less additional materials than the alternative, which is depositing the following layer from underneath the substrate, especially since the substrate has been flipped already (Zhou et al. Paragraph 0004). Regarding claim 10, Erk et al., as modified, does not explicitly teach a bow of the semiconductor wafer following the forming the second oxide layer is within ± 250 µm. Zhou et al. teaches a bow of the semiconductor wafer following the forming of the second oxide layer is within ± 250 µm (Paragraph 29 states that the bow is around 200 µm). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Erk et al., as modified, to have a semiconductor wafer with a bow within ± 250 µm, as taught in Zhou et al., because excessive bowing can result in several issues including misalignment, mechanical stress, pattern distortion . 07-22-aia AIA Claim s 13, 14, & 16 are rejected under 35 U.S.C. 103 as being unpatentable over Erk et al. (US 2019/0019721), Moore et al. (US 6,093,956), Yu et al. (US 2009/0020791) , as applied to claim s 1 and 18, respectively , above, and further in view of Porter et al. (US 2023/0136819) . Regarding claim 13, Erk et al., as modified, does not teach a thickness of the compressive nitride layer adjusted based on a bow of the semiconductor wafer following the forming the first oxide layer and a desired thickness of the first oxide layer and the second oxide layer, wherein the compressive nitride layer imparts a compressive stress on the second surface of the semiconductor wafer to compensate for the desired thickness of the first oxide layer and the second oxide layer. Porter et al. teaches a thickness of the compressive nitride layer adjusted based on a bow of the semiconductor wafer following the forming of the first oxide layer and a desired thickness of the first oxide layer and the second oxide layer (Paragraph 9 describes adding more layers on the backside of the wafer, comprising of nitride layers, till the desired bow is achieved). Wherein the compressive nitride layer imparts a compressive stress on the second surface of the semiconductor to compensate for the desired thickness of the first oxide layer and the second oxide layer (A compressive nitride layer formed on the second surface will impart a compressive stress on the second surface which will compensate for the first and oxide layer on the opposing surface). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Erk et al., as modified, to add compressive nitride layers to offset the thickness of the oxide layer till a desired bow is achieved, as taught in Porter et a., because the compressive nitride layer offsets the bow of the oxide layer, therefore adding compressive nitride layers on the backside will decrease the bow of the wafer up to the point where a desired bow is achieved. Regarding claim 14, Erk et al., as modified, does not explicitly teach a method wherein the thickness of the compressive nitride layer is chosen by calculating a compressive stress offset of the compressive nitride layer. Moore et al. teaches the thickness of the compressive layer being chosen by calculating a compressive stress offset of the compressive nitride layer (Column 5, lines 47-49) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Erk et al., as modified, to adjust the thickness of the compressive layer based off of the stress of the layer, as taught by Moore et al., because this will make sure that the compressive and tensile forces balance out and, therefore, make the wafer less likely to warp (Moore et al. Column 5, lines 51-55) Regarding claim 16, Erk et al., as modified, forming an additional compressive nitride layer and forming an additional oxide layer until a desired total oxide layer thickness is achieved. Porter et al. teaches forming an additional compressive nitride layer and forming an additional oxide layer until a desired total oxide layer thickness is achieved (Paragraph 9 describes adding layers on the both sides of the wafer till a desired thickness is achieved. These layers can be oxide layers or nitride layers) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Erk et al., as modified, to add additional compressive nitride layers and oxide layers till the desired oxide thickness is formed, as taught by Porter et al., because the oxide and compressive nitride layer counteract the bow of the other so one would have to add both to thicken the oxide layer to ensure that the bow doesn’t increase as you add thickness to the wafer . Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure : Bhowmilk et al. (7,691,746 B2) shares a similar structure, having an oxide layer on both sides of the wafer followed by a silicon nitride layer on top of both of the oxide layers, then with an oxide layer on top of the nitride layer. Huang et al. (2024/0003010 A1) shares a compressive layer formed on the backside of a semiconductor wafer that has a tensile layer. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLOTTE ELIZABETH HARBOTTLE whose telephone number is (571)270-0644. The examiner can normally be reached Monday-Friday 7:30-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached at (571) 272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.E.H./Examiner, Art Unit 2818 /JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818 Application/Control Number: 18/618,354 Page 2 Art Unit: 2818 Application/Control Number: 18/618,354 Page 3 Art Unit: 2818 Application/Control Number: 18/618,354 Page 4 Art Unit: 2818 Application/Control Number: 18/618,354 Page 5 Art Unit: 2818 Application/Control Number: 18/618,354 Page 6 Art Unit: 2818 Application/Control Number: 18/618,354 Page 7 Art Unit: 2818 Application/Control Number: 18/618,354 Page 8 Art Unit: 2818 Application/Control Number: 18/618,354 Page 9 Art Unit: 2818 Application/Control Number: 18/618,354 Page 10 Art Unit: 2818 Application/Control Number: 18/618,354 Page 11 Art Unit: 2818 Application/Control Number: 18/618,354 Page 12 Art Unit: 2818 Application/Control Number: 18/618,354 Page 13 Art Unit: 2818 Application/Control Number: 18/618,354 Page 14 Art Unit: 2818 Application/Control Number: 18/618,354 Page 15 Art Unit: 2818 Application/Control Number: 18/618,354 Page 16 Art Unit: 2818
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