DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This OA is in response to the amendment filled on 9/14/2026 that has been entered, wherein claims 1-14 and 21-26 are pending and claims 15-20 are canceled.
Election/Restrictions
Applicant’s election without traverse of Invention I, claims 1-14 and 21-26 in the reply filed on 9/14/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/27/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim 1 provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claim 16 and 20 of copending Application No. 18/478,086 in view of Lin et al. (US 2025/0015079 A1) herein Lin ‘079.
Regarding claim 1, claim 16 of copending Application No. 18/478,086 recites a method for forming a semiconductor structure, comprising:
forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked;
forming an isolation structure;
forming a dummy gate structure across the fin structure over the isolation structure.
Claim 16 of copending Application No. 18/478,086 does not recites forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a fin element, forming an isolation structure to surround the fin element, forming a dummy gate dielectric layer across the fin structure; forming a dummy gate electrode layer on the dummy gate dielectric layer; partially etching the dummy gate electrode layer and the dummy gate dielectric layer to form a trench; removing the first semiconductor layers to form gaps; and
forming a gate stack on a remaining portion of the dummy gate electrode layer and filling the trench and the gaps.
Claim 21 of copending Application No. 18/478,086 does recites partially etching the dummy gate structure; removing the first semiconductor layers to form gaps; and
forming a gate stack on a remaining portion of the dummy gate structure and filling the gaps. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the combination of claims 16 and 21 of copending Application No. 18/478,086 recite claim 1 of the instant case.
Claims 16 and 21 of copending Application No. 18/478,086 do not recite forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a fin element, forming an isolation structure to surround the fin element, forming a dummy gate dielectric layer across the fin structure; forming a dummy gate electrode layer on the dummy gate dielectric layer; partially etching the dummy gate electrode layer and the dummy gate dielectric layer to form a trench; forming a gate stack on a remaining portion of the dummy gate electrode layer and filling the trench.
Lin ‘079 teaches a method for forming a semiconductor structure(Figs. 7, 8, 2 3A-3N, ¶0074), comprising:
forming a fin structure(102, 302’, ¶0037) in which first semiconductor layers(304, ¶0036) and second semiconductor layers(306, ¶0036) are alternately stacked over a fin element(102, ¶0037);
forming an isolation structure(106, ¶0038) to surround the fin element(102, ¶0037);
forming a dummy gate dielectric layer(310, 104w, ¶0049) across the fin structure(102, 302’, ¶0037);
forming a dummy gate electrode layer(312, ¶0049) on the dummy gate dielectric layer(310, 104w, ¶0049);
partially etching( ¶0076) the dummy gate electrode layer(312, ¶0049) and the dummy gate dielectric layer(310, 104w, ¶0049) to form a trench(Fig. 8B); and
forming a gate stack(120, ¶0067) on a remaining portion(750, ¶0071) of the dummy gate electrode layer(312, ¶0049) and filling the trench(Fig. 7). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Claims 16 and 21 of copending Application No. 18/478,086 to include forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked over a fin element, forming an isolation structure to surround the fin element, forming a dummy gate dielectric layer across the fin structure; forming a dummy gate electrode layer on the dummy gate dielectric layer; partially etching the dummy gate electrode layer and the dummy gate dielectric layer to form a trench; forming a gate stack on a remaining portion of the dummy gate electrode layer and filling the trench, as taught by Lin ‘079, in order to prevent the portions of the isolation structure between the gate spacers from further recessing below the surface(¶0049).
This is a provisional nonstatutory double patenting rejection.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-3, 5-7, 9-13 and 21-25 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin et al. (US 2025/0015079 A1) herein Lin ‘079.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1, Lin ‘079 teaches a method for forming a semiconductor structure(Figs. 7, 8, 2 3A-3N, ¶0074), comprising:
forming a fin structure(102, 302’, ¶0037) in which first semiconductor layers(304, ¶0036) and second semiconductor layers(306, ¶0036) are alternately stacked over a fin element(102, ¶0037);
forming an isolation structure(106, ¶0038) to surround the fin element(102, ¶0037);
forming a dummy gate dielectric layer(310, 104w, ¶0049) across the fin structure(102, 302’, ¶0037) over the isolation structure(106, ¶0038);
forming a dummy gate electrode layer(312, ¶0049) on the dummy gate dielectric layer(310, 104w, ¶0049);
partially etching( ¶0076) the dummy gate electrode layer(312, ¶0049) and the dummy gate dielectric layer(310, 104w, ¶0049) to form a trench(Fig. 8B);
removing(¶0050) the first semiconductor layers(304, ¶0036) to form gaps(Fig. 3N); and
forming a gate stack(120, ¶0067) on a remaining portion(750, ¶0071) of the dummy gate electrode layer(312, ¶0049) and filling the trench and the gaps(Fig. 7).
Regarding claim 2, Lin ‘079 teaches the method for forming the semiconductor structure as claimed in claim 1, wherein the remaining portion(750, ¶0071) of the dummy gate electrode layer(312, ¶0049) has a top surface that is lower than a top surface of the fin element(102, ¶0037).
Regarding claim 3, Lin ‘079 teaches the method for forming the semiconductor structure as claimed in claim 1, wherein forming the gate stack(120, ¶0067) on the remaining portion(750, ¶0071) of the dummy gate electrode layer(312, ¶0049) and filling the trench and the gaps comprises:
forming interfacial layers(132, ¶0047) on the second semiconductor layers(306, ¶0036);
forming a gate dielectric layer(122, ¶0051) over the interfacial layers(132, ¶0047); and
forming a metal gate electrode layer(124, ¶0022) over the gate dielectric layer(122, ¶0051).
Regarding claim 5, Lin ‘079 teaches the method for forming the semiconductor structure as claimed in claim 1, wherein the remaining portion(750, ¶0071) of the dummy gate electrode layer(312, ¶0049) protects the isolation structure(106, ¶0038) from being recessed(¶0049).
Regarding claim 6, Lin ‘079 teaches the method for forming the semiconductor structure as claimed in claim 1, wherein the remaining portion(750, ¶0071) of the dummy gate electrode layer(312, ¶0049) has a convex top surface(106S).
Regarding claim 7, Lin ‘079 teaches the method for forming the semiconductor structure as claimed in claim 1, further comprising:
recessing the isolation structure(106, ¶0038) to form a recess between the remaining portion(750, ¶0071) of the dummy gate electrode layer(312, ¶0049) and the fin element(102, ¶0037), wherein the gate stack(120, ¶0067) further fills the recess(Fig. 7).
Regarding claim 9, Lin ‘079 teaches the method for forming the semiconductor structure as claimed in claim 1, wherein after removing the first semiconductor layers(304, ¶0036) to form gaps, a remaining portion(750, ¶0071) of the dummy gate dielectric layer( 104w, ¶0049) remains between the remaining portion(750, ¶0071) of the dummy gate electrode layer(312, ¶0049) and the isolation structure(106, ¶0038).
Regarding claim 10, Lin ‘079 teaches a method for forming a semiconductor structure(Figs. 7, 8, 2 3A-3N, ¶0074), comprising:
forming a plurality of first active region
s(layers 102, 302’of 700a, ¶0037, ¶0068) in a first region of a substrate(region of 700a);
forming an isolation structure(106, ¶0038) to surround lower portions of the plurality of first active regions(layers 102, 302’of 700a, ¶0037, ¶0068);
forming a first dummy gate structure( layers 310, 104w, 312 of 700a, ¶0049, ¶0068) over the plurality of first active regions(layers 102, 302’of 700a, ¶0037, ¶0068);
etching the first dummy gate structure( layers 310, 104w, 312 of 700a, ¶0049, ¶0068), wherein a remaining portion(750, ¶0071) of the first dummy gate structure( layers 310, 104w, 312 of 700a, ¶0049, ¶0068) is provided on the isolation structure(106, ¶0038);
patterning upper portions of the plurality of first active regions(layers 102, 302’of 700a, ¶0037, ¶0068) to form a plurality of first nanostructures(110 of 700a ¶0043, ¶0068); and
forming a first gate stack(120, ¶0067) to surround the plurality of first nanostructures(110 of 700a ¶0043, ¶0068).
Regarding claim 11, Lin ‘079 teaches the method for forming the semiconductor structure as claimed in claim 10, wherein the first gate stack(120, ¶0067) is formed on the remaining portion(750, ¶0071) of the first dummy gate structure( layers 310, 104w, 312 of 700a, ¶0049, ¶0068).
Regarding claim 12, Lin ‘079 teaches the method for forming the semiconductor structure as claimed in claim 10, further comprising:
forming a plurality of second active regions(layers 102, 302’of 700c, ¶0037, ¶0070) in a second region of the substrate(region of 700c), wherein a first spacing between adjacent two of the first active regions(layers 102, 302’of 700a, ¶0037, ¶0068) is less(¶0070) than a second spacing between adjacent two of the second active regions(layers 102, 302’of 700c, ¶0037, ¶0070);
forming the isolation structure(106, ¶0038) to surround lower portions of the plurality of second active regions(layers 102, 302’of 700c, ¶0037, ¶0070);
forming a second dummy gate structure( layers 310, 104w, 312 of 700c, ¶0049, ¶0068) over the plurality of second active regions(layers 102, 302’of 700c, ¶0037, ¶0070);
etching the second dummy gate structure( layers 310, 104w, 312 of 700c, ¶0049, ¶0068) to expose the isolation structure(106, ¶0038); and
patterning the plurality of second active regions(layers 102, 302’of 700c, ¶0037, ¶0070) to form a plurality of second nanostructures(110 of 700c, ¶0043, ¶0070); and
forming a second gate stack(120, ¶0067) to surround the plurality of second nanostructures(110 of 700c, ¶0043, ¶0070).
Regarding claim 13, Lin ‘079 teaches the method for forming the semiconductor structure as claimed in claim 12, wherein after etching the first dummy gate structure( layers 310, 104w, 312 of 700a, ¶0049, ¶0068) and etching the second dummy gate structure( layers 310, 104w, 312 of 700c, ¶0049, ¶0068), a top surface of a first portion of the isolation structure(106, ¶0038) in the first region(region of 700a) is higher than a top surface of a second portion of the isolation structure(106, ¶0038) in the second region(region of 700b).
Regarding claim 21, Lin ‘079 teaches a method for forming a semiconductor structure(Figs. 7, 8, 2 3A-3N, ¶0074), comprising:
forming an active region(102, 302, ¶0037) over a substrate, wherein the active region(102, 302, ¶0037) includes a fin element(102, ¶0037) and a plurality of channel layers(110, ¶0043) over the fin element(102, ¶0037);
forming a dummy gate dielectric layer(310, 104w, ¶0049) over the active region(102, 302, ¶0037);
forming a dummy gate electrode layer(312, ¶0049) on the dummy gate dielectric layer(310, 104w, ¶0049);
forming a gate spacer layer(126, ¶0043) along a sidewall of the dummy gate electrode layer(312, ¶0049);
etching a first portion of the dummy gate electrode layer(312, ¶0049) to expose a first portion of the dummy gate dielectric layer(310, ¶0049), wherein after etching the first portion of the dummy gate electrode layer(312, ¶0049), a top surface of a second portion of the dummy gate electrode layer(750, ¶0071) is lower than a top surface of the fin element(102, ¶0037);
etching the first portion of the dummy gate dielectric layer(310, ¶0049); and
forming a gate stack(120, ¶0067) to surround the plurality of channel layers(110, ¶0043).
Regarding claim 22, Lin ‘079 teaches the method for forming the semiconductor structure as claimed in claim 21, wherein the gate stack(120, ¶0067) is formed on the second portion of the dummy gate electrode layer(750, ¶0071).
Regarding claim 23, Lin ‘079 teaches the method for forming the semiconductor structure as claimed in claim 21, wherein after etching the first portion of the dummy gate dielectric layer(310, ¶0049), a top surface of a second portion of the dummy gate dielectric layer(104w, ¶0049) is lower than the top surface of the fin element(102, ¶0037), and the gate stack(120, ¶0067) is formed on the second portion of the dummy gate dielectric layer(104w, ¶0049)
Regarding claim 24, Lin ‘079 teaches the method for forming the semiconductor structure as claimed in claim 21, further comprising:
forming an isolation structure(106, ¶0038) to surround the fin element(102, ¶0037), wherein during etching the first portion of the dummy gate dielectric layer(310, ¶0049), the second portion of the dummy gate electrode layer(750, ¶0071) protects the isolation structure(106, ¶0038) from being etched(¶0049).
Regarding claim 25, Lin ‘079 teaches the method for forming the semiconductor structure as claimed in claim 24, further comprising:
etching the active region(102, 302, ¶0037) to form a first recess(cavities,¶0044);
etching the isolation structure(106, ¶0038) to form a second recess(recess in 106 in region of 700c, ¶0070);
forming a source/drain feature(130, ¶0047) in the first recess(cavities,¶0044); and
forming a dielectric layer(132, ¶0047) to cover the source/drain feature(130, ¶0047) and fill the second recess(recess in 106 in region of 700c, ¶0070).
Claims 1, 3-5, 9-11 and 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lin et al. (US 2025/0113575 A1) herein Lin ‘575.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding claim 1, Lin ‘575 teaches a method for forming a semiconductor structure(Fig. 4, Fig. 1, ¶0103), comprising:
forming a fin structure(104, ¶0043) in which first semiconductor layers(106, ¶0043) and second semiconductor layers(108, ¶0043) are alternately stacked over a fin element(108, ¶0043);
forming an isolation structure(116, ¶0052) to surround the fin element(108, ¶0043);
forming a dummy gate dielectric layer(120, ¶0051) across the fin structure(104, ¶0043) over the isolation structure(116, ¶0052);
forming a dummy gate electrode layer(122, ¶0051) on the dummy gate dielectric layer(120, ¶0051);
partially etching(¶0082) the dummy gate electrode layer(122, ¶0051) and the dummy gate dielectric layer(120, ¶0051) to form a trench(139, ¶0104);
removing the first semiconductor layers(106, ¶0043) to form gaps(141, ¶0110); and
forming a gate stack(142, ¶0105) on a remaining portion of the dummy gate electrode layer(122’, ¶0104) and filling the trench(139, ¶0104) and the gaps(141, ¶0110).
Regarding claim 3, Lin ‘575 teaches the method for forming the semiconductor structure as claimed in claim 1, wherein forming the gate stack(142, ¶0105) on the remaining portion of the dummy gate electrode layer(122’, ¶0104) and filling the trench(139, ¶0104) and the gaps(141, ¶0110) comprises:
forming interfacial layers(144, ¶0105) on the second semiconductor layers(108, ¶0043);
forming a gate dielectric layer( portion of 146 on 144, ¶0105) over the interfacial layers(144, ¶0105); and
forming a metal gate electrode layer(148, ¶0087) over the gate dielectric layer( portion of 146 on 144, ¶0105).
Regarding claim 4, Lin ‘575 teaches the method for forming the semiconductor structure as claimed in claim 3, further comprising:
forming an oxide layer(portion of 146 on 122, ¶0105, ¶0086) on the remaining portion of the dummy gate electrode layer(122’, ¶0104) while forming the interfacial layers(144, ¶0105).
Regarding claim 5, Lin ‘575 teaches the method for forming the semiconductor structure as claimed in claim 1, wherein the remaining portion of the dummy gate electrode layer(122’, ¶0104) protects the isolation structure(116, ¶0052) from being recessed(Fig. 4).
Regarding claim 9, Lin ‘575 teaches the method for forming the semiconductor structure as claimed in claim 1, wherein after removing the first semiconductor layers(106, ¶0043) to form gaps(141, ¶0110), a remaining portion of the dummy gate dielectric layer(120’, ¶0104) remains between the remaining portion of the dummy gate electrode layer(122’, ¶0104) and the isolation structure(116, ¶0052).
Regarding claim 10, Lin ‘575 teaches a method for forming a semiconductor structure(Fig. 4, Fig. 1, ¶0103), comprising:
forming a plurality of first active regions(104, ¶0043) in a first region of a substrate(102);
forming an isolation structure(116, ¶0052) to surround lower portions of the plurality of first active regions(104, ¶0043);
forming a dummy gate electrode layer(122, ¶0051) over the plurality of first active regions(104, ¶0043);
etching(¶0082) the dummy gate electrode layer(122, ¶0051), wherein a remaining portion of the dummy gate electrode layer(122’, ¶0104) is provided on the isolation structure(116, ¶0052);
patterning upper portions of the plurality of first active regions(104, ¶0043) to form a plurality of first nanostructures(108’, ¶0105); and
forming a first gate stack(142, ¶0105) to surround the plurality of first nanostructures(108’, ¶0105).
Regarding claim 11, Lin ‘575 teaches the method for forming the semiconductor structure as claimed in claim 10, wherein the first gate stack(142, ¶0105) is formed on the remaining portion of the dummy gate electrode layer(122’, ¶0104).
Regarding claim 14, Lin ‘575 teaches the method for forming the semiconductor structure as claimed in claim 10, wherein the dummy gate electrode layer(122, ¶0051) includes a dummy gate dielectric layer(120, ¶0051) and a dummy gate electrode layer(122, ¶0051) over the dummy gate dielectric layer(120, ¶0051), and
etching(¶0082) the dummy gate electrode layer(122, ¶0051) comprises:
etching(¶0082) the dummy gate electrode layer(122, ¶0051) to expose a first portion of the dummy gate dielectric layer(120, ¶0051) while a second portion of the dummy gate dielectric layer(120, ¶0051) remains covered by the dummy gate electrode layer(122, ¶0051); and
etching(¶0082) the first portion of the dummy gate dielectric layer(120, ¶0051) to expose the plurality of first active regions(104, ¶0043).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 26 is rejected under 35 U.S.C. 103 as being obvious over Lin et al. (US 2025/0015079 A1) herein Lin ‘079 in view of Lin et al. (US 2025/0113575 A1) herein Lin ‘575.
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2).
Regarding claim 26, Lin ‘079 teaches the method for forming the semiconductor structure as claimed in claim 21, further comprising:
forming a layer(portion of 122 over 750, ¶0070) on the top surface of the second portion of the dummy gate electrode layer(750, ¶0071).
Lin ‘079 does not explicitly state an oxide layer(portion of 122 over 750, ¶0070). Lin ‘079 does teach a layer(portion of 122 over 750, ¶0070) that is part of the gate dielectric layer(122, ¶0070). Lin ‘579 teaches a gate dielectric layer(146, ¶0086) can be an oxide layer(¶0086). Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use an oxide layer, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. MPEP 2144.07
This rejection under 35 U.S.C. 103 might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C.102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B); or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement. See generally MPEP § 717.02.
Allowable Subject Matter
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding dependent claim 8, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “in a plan view, the gate dielectric layer surrounds the remaining portion of the dummy gate electrode layer.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lin et al. (US 2019/0386115 A1). Discloses a method for forming the semiconductor structure.
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/LAURA M DYKES/Examiner, Art Unit 2892
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