Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Status of Claims
1. Applicant's amendment of claims 1, 10, 11, and 20 in “Claims - 08/19/2026” with “Amendment/Req. Reconsideration-After Non-Final Reject - 08/19/2026”, have been acknowledged by Examiner.
This office action considers claims 1-20 pending for prosecution.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (100; Fig 3A; [0063]) = (element 100; Figure No. 3A; Paragraph No. [0063]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
2. Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wada et al. (US 20220406783 A1; hereinafter Wada).
Regarding claim 1, Wada teaches a semiconductor device (see the entire document, specifically Fig. 1+; [0086+], and as cited below), comprising:
a substrate (Sub; Fig. 9 in view of Fig. 5; see [0111]);
a stack of alternating first layers (103; Fig. 9; [0113]) and second layers (120; Fig. 9; [0119]) on a working surface of the substrate; and
a capacitor array (130; Fig. 9; see also Figs. 6, 41; see [0119, 0127]) including a plurality of capacitors (130; Fig. 9; see also Figs. 6, 41; see [0119, 0127]), wherein a common electrode (102; Fig. 9; see also Figs. 6, 41; see [0128]) of the capacitor array is disposed through the stack of alternating first layers (103; Fig. 9; [0113]) and second layers (120; Fig. 9; [0119]) on the working surface of the substrate, and each of the plurality of capacitors array (130; Fig. 9; see also Figs. 6, 41; see [0119, 0127]) is sandwiched between two adjacent first layers (103; Fig. 9; [0113]) and is contained within one (120; Fig. 9; [0119]) of the second layers (120; Fig. 9; [0119]) between the two adjacent first layers (103; Fig. 9; [0113]), each of the plurality of capacitors (130; Fig. 9; see also Figs. 6, 41; see [0119, 0127]) comprising:
a first electrode (131; Fig. 9; [0127-0128]) extending along a direction parallel to the working surface of the substrate and from the common electrode (102; Fig. 9; see also Figs. 6, 41; see [0128]) to one (120; Fig. 9; [0119]) of the second layers (120; Fig. 9; [0119]) between the two adjacent first layers (103; Fig. 9; [0113]),
a dielectric layer (133; Fig. 9; [0127-0129]) disposed over the first electrode (131; Fig. 9; [0127-0128]), and
a second electrode (134; Fig. 9; [0127-0130]) disposed over the dielectric layer (133; Fig. 9; [0127-0129]).
Regarding claim 2, Wada teaches all of the features of claim 1.
Wada further teaches wherein the first layers (103; Fig. 9; [0113]) are insulating layers.
Regarding claim 3, Wada teaches all of the features of claim 1.
Wada further teaches wherein the second layers (120; Fig. 9; [0119]) are conducting layers or sacrificial layers.
Regarding claim 4, Wada teaches all of the features of claim 1.
Wada further teaches wherein the first electrodes (131; Fig. 9; [0127-0128]) of the plurality of capacitors and the common electrode (102; Fig. 9; [0117]) of the capacitor array are formed of a same conducting material (see [0117, 0128]).
Regarding claim 5, Wada teaches all of the features of claim 1.
Wada further teaches wherein the dielectric layers (133; Fig. 9; [0127-0129]) of two adjacent capacitors are connected to each other through a dielectric layer (133; Fig. 9; [0127-0129]) surrounding a portion of the common electrode (102; Fig. 9; [0117]).
Regarding claim 6, Wada teaches all of the features of claim 5.
Wada further teaches wherein the portion of the common electrode (102; Fig. 9; [0117]) is between two adjacent second layers (120; Fig. 9; [0119]).
Regarding claim 7, Wada teaches all of the features of claim 5.
Wada further teaches wherein the dielectric layer (133; Fig. 9; [0127-0129]) surrounding the portion of the common electrode (102; Fig. 9; [0117]) is between the portion of the common electrode (102; Fig. 9; [0117]) and one of the first layers (103; Fig. 9; [0113]).
Regarding claim 8, Wada teaches all of the features of claim 1.
Wada further teaches wherein the first electrode (131; Fig. 9; [0127-0128]) of each of the plurality of capacitors has first and second surfaces parallel to the working surface of the substrate and a third surface perpendicular to the working surface of the substrate (see Figs. 9, 6, 41).
Regarding claim 9, Wada teaches all of the features of claim 8.
Wada further teaches wherein the dielectric layer (133; Fig. 9; [0127-0129]) of each of the plurality of capacitors has three portions, first and second portions of the dielectric layer (133; Fig. 9; [0127-0129]) respectively being disposed over the first and second surfaces of the first electrode (131; Fig. 9; [0127-0129]) of the respective capacitor, and a third portion of the dielectric layer (133; Fig. 9; [0127-0129]) being disposed over the third surface of the first electrode (131; Fig. 9; [0127-0129]) of the respective capacitor.
Regarding claim 10, Wada teaches all of the features of claim 9.
Wada further teaches wherein the second electrode (134; Fig. 9; [0127-0130]) of each of the plurality of capacitors includes:
a first portion of the second electrode being disposed over the first portion of the dielectric layer (133; Fig. 9; [0127-0130]) and between the first portion of the dielectric layer (133; Fig. 9; [0127-0130]) of the respective capacitor and one of the two adjacent first layers (103; Fig. 9; [0127-0130]) immediately above the one of the second layers (120; Fig. 9; [0127-0130]),
a second portion of the second electrode (134; Fig. 9; [0127-0130]) being disposed over the second portion of the dielectric layer (133; Fig. 9; [0127-0130]) and between the second portion of the dielectric layer (133; Fig. 9; [0127-0130]) of the respective capacitor and the other of the two adjacent first layers (103; Fig. 9; [0127-0130]) immediately below the one of the second layers (120; Fig. 9; [0127-0130]), and
a third portion of the second electrode (134; Fig. 9; [0127-0130]) being disposed over the third portion of the dielectric layer (133; Fig. 9; [0127-0130]) and between the third portion of the dielectric layer (133; Fig. 9; [0127-0130]) of the respective capacitor and the one of the second layers (120; Fig. 9; [0127-0130]).
Regarding claim 11, Wada teaches a method of manufacturing a semiconductor device (see the entire document, specifically Fig. 1+; [0086+], and as cited below), the method comprising:
forming a stack of alternating first layers (103; Fig. 9; [0113]) and second layers (120; Fig. 9; [0119]) on a working surface of a substrate (Sub; Fig. 9 in view of Fig. 5; see [0111]) of the semiconductor device; and
forming a capacitor array (130; Fig. 9; see also Figs. 6, 41; see [0119, 0127]) including a plurality of capacitors (130; Fig. 9; see also Figs. 6, 41; see [0119, 0127]),
wherein a common electrode (102; Fig. 9; see also Figs. 6, 41; see [0128]) of the capacitor array (130; Fig. 9; see also Figs. 6, 41; see [0119, 0127]) is disposed through the stack of alternating first layers (103; Fig. 9; [0113]) and second layers (120; Fig. 9; [0119]) on the working surface of the substrate, and each of the plurality of capacitors (130; Fig. 9; see also Figs. 6, 41; see [0119, 0127]) is sandwiched between two adjacent first layers (103; Fig. 9; [0113]) and is contained within one (120; Fig. 9; [0119]) of the second layers (120; Fig. 9; [0119]) between the two adjacent first layers (103; Fig. 9; [0113]), each of the plurality of capacitors (130; Fig. 9; see also Figs. 6, 41; see [0119, 0127]) comprising:
a first electrode (131; Fig. 9; [0127-0128]) extending along a direction parallel to the working surface of the substrate and from the common electrode (102; Fig. 9; see also Figs. 6, 41; see [0128]) to one (120; Fig. 9; [0119]) of the second layers (120; Fig. 9; [0119]) between the two adjacent first layers (103; Fig. 9; [0113]),
a dielectric layer (133; Fig. 9; [0127-0129]) disposed over the first electrode (131; Fig. 9; [0127-0128]), and
a second electrode (0134; Fig. 9; [0127-0130]) disposed over the dielectric layer (133; Fig. 9; [0127-0129]).
Regarding claim 12, Wada teaches all of the features of claim 11.
Wada further teaches wherein the first layers (103; Fig. 9; [0113]) are insulating layers.
Regarding claim 13, Wada teaches all of the features of claim 11.
Wada further teaches wherein the second layers (120; Fig. 9; [0119]) are conducting layers or sacrificial layers.
Regarding claim 14, Wada teaches all of the features of claim 11.
Wada further teaches wherein the first electrodes (131; Fig. 9; [0127-0128]) of the plurality of capacitors and the common electrode (102; Fig. 9; [0117]) of the capacitor array are formed of a same conducting material (see [0117, 0128]).
Regarding claim 15, Wada teaches all of the features of claim 11.
Wada further teaches wherein the dielectric layers (133; Fig. 9; [0127-0129]) of two adjacent capacitors are connected to each other through a dielectric layer (133; Fig. 9; [0127-0129]) surrounding a portion of the common electrode (102; Fig. 9; [0117]).
Regarding claim 16, Wada teaches all of the features of claim 15.
Wada further teaches wherein the portion of the common electrode (102; Fig. 9; [0117]) is between two adjacent second layers (120; Fig. 9; [0119]).
Regarding claim 17, Wada teaches all of the features of claim 15.
Wada further teaches wherein the dielectric layer (133; Fig. 9; [0127-0129]) surrounding the portion of the common electrode (102; Fig. 9; [0117]) is between the portion of the common electrode (102; Fig. 9; [0117]) and one of the first layers (103; Fig. 9; [0113]).
Regarding claim 18, Wada teaches all of the features of claim 11.
Wada further teaches wherein the first electrode (131; Fig. 9; [0127-0128]) of each of the plurality of capacitors has first and second surfaces parallel to the working surface of the substrate and a third surface perpendicular to the working surface of the substrate (see Figs. 9, 6, 41).
Regarding claim 19, Wada teaches all of the features of claim 18.
Wada further teaches wherein the dielectric layer (133; Fig. 9; [0127-0129]) of each of the plurality of capacitors has three portions, first and second portions of the dielectric layer (133; Fig. 9; [0127-0129]) respectively being disposed over the first and second surfaces of the first electrode (131; Fig. 9; [0127-0129]) of the respective capacitor, and a third portion of the dielectric layer (133; Fig. 9; [0127-0129]) being disposed over the third surface of the first electrode (131; Fig. 9; [0127-0129]) of the respective capacitor.
Regarding claim 20, Wada teaches all of the features of claim 19.
Wada further teaches wherein the second electrode (134; Fig. 9; [0127-0130]) of each of the plurality of capacitors includes:
a first portion of the second electrode being disposed over the first portion of the dielectric layer (133; Fig. 9; [0127-0130]) and between the first portion of the dielectric layer (133; Fig. 9; [0127-0130]) of the respective capacitor and one of the two adjacent first layers (103; Fig. 9; [0127-0130]) immediately above the one of the second layers (120; Fig. 9; [0127-0130]),
a second portion of the second electrode (134; Fig. 9; [0127-0130]) being disposed over the second portion of the dielectric layer (133; Fig. 9; [0127-0130]) and between the second portion of the dielectric layer (133; Fig. 9; [0127-0130]) of the respective capacitor and the other of the two adjacent first layers (103; Fig. 9; [0127-0130]) immediately below the one of the second layers (120; Fig. 9; [0127-0130]), and
a third portion of the second electrode (134; Fig. 9; [0127-0130]) being disposed over the third portion of the dielectric layer (133; Fig. 9; [0127-0130]) and between the third portion of the dielectric layer (133; Fig. 9; [0127-0130]) of the respective capacitor and the one of the second layers (120; Fig. 9; [0127-0130]).
Response to Arguments
Applicant's arguments filed in the “Applicant Arguments/Remarks Made in an Amendment” on 08/19/2026 have been fully considered, but they are not persuasive, because of the following: the Applicant's amendment of claims 1 and 11 necessitated the shift in new grounds of rejection detailed in sections above. Furthermore prior art of record Wada teaches each of the plurality of capacitors array (130; Fig. 9; see also Figs. 6, 41; see [0119, 0127]) is sandwiched between two adjacent first layers (103; Fig. 9; [0113]) and is contained within one (120; Fig. 9; [0119]) of the second layers (120; Fig. 9; [0119]) between the two adjacent first layers (103; Fig. 9; [0113]), each of the plurality of capacitors (130; Fig. 9; see also Figs. 6, 41; see [0119, 0127]). The shift in grounds of rejection renders the Applicant's arguments moot.
Please see the analysis of rejection for claims above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/OMAR F MOJADDEDI/Examiner, Art Unit 2898
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