Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the Applicant Election filled on 07/07/2026. Currently, claims 1-15 and 21-25 are pending in the application. Claims 5 and 16-20 have been withdrawn from consideration and claims 16-20 have been cancelled.
Election/Restrictions
Applicant's election without traverse of Group I and Species IN (Figures 14), claims 1- 4, 6-15 and 21-25, in the reply filed on 07/07/2026 is acknowledged, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ko et al (US 20240063070 A1).
Regarding claim 1, Figure 15 of Ko discloses a package structure, comprising:
a redistribution structure (700, [0096]);
a first package (211, [0089]) component and a second package component (311, [0094]) attached to a first side of the redistribution structure;
an underfill (401, [0097]) over the redistribution structure around lower portions of the first package component and the second package component (considering the lower solder balls are part of the package components 211 and 311); and
a molding layer (910, [0096])) formed over the underfill and around upper portions of the first package component and the second package component, wherein the molding layer comprises:
a base material ([0068] and [0096]); and
fillers embedded in the base material, wherein a thermal conductivity of the fillers is greater than about 400W/mK ([0068], metal power or graphene powder having thermal conductivity above 400W/mK).
Claim 21 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al (US 20210098421 A1).
Regarding claim 21, Figure 7 of Wu discloses a package structure, comprising:
a first redistribution structure (350, [0057]) and a second redistribution structure (110, [0020]) spaced apart from the first redistribution structure;
a semiconductor die (530, [0074]) between the first redistribution structure and the second redistribution structure;
a through insulating via (120, [0020]) between the first redistribution structure and the second redistribution structure and laterally spaced apart from the semiconductor die, wherein the through insulating via electrically connects the first redistribution structure (350) to the second redistribution structure (110);
a first package component (200A, [0038]) attached to the first redistribution structure (350) on a side opposite the semiconductor die;
a molding layer (210,[0081]) over the first redistribution structure and laterally surrounding the first package component (200A), wherein the molding layer comprises a base material and fillers embedded in the base material, wherein a thermal conductivity of the fillers (212) is greater than a thermal conductivity of the base material ([0043]); and
a conductive connector (300, [0046]) on the second redistribution structure (110) on a side opposite the semiconductor die (530).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-15 and 22-25 are rejected under 35 U.S.C. 103 as being obvious over Wu et al (US 20210098421 A1) in view of NAM et al (US 20220189907 A1) and Ko et al (US 20240063070 A1).
Regarding claim 1, Figure 7 of Wu discloses a package structure, comprising:
a redistribution structure (350, [0057]);
a first package component (200A, [0038]) and a second package component (200B, [0038]) attached to a first side of the redistribution structure; and
a molding layer (210, [0043]) formed around upper portions of the first package component and the second package component, wherein the molding layer comprises:
a base material ([0043]); and
fillers (212, [0043]) embedded in the base material.
Wu does not teach an underfill over the redistribution structure around lower portions of the first package component and the second package component.
However, NAM is a pertinent art which teaches a semiconductor package including an interposer substrate, first to third semiconductor chips on the interposer substrate to face each other, an underfill part between each of the first to third semiconductor chips and the interposer substrate, a first side-fill part extending upward from a lower end of side walls of the first to third semiconductor chips, and a second side-fill part between the side walls of the first to third semiconductor chips and extending from the first side-fill part to an upper end of the side walls of the first to third semiconductor chips may be provided. Figures 1-3 of NAM teach such a semiconductor package with an underfill layer 230 and second fill layer 251 for improved reliability ([0004]-[0007]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wu with an underfill over the redistribution structure around lower portions of the first package component and the second package component under the molding layer according to the teaching of NAM in order to improve the mechanical integrity and improve reliability of the package structure ([0004]-[0007] of NAM).
Wu, further, does not teach wherein a thermal conductivity of the fillers is greater than about 400W/mK.
Further, Ko is a pertinent art which teaches method of forming a semiconductor package wherein Ko teaches molding material having filler dispersed in the insulating resin. In example embodiments, the filler of the preliminary molding layer 501 (same for 901 in Figure 15) may include, but is not limited to, metal powder or graphene powder, each of which has high thermal conductivity (these materials having thermal conductivity greater than 400W/mK) ([0068]), wherein the underfill layer 401 (Figure 15) does not use fillers with higher conductivity.
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to use fillers such as metal powder or graphene powder in the package structure of Wu according to the teaching of Ko, wherein a thermal conductivity of the fillers is greater than about 400W/mK in order to achieve higher thermal conductivity in the molding layer in contact with external environment ([0068] of Ko).
Regarding claim 2, Figure 7 of Wu in view of NAM and Ko teach that the package structure of claim 1, wherein the molding layer has a first portion between the upper portions of the first package component and the second package component, the underfill has a second portion between the lower portions of the first package component and the second package component, a thickness of the first portion of the molding layer is greater than a thickness of the second portion of the underfill (Figure 1-3 of NAM teach the underfill 230 under upper fill 251).
Regarding claim 3, Figure 7 of Wu in view of NAM and Ko teach that the package structure of claim 1, further comprising: a dummy die (200C, Figure 7 of Wu) attached to the first side of the redistribution structure and spaced apart from the first package component, wherein the molding layer (210, Figure 7 of Wu) extends between the dummy die and the first package component.
Regarding claim 4, Figure 7 of Wu in view of NAM and Ko teach that the package structure of claim 3, wherein the molding layer extends between the dummy die and the second package component (Figures 1-3 of NAM teach the molding layer between the chips 211 and 212).
Regarding claim 6, Figure 7 of Wu in view of NAM and Ko teach that the package structure of claim 1, wherein the fillers comprise graphite, graphene, or diamond-like carbon ([0068] of Ko).
Regarding claim 7, Figure 7 of Wu in view of NAM and Ko do not teach that the package structure of claim 1, wherein a concentration of the fillers in the molding layer is in a range between 20 wt% and 8o wt%.
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to use the above claimed ranges in order to have package with higher thermal conductivity ([0068] of Ko) since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working range involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 8, Figure 7 of Wu disclose a package structure, comprising:
a first redistribution structure (350, [0081]);
a first package component (200A, [0038]) and a second package component (200B, [0038]) attached to a first side of the first redistribution structure (350) and spaced apart from each other;
a first molding layer (210, [0043]) over the underfill and over the first side of the first redistribution structure; and
a first semiconductor die (530, [0074]) attached to a second side of the first redistribution structure (350), wherein the first semiconductor die (530) partially overlaps the first package component and the second package component in a top view.
Wu does not teach an underfill around the first package component and the second package component;
However, NAM is a pertinent art which teaches a semiconductor package including an interposer substrate, first to third semiconductor chips on the interposer substrate to face each other, an underfill part between each of the first to third semiconductor chips and the interposer substrate, a first side-fill part extending upward from a lower end of side walls of the first to third semiconductor chips, and a second side-fill part between the side walls of the first to third semiconductor chips and extending from the first side-fill part to an upper end of the side walls of the first to third semiconductor chips may be provided. Figures 1-3 of NAM teach such a semiconductor package with an underfill layer 230 and second fill layer 251 for improved reliability ([0004]-[0007]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wu with an underfill around the first package component and the second package component according to the teaching of NAM in order to improve the mechanical integrity and improve reliability of the package structure ([0004]-[0007] of NAM).
Wu, further, does not teach wherein the first molding layer comprises first carbon-made particles and wherein a thermal conductivity of the first molding layer is greater than a thermal conductivity of the underfill.
Further, Ko is a pertinent art which teaches method of forming a semiconductor package wherein Ko teaches molding material having filler dispersed in the insulating resin. In example embodiments, the filler of the preliminary molding layer 501 (same for 901 in Figure 15) may include, but is not limited to, metal powder or graphene powder, each of which has high thermal conductivity (materials having thermal conductivity greater than 400W/mK) ([0068]), wherein the underfill layer 401 (Figure 15) does not use filler with higher conductivity.
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to use the first molding layer comprises first carbon-made particles such as graphene, and wherein a thermal conductivity of the first molding layer is greater than a thermal conductivity of the underfill in the package structure of Wu according to the teaching of Ko in order to achieve higher thermal conductivity in the molding layer in contact with external environment ([0068] of Ko).
Regarding claim 9, Figure 7 of Wu in view of NAM and Ko teach that the package structure of claim 8, wherein the first carbon-made particles are graphite or diamond-like carbon ([0068] of Ko).
Regarding claim 10, Figure 7 of Wu discloses that the package structure of claim 8, further comprising a second redistribution structure (110, [0020]) attached to the first semiconductor die (530); and a second molding layer (140) around the first semiconductor die.
Wu does not teach wherein the second molding layer (140) comprises second carbon-made particles.
Further, Ko which is a pertinent art here, teaches the filler of the preliminary molding layer 501 (same for 901 in Figure 15) may include, but is not limited to, metal powder or graphene powder, each of which has high thermal conductivity (materials having thermal conductivity greater than 400W/mK) ([0068]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to use a second molding layer comprises second carbon-made particles in the package structure of Wu according to the teaching of Ko in order to achieve higher thermal conductivity in the second molding layer ([0068] of Ko).
Regarding claim 11, Figure 7 of Wu in view of NAM and Ko do not explicitly teach that the package structure of claim 10, wherein the first carbon-made particles are different from the second carbon-made particles.
However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use he first carbon-made particles are different from the second carbon-made particles in the package structure of Wu for specific thermal conductivity for improved performance and lowering the cost of manufacturing according to the teaching Ko ([0068]), since it has been held to be within the general skill of a worker in the art to select a known material such as different carbon-made particle for different molding layer on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416 (CCPA 1960).
Regarding claim 12, Figure 7 of Wu discloses that the package structure of claim 8, further comprising: a dummy die (200C, [0038]) attached to the first side of the first redistribution structure (350); and a third package component (please see Figure 2 for more dies) attached to the first side of the first redistribution structure (350), wherein the first molding layer (210) is in contact with the dummy die and the third package component.
Regarding claim 13, Figure 7 of Wu discloses that the package structure of claim 12, wherein the first semiconductor die (530) partially overlaps the dummy die in the top view since rearranging parts of an invention involves only routine skill in the art. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950).
Regarding claim 14, Figure 7 of Wu discloses that the package structure of claim 13, wherein the first semiconductor die partially overlaps the third package component in the top view since rearranging parts of an invention involves only routine skill in the art. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950).
Regarding claim 15, Figure 7 of Wu in view of NAM and Ko teaches that the package structure of claim 8, wherein the first package component (200A) has a first sidewall surface facing the second package component (200A) in a first direction, wherein a contact height between the first sidewall surface and the first molding layer (210) is greater than a contact height between the first sidewall surface and the underfill (Figures 1-3 of NAM teaches the underfill layer).
Regarding claim 22, Figure 7 of Wu does not teach that that the package structure of claim 21, further comprising an underfill between the first package component and the first redistribution structure, wherein the underfill covers a lower portion of a sidewall of the first package component, wherein the molding layer covers an upper portion of the sidewall of the first package component, wherein a thermal conductivity of the molding layer is greater than a thermal conductivity of the underfill.
However, NAM is a pertinent art which teaches a semiconductor package including an interposer substrate, first to third semiconductor chips on the interposer substrate to face each other, an underfill part between each of the first to third semiconductor chips and the interposer substrate, a first side-fill part extending upward from a lower end of side walls of the first to third semiconductor chips, and a second side-fill part between the side walls of the first to third semiconductor chips and extending from the first side-fill part to an upper end of the side walls of the first to third semiconductor chips may be provided. Figures 1-3 of NAM teach such a semiconductor package with an underfill layer 230 and second fill layer 251 for improved reliability ([0004]-[0007]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Wu with an underfill between the first package component and the first redistribution structure, wherein the underfill covers a lower portion of a sidewall of the first package component, wherein the molding layer covers an upper portion of the sidewall of the first package component according to the teaching of NAM in order to improve the mechanical integrity and improve reliability of the package structure ([0004]-[0007] of NAM).
Further, Ko is a pertinent art which teaches method of forming a semiconductor package wherein Ko teaches molding material having filler dispersed in the insulating resin. In example embodiments, the filler of the preliminary molding layer 501 (same for 901 in Figure 15) may include, but is not limited to, metal powder or graphene powder, each of which has high thermal conductivity (materials having thermal conductivity greater than 400W/mK) ([0068]), wherein the underfill layer 401 (Figure 15) does not use filler with higher conductivity.
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to use the first molding layer comprises fillers, wherein a thermal conductivity of the first molding layer is greater than a thermal conductivity of the underfill in the package structure of Wu according to the teaching of Ko in order to achieve higher thermal conductivity in the molding layer in contact with external environment ([0068] of Ko).
Regarding claim 23, Figure 7 of Wu in view of NAM and Ko teach that the package structure of claim 21, further comprising a second package component attached to the first redistribution structure adjacent the first package component, wherein the semiconductor die (530) overlaps the first package component (200A) and the second package component (200B) in a plan view.
Regarding claim 24, Figure 7 of Wu in view of NAM and Ko teach that the package structure of claim 21, wherein a thermal conductivity of the fillers is greater than about 400W/mK ([0068] of Ko teaches material such as graphene meets this limitation).
Regarding claim 25, Figure 7 of Wu discloses that the package structure of claim 21, further comprising a second molding layer (140) laterally surrounding the semiconductor die (530) and the through insulating via (120), wherein the second molding layer comprises second fillers (142, [0043]) embedded in a second base material, wherein the fillers of the molding layer are different from the second fillers of the second molding layer (considering filler with higher conductivity in the external molding layer according to Ko and regular filler in the internal molding layer), and wherein the base material of the molding layer is a same material as the second base material of the second molding layer (Wu teaches both 140 and 210 having same base material, [0043]).
Examiner Notes
A reference to specific paragraphs, columns, pages, or figures in a cited prior art reference is not limited to preferred embodiments or any specific examples. It is well settled that a prior art reference, in its entirety, must be considered for all that it expressly teaches and fairly suggests to one having ordinary skill in the art. Stated differently, a prior art disclosure reading on a limitation of Applicant's claim cannot be ignored on the ground that other embodiments disclosed were instead cited. Therefore, the Examiner's citation to a specific portion of a single prior art reference is not intended to exclusively dictate, but rather, to demonstrate an exemplary disclosure commensurate with the specific limitations being addressed. In re Heck, 699 F.2d 1331, 1332-33,216 USPQ 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 USPQ 275, 277 (CCPA 1968)). In re: Upsher-Smith Labs. v. Pamlab, LLC, 412 F.3d 1319, 1323, 75 USPQ2d 1213, 1215 (Fed. Cir. 2005); In re Fritch, 972 F.2d 1260, 1264, 23 USPQ2d 1780, 1782 (Fed. Cir. 1992); Merck& Co. v. BiocraftLabs., Inc., 874 F.2d 804, 807, 10 USPQ2d 1843, 1846 (Fed. Cir. 1989); In re Fracalossi, 681 F.2d 792,794 n.1, 215 USPQ 569, 570 n.1 (CCPA 1982); In re Lamberti, 545 F.2d 747, 750, 192 USPQ 278, 280 (CCPA 1976); In re Bozek, 416 F.2d 1385, 1390, 163 USPQ 545, 549 (CCPA 1969).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAJA AHMAD whose telephone number is (571)270-7991. The examiner can normally be reached on Monday-Friday, 8:00 AM - 5:00 PM (Eastern Time).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice .
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHAJA AHMAD/Primary Examiner, Art Unit 2813
Prosecution Insights