DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “epoxy resin” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 2 are rejected under 35 U.S.C. 103 as being unpatentable over Ishino et al. (US 9,729,044 B2)
Ishino discloses an electronic device comprising:
a plurality of layers having a first major surface and a second major surface opposite the first major surface (see Fig. 1C, stack of layers forming module with two major surfaces; Col. 9, lines 22-27);
a polymer support layer (7) along the first major surface of the plurality of layers (mold resin 7 encapsulates the device components, serving as a support layer, Col. 9, lines 45-50); and
a heat sink physically coupled to the second major surface of the plurality of layers (FIG. 1C, a part of the lead frame 3 and a part of the lead frame 4 are exposed from the mold resin 7 and function as heat sinks 3h and 4h, respectively; Col. 11, lines 16-22; Col. 15, lines 54-60), wherein:
the heat sink includes a heat sink structure, a thermally conductive epoxy resin, and a heat sink layer (Col. 16, lines 9-17; a heat-sinking and insulating sheet (for example, epoxy-based resin mixed with inorganic filler, such as Al2O3 , BN, and AlN, so as to have high thermal conductivity) may be interposed between the heat sink and the water-cooling cooler.),
the heat sink layer is thermally conductive and electrically insulating (Col. 16, lines 13-18), and
the thermally conductive epoxy resin is disposed between the heat sink layer and the heat sink structure (Col. 16, lines 9-17; describes a layer of thermal grease between a ceramic substrate and a heat sink, which aligns with the claimed spatial arrangement).
The limitation that the heat sink layer is disposed between the plurality of layers and the thermally conductive epoxy resin would have been obvious over Ishino which expressly teaches that a “heat-sinking and insulating sheet” may be interposed between the heat sink and the water-cooling cooler, and further teaches that this sheet may be formed of an epoxy-based resin mixed with inorganic filler, such as Al2O3, BN, and AlN, so as to have high thermal conductivity. See Col. 16, lines 9–17. This teaching would have suggested to a person of ordinary skill in the art that a thermally conductive, electrically insulating sheet or layer may be positioned between a semiconductor structure and a heat-transfer structure to improve thermal conduction while maintaining electrical isolation. Accordingly, it would have been obvious to interpose the claimed heat sink layer between the plurality of layers and the thermally conductive epoxy resin as a predictable thermal-management modification.
Regarding claim 2, Ishino disclose the electronic device of claim 1 as described above, wherein the heat sink layer includes AIN. Ishino teaches a heat-sinking and insulating sheet that may include inorganic filler such as AlN (Col. 16, lines 8-17).
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Ishino et al. in view of Yoshimi et al. (US 2007/0228554).
Regarding claim 3, Ishino discloses the electronic device of claim 1. Yoshimi expressly teaches that the heat sink or radiator may be formed of a thermally conductive metal such as copper or aluminum, both of which are electrically conductive materials. (Para [0026]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to use such a metal heat sink structure in the device of Ishino because metals such as copper and aluminum are conventional heat sink materials that provide efficient thermal dissipation and would have been recognized by a person of ordinary skill in the art as electrically conductive heat sink structures suitable for semiconductor packaging.
Therefore, claim 3 would have been obvious over Ishino in view of Yoshimi.
Regarding 4, Ishino in view of Yoshimi disclose the electronic device of claim 3, wherein the heat sink structure is thermally conductive. Yoshimi expressly teaches that the heat sink/radiator may be made of copper or aluminum and that a preferable heat sink material has thermal conductivity higher than that of the semiconductor substrate. Accordingly, Yoshimi teaches or suggests that the heat sink structure is thermally conductive.
It would have been obvious to apply this known thermally conductive heat sink structure to the device taught by Yoshimi in Ishino to improve heat dissipation.
Claims 6, 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Ishino as applied to claim 1 above, and further in view of Farnsworth et al. (US 7,221,059).
Ishino discloses the electronic device of claim 1, but fails to detail a first spacer structure along the first major surface of the plurality of layers.
Farnsworth teaches a device having support structures along a major surface of a plurality of layers, including polymer support features used during thinning and singulation.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the device of Ishino to include a first spacer structure along the first major surface of the plurality of layers as taught by Farnsworth, in order to provide additional mechanical support, spacing, and packaging stability during wafer processing and handling.
Regarding claim 8, Ishino in view of Farnsworth discloses the electronic device of claim 6, wherein the first spacer structure includes an inorganic oxide, nitride, or oxynitride or a different polymer as compared to the polymer support layer (Col. 9, lines 24-28).
Regarding claim 9, Ishino in view of Farnsworth discloses the electronic device of claim 6.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the device of Ishino in view of Farnsworth to further include a second spacer structure along the first major surface of the plurality of layers, with the polymer support layer disposed between and contacting sides of the first spacer structure and the second spacer structure. Farnsworth teaches support and spacing structures used in wafer-level semiconductor packaging to provide mechanical reinforcement and to control the relative positioning of package components during fabrication and singulation. Providing a second spacer structure in addition to the first spacer structure would have been a predictable design choice to increase structural stability, improve handling robustness, and better define the support region for the polymer support layer. The resulting arrangement, in which the polymer support layer is located between and contacts the sides of the first and second spacer structures, would have been an obvious and expected packaging configuration for securing and supporting the layered device during processing.
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Ishino et al. in view of Farnsworth et al. (US 7,221,059) as applied to claim 6 above, further in view of Yoshimi et al. (US 2007/0228554).
Ishino in view of Farnsworth discloses the electronic device of claim 6, but does not explicitly disclose the first spacer structure is an electrically conductive member.
Yoshimi expressly teaches the use of thermally conductive metal such as copper or aluminum, both of which are electrically conductive materials. (Para [0026]).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the device of Ishino in view Farnsworth to have the first spacer structure be an electrically conductive member, because Yoshimi teaches that electrically conductive metals such as copper and aluminum are conventional thermally conductive materials for semiconductor thermal management structures, and using such a material for the spacer structure would have predictably provided improved thermal spreading and structural integration in the packaged device.
Claims 1 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Farnworth in view of Ishino et al.
Farnworth discloses a wafer-level semiconductor component having a plurality of layers, including a circuit side polymer layer, a back side polymer layer, and edge polymer layers, with the component encapsulating a die and associated structures. (Farnworth; FIGS. 1A-1K, 4A-4C). Farnworth et al. further discloses an embodiment in which a heat sink is attached to the thinned backside of the semiconductor substrate (FIG. 6B).
Ishino et al. teaches semiconductor element modules molded with resin and having heat sinks disposed on opposite surfaces of the module to improve thermal radiation performance and package reliability (FIGS. 1A-2C, 6A-6B).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the semiconductor component of Farnworth et al. in view of Ishino et al. to include a heat sink structure physically coupled to the device, because both references are directed to semiconductor packaging and thermal management, and the combination would have predictably improved heat dissipation, reduced operating temperature, and enhanced package reliability.
Regarding claim 21, Farnworth et al. in view of Ishino et al. discloses electronic device of claim 1.
Farnworth et al. discloses a wafer-level semiconductor component having a plurality of dice separated by streets, with trenches formed in the streets and polymer material disposed therein, as well as a heat sink embodiment attached to the thinned backside of the component. (FIGS. 2A-3J, 6B).
It would have been obvious to one of ordinary skill in the art at the time the invention was made to modify the device of Farnworth et al. in view of Ishino et al. to provide a heat sink structure overlying adjacent layered regions of the device and the intervening separation region, because both references are directed to improving thermal management in semiconductor packages, and extending the thermal structure across adjacent regions would have been a predictable packaging modification to improve heat spreading and thermal uniformity.
Response to Arguments
Applicant’s arguments with respect to the claim have been considered but are moot because the new ground of rejections as set for the above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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