DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-16 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/6/2026.
Applicant’s election without traverse of invention II, claims 17-20 in the reply filed on 7/6/2026 is acknowledged.
Status of Claims
Claims 1-16 have been cancelled, claims 17-20 are elected and new claims 21-36 have been added.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 25-32 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. New independent claim 25 recited method step of forming a first pedestal structure and a second pedestal structure. However, the examiner couldn’t find the features “pedestal structure” in the specification, therefore the feature “pedestal structure” is new matter.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 25-32 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
New independent claim 25 recited method step of forming a first pedestal structure and a second pedestal structure. However, “pedestal structure” has not been clearly defined in the specification. Therefore, the scope of the limitation “pedestal structure” is unclear and indefinite. In the interest of prosecution “pedestal structure” will be interpreted as “fin structure”, as claimed in the independent claim 17.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 17, 19-20, 23, 25-26 and 31-36 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ting, US 2020/0357802.
Regarding claim 17, Ting discloses; a method for forming an integrated chip, comprising: patterning a substrate to form a first fin structure and a second fin structure over a base region of the substrate (Fig. 2 and [0015]; substrate 110 patterned by performing one or more etching steps, thereby forming fins 218); forming a first source/drain region on the first fin structure and a second source/drain region on the second fin structure (Fig. 8 and [0031]; formation of the source/drain regions 834 on the fins 218); depositing a gate dielectric layer over the substrate and along sidewalls of the first and second fin structures (Fig. 5 and [0023]; gate insulator layer 526 is formed along the surfaces of the fins 218); and forming a gate electrode over the gate dielectric layer and laterally between the first and second fin structures (Fig. 5 and [0023]; gate electrode material 528 is formed within the trenches between the fins 218).
Regarding claim 19, Ting discloses; forming an isolation structure over the base region of the substrate and on opposing sides of the first and second fin structures (Fig. 3 and [0019]; dielectric material 320 is formed over the substrate 110 on opposing sides of the fins 218), wherein a top surface of the gate electrode is recessed below a top surface of the isolation structure (Fig. 5-6 and [0029]; recessing of the gate electrode material 528 to form the gate electrodes 630 below top surface of the dielectric material 320).
Regarding claim 20, Ting discloses; the first fin structure has a first sidewall opposite a second sidewall, wherein the gate dielectric layer directly contacts the first sidewall and wherein the isolation structure directly contacts the second sidewall (Fig. 3-5 and [0023]; gate insulator layer 526 is formed along the side surfaces of the fins 218 and dielectric material 320 is formed along the other side surface of the fins 218).
Regarding claim 23, Ting discloses; a bottom surface of the gate electrode is below a bottom of the first source/drain region by a distance greater than a height of the first source/drain region (attached Fig. 8 below shows that, the distance between bottom surface of the gate electrode 630 and bottom of the first source/drain region is greater than a height of the first source/drain region).
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Regarding claim 25, Ting discloses; a method for forming an integrated chip, comprising: forming a first pedestal structure and a second pedestal structure over a base region of a substrate (Fig. 2 and [0015]; substrate 110 patterned by performing one or more etching steps, thereby forming fins 218), wherein a lateral surface of the substrate extends between the first and second pedestal structures (Fig. 2 and [0015]; top surface of substrate 110 extends between fins 118); forming a first source/drain region on the first pedestal structure and a second source/drain region on the second pedestal structure (Fig. 8 and [0031]; formation of the source/drain regions 834 on the fins 218); forming a silicide layer on the first and second source/drain regions (Fig. 8 and [0032]; silicide regions 836 formed on the source/drain regions 834 on the fins 218); depositing a gate dielectric layer on the lateral surface of the substrate and on the first and second pedestal structures (Fig. 5 and [0023]; gate insulator layer 526 is formed along the surfaces of the fins 218 and on the substrate 110); and forming a gate electrode over the gate dielectric layer and between the first and second pedestal structures (Fig. 5 and [0023]; gate electrode material 528 is formed within the trenches between the fins 218), wherein a top surface of the gate electrode is recessed below a bottom surface of the silicide layer (Fig. 5-6, 8 and [0029]; recessing of the gate electrode material 528 to form the gate electrodes 630 below bottom surface of the silicide regions 836).
Regarding claim 26, Ting discloses; a width of the first source/drain region is equal to a width of the first pedestal structure (attached Fig. 8 above shows that, width of the first source/drain region 834 is equal to a width of the fins 118).
Regarding claim 31, Ting discloses; a top surface of the gate dielectric layer is aligned with or above a top surface of the first source/drain region (attached Fig. 8 above shows that, top surface of the gate insulator layer 526 is aligned with the top surface of the source/drain regions 834).
Regarding claim 32, Ting discloses; doping the substrate to form a well region in the substrate between the first and second pedestal structures, wherein the well region extends vertically along the first and second pedestal structures ([0025]; substrate 110 doped before forming the gate insulator layer along the sidewalls and bottom of the trenches 2162 and 2164).
Regarding claim 33, Ting discloses; a method for forming an integrated chip, comprising: forming a first fin structure and a second fin structure in a substrate (Fig. 2 and [0015]; substrate 110 patterned by performing one or more etching steps, thereby forming fins 218); forming source/drain regions on the first and second fin structures (Fig. 8 and [0031]; formation of the source/drain regions 834 on the fins 218); forming an isolation structure over the substrate and around the first and second fin structures (Fig. 3 and [0019]; dielectric material 320 is formed over the substrate 110 on opposing sides of the fins 218), wherein the isolation structure comprises a segment between the first fin structure and the second fin structure (Fig. 3 and [0019]; dielectric material 320 is formed between the fins 218); removing the segment of the isolation structure to form an opening between the first and second fin structures (Fig. 4 and [0021]; removal of the first dielectric material 320 from select ones of the trenches 2162 and 2164); forming a gate dielectric layer lining the opening (Fig. 5 and [0023]; gate insulator layer 526 is formed along the surfaces of the trenches 2162 and 2164); forming a gate electrode in the opening and on the gate dielectric layer, wherein the gate dielectric layer is arranged between the gate electrode and the first and second fin structures (Fig. 5 and [0023]; gate electrode material 528 is formed within the trenches 2162 and 2164 between the fins 218); and forming a capping layer over the gate electrode (Fig. 7 and [0030]; second dielectric layer 732 is formed over the substrate 110, filling the recesses above the gate electrodes 630), wherein a bottom surface of the capping layer is below a top of the source/drain regions (Fig. 8; bottom surface of the second dielectric layer 732 is below the top surface of the source/drain regions 834).
Regarding claim 34, Ting discloses; a width of the first fin structure is greater than a thickness of the gate dielectric layer and less than a width of the gate electrode (attached Fig. 8 below shows that, width of the fins 118 is greater than a thickness of the gate insulator layer 526 and less than a width of the gate electrode 630).
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Regarding claim 35, Ting discloses; a bottom surface of the gate electrode is above a bottom surface of the isolation structure, wherein a top surface of the gate electrode is below a top surface of the isolation structure (attached Fig. 8 above shows that, bottom surface of the gate electrode 630 is above the bottom surface of the dielectric material 320 as gate insulator layer 526 is under gate electrode 630 and top surface of the gate electrode 630 is below a top surface of the dielectric material 320).
Regarding claim 36, Ting discloses; a top surface of the capping layer is aligned with a top surface of the gate dielectric layer and the top of the source/drain regions (attached Fig. 8 above shows that, top surface of the second dielectric layer 732 is aligned with a top surface of the gate insulator layer 526 and the top of the source/drain regions 834).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 18, 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Ting, US 2020/0357802 as applied to claims 17, 19-20, 23, 25-26 and 31-36 above, and further in view of LIU, US 2023/0217648.
Regarding claim 18, Ting substantially discloses the method steps of manufacturing transistor with source/drain region formed on the fins after forming gate insulator layer on the sidewall of the fins and bottom of the trench but is silent about the first and second source/drain regions are formed before depositing the gate dielectric layer, wherein the gate dielectric layer extends along tops of the first and second source/drain regions. However, LIU shows the method step of forming gate oxide layer 204 after forming the source and drain in the active region and gate oxide layer 204 extends along tops of the active region (Fig. 5 and [0053, 0068]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Ting by providing the method step of forming the first and second source/drain regions before depositing the gate dielectric layer, wherein the gate dielectric layer extends along tops of the first and second source/drain regions, since the silicon oxide has a desirable insulativity and can contact the surface of the trench at a low surface state density, the silicon oxide as the gate oxide layer can effectively improve the performance of the device ([0070]).
Regarding claims 21 and 22, Ting substantially discloses the method steps of manufacturing transistor with source/drain region formed on the fins after forming gate insulator layer on the sidewall of the fins and bottom of the trench with isolation trenches formed by the first dielectric material but is silent about the gate dielectric layer extends around an outer perimeter of the first source/drain region, wherein the gate dielectric layer is spaced between the isolation structure and the first and second fin structures in claim 21 and the isolation structure is formed after the gate dielectric layer in claim 22. However, LIU shows that gate oxide layer 204 extends around an outer perimeter of the source/drain region at the active region (Fig. 5 and [0053, 0068]) and gate oxide layer 204 is spaced between the isolation material layer 203 and fin structures source/drain region at the active region (Fig. 8-9 and [0058, 0059]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Ting by providing the gate dielectric layer extends around an outer perimeter of the first source/drain region, wherein the gate dielectric layer is spaced between the isolation structure and the first and second fin structures in claim 21 and the isolation structure is formed after the gate dielectric layer in claim 22, since the silicon oxide has a desirable insulativity and can contact the surface of the trench at a low surface state density, the silicon oxide as the gate oxide layer can effectively improve the performance of the device ([0070]).
Claims 28-30 are rejected under 35 U.S.C. 103 as being unpatentable over Ting, US 2020/0357802 as applied to claims 17, 19-20, 23, 25-26 and 31-36 above, and further in view of Dokania, US 12289894.
Regarding claims 28 and 30, Ting discloses in claim 28; forming a conductive contact over the first source/drain region (Fig. 10A and [0034]; bitline contacts 954 over source/drain regions 834); forming a conductive interconnect over the conductive contact (Fig. 10A and [0034]; bitline contacts 954 over the bitline 952); forming a capacitor over the conductive interconnect, wherein the capacitor is coupled to the first source/drain region (Fig. 10A and [0034]; the source/drain regions 834 of the access transistor is electrically coupled to a storage node 956 via storage node contacts 958. The storage node 956 may be, for example, a metal-insulator-metal (MIM) capacitor, a planar capacitor, a U-shaped capacitor, a vertical capacitor, a horizontal capacitor). Ting substantially discloses the method steps of manufacturing transistor with source/drain region formed on the fins and the source/drain regions of the access transistor is electrically coupled to a storage node 956 (capacitor) via storage node contacts 958 but is silent about the method steps of depositing a first dielectric layer over the substrate and depositing a second dielectric layer over the conductive interconnect in claim 28 and forming the capacitor comprises: etching the second dielectric layer to form an opening in the second dielectric layer; depositing a plurality of capacitor layers over the second dielectric layer and lining the opening; and performing a planarization process on the plurality of capacitor layers in claim 30. However, Dokania teaches that transistors 402A and 402B are coupled to capacitors 108 through interconnect 102A formed on the dielectric layer 103 (Fig. 1A, 4B) and formation of a plurality of capacitors by patterning on the dielectric layers 222, 224 and 226 (Fig. 2, 4B, 5). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Ting by providing the method steps of depositing a first dielectric layer over the substrate and depositing a second dielectric layer over the conductive interconnect in claim 28 and forming the capacitor comprises: etching the second dielectric layer to form an opening in the second dielectric layer; depositing a plurality of capacitor layers over the second dielectric layer and lining the opening; and performing a planarization process on the plurality of capacitor layers in claim 30, so that to form structures that can couple two or more capacitors across different levels are desirable to increase charge storage and facilitate operation of memory and logic devices based on stacked capacitors ([0093]).
Regarding claim 29, Ting discloses; the conductive contact extends through and directly contacts the gate dielectric layer (Fig. 10A and [0034]; bitline contacts 954 contacts the gate insulator layer 526).
Claims 24 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Ting, US 2020/0357802 as applied to claims 17, 19-20, 23, 25-26 and 31-36 above, and further in view of official notice.
Regarding claim 24, Ting discloses; the gate electrode, the first fin structure, and the second fin structure extend along a first direction and are arranged in parallel (Fig. 6 and [0029]; gate electrode 630 and the fins 218 are in parallel). Ting substantially discloses the method steps of manufacturing transistor with source/drain region formed on the fins with gate electrode layer formed in the trenches but is silent about, a length of the gate electrode is greater than lengths of the first and second fin structures in claim 24 and a distance between a bottom of the first source/drain region and the lateral surface of the substrate is greater than a distance between the first and second pedestal structures in claim 27. Ting also discloses that embodiments disclosed herein also allow layout designers greater freedom. For example, the gate length is defined by the depth of the trench as opposed to the pitch between fins, thereby possibly allowing the gate length to be adjusted without increasing the pitch [0036]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Ting by providing a length of the gate electrode is greater than lengths of the first and second fin structures in claim 24 and a distance between a bottom of the first source/drain region and the lateral surface of the substrate is greater than a distance between the first and second pedestal structures in claim 27, since applicant has not disclosed the specific measurement of length and distance in the claim language, therefore it has been held that where general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation- MPEP 2144.05.II.A.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AZM PARVEZ whose telephone number is (571)272-1447. The examiner can normally be reached M-F 9-6 EST.
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/AZM PARVEZ/
Examiner
Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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