DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-6 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/6/2026.
Applicant’s election without traverse of Group II, claims 7-20 in the reply filed on 7/6/2026 is acknowledged.
Status of Claims
Claims 1-6 are cancelled, claims 7-20 are elected and new claims 21-26 have been added.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 7, 8 and 11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Liao, US 2023/0411442.
Regarding claim 7, Liao discloses; a method, comprising: forming a masking layer (Fig. 4 and [0029]; mask layer 112); forming, in openings of the masking layer, a conductive structure having a portion that extends above a top surface of the masking layer (Fig. 5-6 and [0031] ; conductive material 118 is formed on the seed layer 116 and in the openings 114); removing the portion that extends above the top surface to form an approximately planar, horizontal surface on the conductive structure (Fig. 7 and [0032] ; planarization step, to remove excess portions of the conductive material 118 which are over the mask layer 112); removing the masking layer (Fig. 8 and [0033]; mask layer 112 is removed); forming a dielectric layer over the conductive structure (Fig.14 and [0050]; dielectric layer 136 is formed); and forming an interconnect structure that penetrates through the dielectric layer and connects with the approximately planar, horizontal surface of the conductive structure (Fig. 14 and [0050] ; RDL 134 penetrates through dielectric layer 136 to connect with vias 120).
Regarding claim 8, Liao discloses; forming the masking layer includes: depositing a photoresist layer on a conductive layer (Fig. 4 and [0029]; mask layer 112 a dry-film photoresist over the lower RDL 110); and forming the openings using a photolithography operation (Fig. 4 and [0029]; mask layer 112 patterned using acceptable development and exposure techniques to form openings 114).
Regarding claim 11, Liao discloses; removing the portion that extends above the top surface to form the approximately planar, horizontal surface includes: using a chemical/mechanical planarization operation to remove the portion (Fig. 7 and [0032]; planarization step, such as a chemical mechanical polish (CMP)).
Claim(s) 21-26 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen, US 2023/0245991.
Regarding claim 21, Chen discloses; a method, comprising: forming a conductive structure of a redistribution layer (Fig.1-10 and [0028,0050]; through vias 116 for under-bump metallurgy layers114 and redistribution structure 170), the conductive structure comprising: a vertically-oriented sidewall (Fig.11 and [0059]; side wall 116S of through vias 116), a rounded footer protruding laterally from the vertically-oriented sidewall at a base of the conductive structure (Fig.11 and [0060]; side wall 116S protruding at the base of through vias 116 with width W2), and an approximately planar, horizontal surface that forms a sharp corner with the vertically-oriented sidewall at a top of the conductive structure that is opposite the base (Fig.11 and [0060]; side wall 116S protruding at the top surface of through vias 116 with width W2 forms a sharp corner); and forming an interconnect structure that connects to the conductive structure along the approximately planar, horizontal surface (Fig.1-10 and [0050]; redistribution structure 170 connects with through vias 116).
Regarding claim 22, Chen discloses; the rounded footer includes a curvature configured to reduce a stress concentration at the base of the conductive structure (Fig. 11 and [0059]; forming the through via 116 with curved sidewalls 116S can reduce the amount of stress that concentrates on the junction between the through via 116 and the UBML 114).
Regarding claim 23, Chen discloses; the sharp corner has an angle that is included in a range of approximately 10 degrees to approximately 170 degrees (Fig. 11 and [0062]; The angles θ1, θ2, θ3, θ4 are each in the range of 90 degrees to 120 degrees, whereas 180-90= 90 and 180-120=60, therefore sharp angles has range of 60 degrees to 90 degrees).
Regarding claim 24, Chen discloses; a width of the base including the rounded footer is greater than a width of the approximately planar, horizontal surface (Fig. 17; width of the base 126 is greater than the top surface).
Regarding claim 25, Chen discloses; the vertically-oriented sidewall includes a concave -shaped surface that extends inward toward a center of the conductive structure (Fig. 11 and [0059]; sidewall 116S is concave shape surface extends inward with W1 is smaller than W2).
Regarding claim 26, Chen discloses; forming a dielectric layer that surrounds the conductive structure, conforms to the concave-shaped surface, and conforms to the rounded footer (Fig. 8-11; encapsulant 154 surrounds the via 116).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Liao, US 2023/0411442 as applied to claims 7,8 and 11above, and further in view of Lee, US 2025/0118595.
Regarding claim 9, Liao substantially discloses the method steps including mask layer patterned using acceptable development and exposure techniques to form openings but is silent about depositing a hard mask layer on a conductive layer; and forming the openings using an etch operation. However, Lee teaches that the patterning of the hard mask 224 and the third ESL 222 may include photolithography processes and etching processes to form openings (Fig. 2-7 and [0033]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Liao by depositing a hard mask layer on a conductive layer; and forming the openings using an etch operation so that a durable, non-organic hard mask layer is deposited on a semiconductor wafer to form fine circuit patterns when regular photoresist is too fragile to withstand the etching process.
Claims 10 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Liao, US 2023/0411442 as applied to claims 7, 8 and 11above, and further in view of Chen, US 2023/0245991.
Regarding claims 10 and 13, Liao substantially discloses the method steps including forming plurality of conductive vias is formed in the openings of mask layer, and also planarization step, to remove excess portions of the conductive material which are over the mask layer but is silent about forming a rounded footer that protrudes laterally from a vertically-oriented sidewall of the conductive structure at a base of the conductive structure in claim 10 and removing the portion to form a sharp corner with a vertically-oriented sidewall of the conductive structure in claim 13. However Chen teaches forming a rounded footer that protrudes laterally from a vertically-oriented sidewall of the conductive structure at a base of the conductive structure (Fig.11 and [0060]; side wall 116S protruding at the base of through vias 116 with width W2) and removing the portion to form a sharp corner with a vertically-oriented sidewall of the conductive structure (Fig.11 and [0062]; side wall 116S protruding at the top surface of through vias 116 with width W2 forms a sharp corner). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Liao by forming a rounded footer that protrudes laterally from a vertically-oriented sidewall of the conductive structure at a base of the conductive structure in claim 10 and removing the portion to form a sharp corner with a vertically-oriented sidewall of the conductive structure in claim 13, so that forming the through vias with curved sidewalls can reduce the amount of stress that concentrates on the respective interfaces between the through vias and the encapsulant, reducing the risk of the encapsulant delaminating from the through vias [0014].
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Liao, US 2023/0411442 as applied to claims 7,8 and 11above, and further in view of CHANG, US 2023/0069315.
Regarding claim 12, Liao discloses; Liao substantially discloses the method steps including forming plurality of conductive vias is formed in the openings of mask layer, and planarization step, to remove excess portions of the conductive material which are over the mask layer but is silent about removing the portion to form the approximately planar, horizontal surface includes: removing a portion of the masking layer. However, CHANG teaches the method step of planarize hard mask layer 520, conductive layers 502, 504 and the dielectric layers 506, 508 that are disposed above the upper surface of the hard mask layer 520 (Fig. 2, 3G and [0085]; Step 614). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Liao by removing the portion to form the approximately planar, horizontal surface includes: removing a portion of the masking layer, so that so that the planarizing is terminated in response to a consistently measurable endpoint reflecting sufficient removal of an overlying material layer, typically followed by a brief overetch or over-polish to compensate for variations in the thickness of the material layer.
Claims 14 is rejected under 35 U.S.C. 103 as being unpatentable over Liao, US 2023/0411442, in view of CHEN, JP 2024-018952.
Regarding claim 14, Liao discloses; a method, comprising: forming, in openings of a masking layer (Fig. 4 and [0029]; mask layer 112) over a semiconductor die (Fig. 1, 10D-15 and [0014]; circuit die 50), conductive structures of a redistribution layer (Fig. 5-6 and [0031] ; conductive material 118 is formed on the seed layer 116 and in the openings 114 with excess portions over the mask layer 112); removing a portion of at least one of the conductive structures (Fig. 7 and [0032]; planarization step, to remove excess portions of the conductive material 118 which are over the mask layer 112); removing the masking layer (Fig. 8 and [0033]; mask layer 112 is removed); forming a dielectric layer over the conductive structures (Fig.14 and [0050]; dielectric layer 136 is formed); and forming interconnect structures that penetrate through the dielectric layer and connect with the conductive structures (Fig. 14 and [0050] ; RDL 134 penetrates through dielectric layer 136 to connect with vias 120). Liao substantially discloses the method steps including forming plurality of conductive vias is formed in the openings of mask layer, and planarization step, to remove excess portions of the conductive material which are over the mask layer but is silent about conductive structures having different heights across the semiconductor die and to reduce a variation in the different heights across the semiconductor die. However, CHEN shows that conductive structures having different heights across the semiconductor die (Fig. 32; top surface of electrode layer 1101 over the sacrificial layer 3002 having different heights across the interconnect structure of 302) and to reduce a variation in the different heights across the semiconductor die (Fig. 33; top surface of the bottom electrode layer 1101 is recessed until it is at the same level or almost the same level as the top surface of the sacrificial layer 3002). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Liao by providing conductive structures having different heights across the semiconductor die and to reduce a variation in the different heights across the semiconductor die, so that this divides the bottom electrode layer into individual bottom electrodes for the memory cells being formed (Page 17; ¶ 3).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Liao, US 2023/0411442, in view of CHEN, JP 2024-018952 as applied to claim 14 above, and further in view of EL-GHOROURY, US 2024/0021746.
Regarding claim 15, Liao view of CHEN substantially discloses the method steps including forming plurality of conductive vias is formed in the openings of mask layer, and also planarization step, to remove excess portions of the conductive material which are over the mask layer but is silent about removing the portion of the at least one of the conductive structures to reduce the variation in the different heights improves a planarity of the conductive structures to be less than approximately 100 nanometers within the semiconductor die. However, EL-GHOROURY teaches that the top side of the deposited contact layer 130 is polished to a high planarity specification of less than 0.5 nanometers using high planarity semiconductors chemical mechanical polishing (CMP) techniques [0026]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Liao view of CHEN by removing the portion of the at least one of the conductive structures to reduce the variation in the different heights improves a planarity of the conductive structures to be less than approximately 100 nanometers within the semiconductor die, to provide high planarity polishing of the deposited contact layer.
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Liao, US 2023/0411442, in view of CHEN, JP 2024-018952 as applied to claim 14 above, and further in view of Chen, US 2023/0245991.
Regarding claims 16 and 17, Liao in view of CHEN’ JP952 substantially discloses the method steps including forming plurality of conductive vias is formed in the openings of mask layer, and also planarization step, to remove excess portions of the conductive material which are over the mask layer but is silent about an intersection of the approximately planar, horizontal surface and the vertically- oriented sidewall forms a sharp corner having an acute angle in claim 16 and an intersection of the approximately planar, horizontal surface and the vertically- oriented sidewall is a sharp corner having an acute angle in claim 17. However, Chen’ US991 teaches that side wall 116S protruding at the top surface of through vias 116 with width W2 forms a sharp corner (Fig.11 and [0062]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Liao in view of CHEN’ JP952 by providing an intersection of the approximately planar, horizontal surface and the vertically- oriented sidewall forms a sharp corner having an acute angle in claim 16 and an intersection of the approximately planar, horizontal surface and the vertically- oriented sidewall is a sharp corner having an acute angle in claim 17, so that forming the through vias with curved sidewalls can reduce the amount of stress that concentrates on the respective interfaces between the through vias and the encapsulant, reducing the risk of the encapsulant delaminating from the through vias [0014].
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Liao, US 2023/0411442, in view of CHEN, JP 2024-018952 as applied to claim 14 above, and further in view of Sahota, US 6927113.
Regarding claim 18, Liao in view of CHEN substantially discloses the method steps including forming plurality of conductive vias is formed in the openings of mask layer, and also planarization step, to remove excess portions of the conductive material which are over the mask layer but is silent about removing the portion using a chemical/mechanical planarization operation that uses a copper slurry dispensed on a polishing pad. However, Sahota teaches that the electrically conductive material is recessed using an over-polishing process with highly selective copper slurry (abstract). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Liao in view of CHEN by removing the portion using a chemical/mechanical planarization operation that uses a copper slurry dispensed on a polishing pad , so that a high selectivity copper chemical mechanical planarization (CMP) process will keep a substantial amount of barrier layer on hardmask ( Col 6; Ln 67- Col. 7; Ln 1-2).
Regarding claim 19, Liao discloses; removing the portion using the chemical/mechanical planarization operation includes: stopping the chemical/mechanical planarization operation on or within the masking layer (Fig. 7 and [0032]; after the planarization step, top surfaces of the conductive material 118, the seed layer 116, and the mask layer 112 are level).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Liao, US 2023/0411442, in view of CHEN, JP 2024-018952 as applied to claim 14 above, and further in view of Cohen, US 6657305.
Regarding claim 20, Liao in view of CHEN substantially discloses the method steps including forming plurality of conductive vias is formed in the openings of mask layer, and also planarization step, to remove excess portions of the conductive material which are over the mask layer but is silent about stopping the chemical/mechanical planarization operation above the masking layer. However, Cohen teaches that masking layer 16 is below the top surface of conductive members 2 and 3 (Fig. 3, 4). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to modify Liao in view of CHEN by stopping the chemical/mechanical planarization operation above the masking layer, so that to avoid, such as high electric field concentration points; and the benefit of having a final mask thickness that is selectable and no thicker than necessary (Col. 4; Ln. 6-8).
Conclusion
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/AZM PARVEZ/
Examiner, Art Unit 2892
/NORMAN D RICHARDS/Supervisory Patent Examiner, Art Unit 2892
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