Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/619,755 filed on March 28, 2024.
Information Disclosure Statement
3. Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Specification
4. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Method of Microfabrication Comprising Metallization and Planarization Related to Defect Detection”.
Claim Objections
5. Claims 2, 17 are objected to because of the following informalities: In the following, the claims should be recited to avoid indefiniteness due to lack of antecedent basis, and/or smooth flow of claim languages/phrases:
2. (Currently Amended) The method of claim 1, wherein:
the polishing comprises executing a chemical-mechanical polishing (CMP) process on the insulating layer.
17. (Currently Amended) A method of defect detection, the method comprising:
providing a wafer comprising a conductive layer and an insulating layer formed over the conductive layer;
forming an opening in the insulating layer by an etch process;
depositing a metal material in the opening by a deposition process;
etching the metal material to form a recess in the insulating layer so that a top surface of the metal material is below a top surface of the insulating layer;
polishing the wafer so that the top surface of the metal material and the top surface of the insulating layer are co-planar; and
characterizing the wafer by electron beam inspection (EBI) in a voltage contrast (VC) mode to determine whether a defect of the etch process exists, wherein
the defect exists when a VC signal of the opening is below a threshold, and
the defect does not exist when the VC signal of the opening is at or above the threshold.
Appropriate corrections are needed.
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
9. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or non-obviousness.
10. Claims 1-3, 10-12, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Tsutsue (US 2008/0318411 A1) in view of Aklik et al. (US 2012/0007245 A1).
Regarding independent claim 1, Tsutsue teaches a method of microfabrication, the method comprising (Figs. 1, 3A-3E):
providing a wafer (substrate which is a part of the wafer, para [0070] not shown in the figure) comprising a conductive layer (104 metal wire, para [0070]) and an insulating layer (106, para [0076]) formed over the conductive layer (104);
forming an opening (111 groove/110 hole, para [0075], [0076]) through the insulating layer (106) to expose (see Fig. 3C) the conductive layer (104);
depositing a metal material (114: 112/113, para [0079]) to fill the opening (111/110);
polishing the wafer so that the top surface of the metal material (114) and the top surface of the insulating layer (106) are co-planar (see Fig. 3E).
Tsutsue is explicitly silent of disclosing wherein, etching the metal material to form a recess in the insulating layer so that a top surface of the metal material is below a top surface of the insulating layer.
Aklik et al. teaches wherein (Figs. 1A-1D), etching (removing/CMP, see Fig. 1D, para [0010]) the metal material (126) to form a recess (134 cavity, para [0011]) in the insulating layer (114) so that a top surface of the metal material (126) is below a top surface of the insulating layer (114).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Aklik et al., while polishing the top surface of the metal material of Tsutsue, using the conventional chemical-mechanical polishing and evolving cavity that is under the non-conductive structure which is called coring, as shown as processing step that does not present significant issue rather provides an improvement step in the manufacturing process.
Regarding claim 2, Tsutsue and Aklik et al. teach all of the limitations of claim 1 from which this claim depends.
Tsutsue teaches wherein (Fig. 3E: the polishing (removing, para [0079]) comprises executing a chemical-mechanical polishing (CMP, para [0079]) process on the insulating layer (106).
Regarding claim 3, Tsutsue and Aklik et al. teach all of the limitations of claim 2 from which this claim depends.
Tsutsue teaches wherein (Fig. 3E: the CMP process (para [0079]) is configured to stop at the top surface of the metal material (114).
Regarding claim 10, Tsutsue and Aklik et al. teach all of the limitations of claim 2 from which this claim depends.
Tsutsue teaches wherein (see Fig. 3A): the wafer further comprises an etch stop layer (ESL) (105 insulating film, para [0076]) formed between the conductive layer (104) and the insulating layer (106).
Regarding claim 11, Tsutsue and Aklik et al. teach all of the limitations of claim 10 from which this claim depends.
Tsutsue teaches wherein (see Fig. 3A): further comprising:
executing a first etch process of the insulating layer (106) that stops at the ESL (105) to form the opening (110/111) through the insulating layer (106).
Regarding claim 12, Tsutsue and Aklik et al. teach all of the limitations of claim 11 from which this claim depends.
Tsutsue teaches wherein (see Fig. 3C): further comprising:
executing a second etch process (para [0076]) of the ESL (105) via the opening (110/111) to expose the conductive layer (104).
Regarding claim 16, Tsutsue and Aklik et al. teach all of the limitations of claim 1 from which this claim depends.
Tsutsue teaches wherein (see Fig. 3A): the insulating layer (106) comprises silicon oxide (SiOC, para [0073]), silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbon oxynitride or a combination thereof.
11. Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Tsutsue (US 2008/0318411 A1) in view of Aklik et al. (US 2012/0007245 A1) as applied to claim 1, and further in view of O,brien et al. (US 2010/0140804 A1).
Regarding claim 13, Tsutsue and Aklik et al. teach all of the limitations of claim 1 from which this claim depends.
Tsutsue and Aklik et al. are explicitly silent of disclosing wherein, the metal material comprises ruthenium.
O,brien et al. teaches wherein (Fig. 4), the metal material comprises ruthenium (310, para [0028]) in the opening (150).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Aklik et al., and substituting the metal material with ruthenium in the opening of Tsutsue, in order to enhance the interconnect contact or via or line with electromigration resistance, and reduces resistance to electrical flow between the refractor interconnect 310 and an underlying metal 170 (para [0023]).
Regarding claim 14, Tsutsue and Aklik et al. teach all of the limitations of claim 1 from which this claim depends.
Tsutsue teaches wherein (see Fig. 3A): the metal material is copper (para [0078]).
Tsutsue and Aklik et al. are explicitly silent of disclosing wherein, the metal material does not comprise copper.
However, O,brien et al. teaches wherein (Fig. 4), the metal material comprises ruthenium (310, para [0028]) in the opening (150).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Aklik et al., and substituting copper with ruthenium in the opening of Tsutsue, in order to enhance the interconnect contact or via or line with electromigration resistance, and reduces resistance to electrical flow between the refractor interconnect 310 and an underlying metal 170 (para [0023]).
Regarding claim 15, Tsutsue and Aklik et al. teach all of the limitations of claim 1 from which this claim depends.
Tsutsue teaches wherein (para [0070]), the conductive layer (110, para [0070]) is copper wire and the metal material (114: 113) is made of copper also.
Tsutsue and Aklik et al. are explicitly silent of disclosing wherein, the conductive layer and the metal material comprise different metals.
However, O,brien et al. teaches wherein (Fig. 4), the metal material comprises ruthenium (310, para [0028]) in the opening (150).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Aklik et al., and substituting copper with ruthenium in the opening of Tsutsue, in order to enhance the interconnect contact or via or line with electromigration resistance, and reduces resistance to electrical flow between the refractor interconnect 310 and an underlying metal 170 (para [0023]).
Therefore, the combination of Tsutsue and O,brien et al. discloses the conductive layer (copper) and the metal material (ruthenium) comprise different metals.
Allowable Subject Matter
12. Claims 17-20 are allowed.
13. The following is an examiner’s statement of reasons for allowance:
Claim 17: the prior art of record alone or in combination neither teaches nor makes obvious a method of defect detection, the method comprising:
….
characterizing the wafer by electron beam inspection (EBI) in a voltage contrast (VC) mode to determine whether a defect of the etch process exists, wherein the defect exists when a VC signal of the opening is below a threshold, and the defect does not exist when the VC signal of the opening is at or above the threshold;
14. Claim 4 (claims 5-9 depends on the claim 4) is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
claim 4 recites….further comprising:
depositing a dielectric material to fill the recess and cover the insulating layer.
15. Recorded prior arts in PTO-892 and not relied upon are considered pertinent to applicant’s disclosure: the prior arts, Tsutsue (US 2008/0318411 A1) and Aklik et al. (US 2012/0007245 A1) and/or O,brien et al. (US 2010/0140804 A1) describes the manufacturing steps for forming the microfabrication structure, however, by itself or in combination or with other prior arts does not disclose the quoted limitation as stated in the sections 12 and 13.
Examiner’s Note
16. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
17. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
18. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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