DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant's election with traverse of Group 1 claims 1-19 in the reply filed on 06/25/2026 is acknowledged. The traversal is on the ground(s) that there is no search burden. This is not found persuasive because:
Group I would require a search in at least CPC H10W20/023, along with a unique text search.
Group II would not be searched as above and would instead require a search in CPC
H10W90/732.
The requirement is still deemed proper and is therefore made FINAL.
Claims 1-19 are pending in this application.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4, and 7-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US20220359405A1-Chen05).
Regarding claim 1, Chen05 discloses a method, comprising:
providing a first substrate and a second substrate (providing first substrate 122/126 and second substrate 104/108 -Fig 2, Fig 3),
wherein the first substrate includes
a first base material (first base material 122-Fig 2) and
a first dielectric layer on the first base material (first dielectric layer 126 on first base material 122-Fig 2, [0028] L1-7), and
the second substrate includes
a second base material (second base 104-Fig 3) and
a second dielectric layer on the second base material (second dielectric layer 108on second base layer 104-Fig 3),
wherein the second base material has a first through hole (second base material 104 having first through hole 112-Examiner's annotated Fig 3), and
the first dielectric layer and the second dielectric layer have a first hole and a second hole (second dielectric material 108 having second hole 110 and first dielectric material 126 having first hole 110-Examiner's annotated Fig 3, [0029] L1-11), respectively;
connecting the second substrate to the first substrate in such a way that the second dielectric layer is connected to the first dielectric layer to form a first composite structure (connecting first substrate 122/126 to second substrate 104/108 in such a way that first dielectric layer 126 is connected to the second dielectric layer 108 to form a first composite structure 122/126/108/104-Examiner's annotated Fig 3, [0035] L1-14);
thinning a top surface of the first composite structure to expose the first through hole (Thinning top surface of first composite structure 122/126/108/104 to expose first through holes 114-[0041] L1-2, Fig 3, Fig 4) ; and
forming a first conductive member in the first through hole (Forming first conductive member in first through hole 112-[0033]L1-5).
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Regarding claim 4, Chen05 discloses all the elements of claim 1, as noted above.
Chen05 further discloses a method
wherein providing the second substrate comprises:
forming the second dielectric layer on the second base material (forming second dielectric layer 108 on second base layer 104-Fig 3, [0027] L1-2, [0028] L1-4),
wherein the second hole of the second dielectric layer is aligned with the first through hole of the second base material ( First through hole 112 of second base material 104 being aligned with second hole 110 of second dielectric layer 108-Examiner's annotated Fig 3).
Regarding claim 7, Chen05 discloses all the elements of claim 1, as noted above.
Chen05 further discloses a method
wherein connecting the second substrate to the first substrate comprises:
the second hole of the second dielectric layer being aligned with the first hole of the first dielectric layer (second hole 110 of the second dielectric layer 108 being aligned with first hole 110 of the first dielectric layer 126-Examiner's annotated Fig 3).
Regarding claim 8, Chen05 discloses all the elements of claim 7, as noted above.
Chen05 further discloses a method
wherein forming the first conductive member further comprises:
forming the first conductive member in the first hole and the second hole (forming first conductive member 110 in first/bottom hole 110 and second/top hole 110-[0030] L1-2).
Regarding claim 9, Chen05 discloses all the elements of claim 1, as noted above.
Chen05 further discloses a method
wherein neither wiring nor bumps are formed after forming the first conductive member (Semiconductor 102C placed on top of through hole 112 of semiconductor 102A without adding any wiring or bump-Fig 29C).
Regarding claim 10, Chen05 discloses all the elements of claim 1, as noted above.
Chen05 further discloses a method
providing a third substrate (providing third substrate 104/108 for 102C/D-Fig 29C, [0101] L1-17, [0103] L1-6), which comprises
a third base material (104 for 102 C/D-Fig 29C) and
a third dielectric layer on the third base material (third dielectric layer 108 on third base material for 102C/D-Fig 29C),
wherein the third base material has a second through hole (second through hole 112 for 102 C/D in third base material 104 for 102C/D-Fig 29C),
wherein the third dielectric layer has a third hole (third dielectric layer 108 on third base material for 102C/D having third hole 110-Fig 29C);
connecting the third substrate to the first composite structure to form a second composite structure (bonding so connecting third substrate 104/108 of 102C/D to the first composite structure 104/108 of 102 A/B +122/126/120 to form second composite structure 120/ (102A/B) / (102C/D)-Fig 29D, [0103] L1-15);
thinning a top surface of the second composite structure to expose the second through hole (Recessing so thinning top surface of second composite structure 120/ (102A/B) / (102C/D)-Fig 29D, [0104] L1-2; and
forming a second conductive member in the second through hole (Forming second conductive in second through hole 112 of 102 C/D-Fig 29C/D-[0101] L1-5, [0033]L1-5).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 12, and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US20220359405A1-Chen05) in view of Asami et al. (US 20060124345 A1-Asami45).
Regarding claim 2, Chen05 discloses all the elements of claim 1, as noted above.
Chen05 does not disclose a method
wherein forming the first conductive member comprises: using a printing process.
Asami45 teaches a method
wherein forming the first conductive member comprises: using a printing process ([0075] L2-6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Chen05, as taught by Asami45 for the purpose of lowering resistance (Asami45: [0043]).
Regarding claim 12, Chen05 discloses all the elements of claim 10, as noted above.
Chen05 does not disclose a method
wherein connecting the third substrate to the first composite structure comprises:
the third dielectric layer of the third substrate being connected to a top surface of the second through hole exposed by the first composite structure.
Asami45 teaches a method
wherein connecting the third substrate to the first composite structure comprises:
the third dielectric layer of the third substrate being connected to a top surface of the second through hole exposed by the first composite structure Third dielectric layer 72 of third substrate 50/72 being connected to top surface of second through hole 53 exposed by first through hole 53 so by the second base layer 50 of first composite (Middle 50/70)/(Bottom 50/70 ) structure -Examiner's annotated Fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Chen05, as taught by Asami45 for the purpose of lowering resistance (Asami45: [0043]).
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Regarding claim 18, Chen05 discloses all the elements of claim 10, as noted above.
Chen05 does not disclose a method
wherein the first base material, the second base material and the third base material are all dies.
Asami45 teaches a method
wherein the first base material, the second base material and the third base material are all dies (First, second, and third base material comprising a semiconductor chip 56 so being dies-Examiner's annotated Fig 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Chen05, as taught by Asami45 for the purpose of lowering resistance (Asami45: [0043]).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US20220359405A1-Chen05) in view of Asami et al. (US 20060124345 A1-Asami45), and further in view of Ma et al. (US 20130249109 A1-Ma09).
Regarding claim 3, Chen05 and Asani45 combination discloses all the elements of claim 2, as noted above.
Asami45 further teach a method
wherein using the printing process comprises:
filling a conductive ink into the first through hole (filling conductive ink 59 into first through hole 53-[0075] L2-6, Fig 10D)
Chen05 and Asami45 combination does not teach a method
wherein using the printing process comprises:
curing the conductive ink in the first through hole.
Ma09 teaches a method
wherein using the printing process comprises:
curing the conductive ink in the first through hole (Operation 807-[0038] L14-18, Fig 8A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Chen05 in view of Asami45, as taught by Ma09 for the purpose of lowering cost of material for the interposer and cost to form the through vias (Ma09: [0018]).
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US20220359405A1-Chen05) in view of Haba et al. (US 20180190580 A1-Haba80).
Regarding claim 5, Chen05 discloses all the elements of claim 1, as noted above.
Chen05 does not disclose a method
wherein the first hole exposes the first base material, and
the second hole exposes the second base material.
Haba80 teaches a method
wherein the first hole exposes the first base material (first hole exposing first base material 270b-Examiner's annotated Fig 10E), and
the second hole exposes the second base material (second hole exposing second base material 270a-Examiner's annotated Fig 10E).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Chen05 , as taught by Haba80 for the purpose of providing through conductive vias through the thickness of passive component (Haba80:[0143]).
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Regarding claim 6, Chen05 discloses all the elements of claim 1, as noted above.
Chen05 does not disclose a method
wherein the first conductive member directly contacts the second substrate.
Haba80 teaches a method
wherein the first conductive member directly contacts the second substrate (Through hole 235 comprising a conductor/first conductive member directly contacting second base 270a so second substrate -Examiner's annotated Fig 10E, [0108] L 1-5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Chen05 , as taught by Haba80 for the purpose of providing through conductive vias through the thickness of passive component (Haba80:[0143]).
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US20220359405A1-Chen05) in view of Chu et al. (US 20210183764 A1-Chu64).
Regarding claim 19, Chen05 discloses all the elements of claim 1, as noted above.
Chen05 does not disclose a method
wherein connecting the second substrate to the first substrate comprises:
coating an adhesive layer onto the first dielectric layer; and
adhering the second dielectric layer of the second substrate to the first dielectric layer of the first substrate using the adhesive layer.
Chu64 teaches a method
wherein connecting the second substrate to the first substrate comprises:
coating an adhesive layer onto the first dielectric layer (adhesive layer 105' placed so coated onto first dielectric layer 85-Fig 2E, [0028] L 1-11) ; and
adhering the second dielectric layer of the second substrate to the first dielectric layer of the first substrate using the adhesive layer (adhesive layer 105' placed so coated onto first dielectric layer 85 and pressing so adhering second dielectric layer 100 to first dielectric layer 85 using adhesive layer 105'-Fig 2E, [0028] L 1-11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Chen05 , as taught by Chu64for the purpose of simplifying the forming process of the redistribution structure (Chu64: [0003]).
Allowable Subject Matter
Claims 11 and 13-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11, the prior art of record does not teach or suggest a method, namely “wherein the first conductive member and the second conductive member are formed integrally”. The term “integrally” has been interpreted as being formed as one continue part” as shown in Fig 9 of the application.
References such as Chen et al. (US20220359405A1-Chen05) and Asami et al. (US 20060124345 A1-Asami45) combination, teaches a method, but does not teach or suggest a method, namely “wherein the first conductive member and the second conductive member are formed integrally”, in combination with other claimed elements.
Regarding claim 13, the prior art of record does not teach or suggest a method, namely “wherein after thinning the top surface of the second composite structure, the first conductive member and the second conductive member are formed at the same time”. The term “integrally” has been interpreted as being formed as one continue part” as shown in Fig 9 of the application.
References such as Chen et al. (US20220359405A1-Chen05) and Asami et al. (US 20060124345 A1-Asami45) combination, teaches a method, but does not teach or suggest a method, namely “wherein after thinning the top surface of the second composite structure, the first conductive member and the second conductive member are formed at the same time”, in combination with other claimed elements.
The balance of the claims are allowable for at least the above-stated reasons.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHALIE R FAYETTE whose telephone number is (571)272-1220. The examiner can normally be reached Monday-Friday 8:30 am-6pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at (571) 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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NATHALIE R. FAYETTE
Examiner
Art Unit 2812
/NATHALIE R FAYETTE/Examiner, Art Unit 2812 09/02/2026
/CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
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