CTNF 18/620,250 CTNF 101989 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. 12-151 AIA 26-51 12-51 Status of Claims Applicants’ election of invention I drawn to claims 1-15 and appended claims 21-25 are acknowledge. Claims 16-20, drawn to an unelected invention, are cancelled. Claims 23-24 are drawn to an unelected species and are thus withdrawn from further examination. Claims 1-15, 21-22, and 25 are examined herein. Election/Restrictions 08-06 AIA Claim s 16-20, and 23-24 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention , there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04/24/2026 . 08-25-01 AIA Applicant’s election without traverse of 1-15, 21-22, and 25 in the reply filed on 04/24/2026 is acknowledged. 08-23-02 AIA Applicant is reminded that upon the cancelation of claims to a non-elected invention, the inventorship must be corrected in compliance with 37 CFR 1.48(a) if one or more of the currently named inventors is no longer an inventor of at least one claim remaining in the application. A request to correct inventorship under 37 CFR 1.48(a) must be accompanied by an application data sheet in accordance with 37 CFR 1.76 that identifies each inventor by his or her legal name and by the processing fee required under 37 CFR 1.17(i). Information Disclosure Statement The information disclosure statements (IDS) submitted on 03/28/2024 and 08/20/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim (s) 1-4, 6-8, 10-11, 13, 21, and 25 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Huang (US Patent Application Publication US 2022/0139935 A1) . Regarding claim 1, Huang (US Patent No 11,706,928) teaches a semiconductor device (integrated circuit device 100A, Figure 1A, col 4, line 40), comprising: an electrode (gate electrode 105A, Figure 1A) in a first dielectric layer (substrate 103A, Figure 1A, col 4 lines 51-52 + col 6 lines 20-23, teaches the gate electrode may be buried in a substrate...The substrate may be or include a dielectric material. For example, the substrate may be a dielectric substrate or may include a dielectric layer on a semiconductor substrate); a ferroelectric layer over the electrode and the first dielectric layer (ferroelectric layer 107A, Figure 1A, col 4, lines 49-50, teaches the gate electrode is underneath the ferroelectric layer); a high-k dielectric layer over the ferroelectric layer (dielectric layer 109A, Figure 1A, col 4, lines 48-49, teaches the ferroelectric layer and the channel layer are separated by a dielectric layer); an oxide semiconductor layer over the high-k dielectric layer (channel layer 111A, Figure 1A, col 4 lines 48-49 + col 5 lines 27-28, teaches the ferroelectric layer and the channel layer are separated by a dielectric layer...the channel layer is or includes an oxide semiconductor); a second dielectric layer (interlevel dielectric 115A, Figure 1A, col 8, lines 25-26, teaches forming the interlevel dielectric over the channel layer) over the oxide semiconductor layer and the high-k dielectric layer; and a first contact feature and a second contact feature (source coupling 117A & drain coupling 113A, Figure 1A, col 4, lines 52-54, teaches the source coupling and the drain coupling may be vias in an interlevel dielectric) extending through the second dielectric layer to contact the oxide semiconductor layer, as claimed. PNG media_image1.png 505 495 media_image1.png Greyscale Regarding claim 2, Huang (US Patent Application Publication US 2022/0139935 A1) further teaches the semiconductor device of claim 1, wherein the electrode comprises: a barrier layer in contact with the first dielectric layer (col 5, lines 52-55, teaches one or more of the source coupling, the drain coupling, and the gate electrode may further include a diffusion barrier layer, a glue layer, or other such layer); and a metal fill layer over the barrier layer and spaced apart from the first dielectric layer by the barrier layer (col 5, lines 43-49, teaches the source coupling, the drain coupling, and the gate electrode, may be formed of any suitable conductive materials. Suitable conductive materials may include doped polysilicon, graphene, metals, and the like. In some embodiments, the source coupling, the drain coupling, and the gate electrode are formed with metals), as claimed. Regarding claim 3, Huang (US Patent Application Publication US 2022/0139935 A1) further teaches the semiconductor device of claim 1 wherein the barrier layer comprises titanium nitride (col 5, lines 55-59, teaches materials that may be used for a diffusion barrier layer or a glue layer are titanium nitride (TiN), tantalum nitride (TaN), molybdenum nitride (MoN), zirconium nitride (ZrN), hafnium nitride (HfN), and the like), wherein the metal fill layer comprises tungsten (col 5, lines 49-52, teaches examples of metals that may be used are tungsten (W), copper (Cu), ruthenium (Ru), molybdenum (Mo), cobalt (Co), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), and the like, and alloys thereof), as claimed. Regarding claim 4, Huang (US Patent Application Publication US 2022/0139935 A1) further teaches the semiconductor device of claim 1, wherein the ferroelectric layer comprises hafnium zirconium oxide (HfZrO), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium cerium oxide (HfCeO), hafnium oxide (HfO), hafnium gadolinium oxide (HfGdO), or hafnium silicate (HfSiO) (col 4 line 64 - col 5 line 2, teaches ferroelectric materials that may be used include, without limitation, hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium cerium oxide (HfCeO), hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium gadolinium oxide (HFGdO), or the like), as claimed. Regarding claim 6, Huang (US Patent Application Publication US 2022/0139935 A1) further teaches the semiconductor device of claim 1, the oxide semiconductor layer comprises zinc oxide, indium tungsten oxide, indium gallium zinc oxide, indium zinc oxide, or indium tin oxide (col 5, lines 28-37, teaches oxide semiconductors that may be suitable for the channel layer include, without limitation, zinc oxide (ZnO), magnesium oxide (MgO), gadolinium oxide (GdO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium zinc tin oxide (InGaZnSnO or IGZTO), indium tin oxide (InSnO or ITO), combinations thereof, or the like. In some embodiments, the channel layer is or includes polysilicon, amorphous silicon, silicon geranium (SiGe), or the like), as claimed. Regarding claim 7, Huang (US Patent Application Publication US 2022/0139935 A1) further teaches the semiconductor device of claim 1 wherein the ferroelectric layer comprises a first thickness (Figure 1A, col 5, lines 3-5, teaches the ferroelectric layer is from 0.1 nm to 100 nm thick. In some embodiments, the ferroelectric layer, is from 1 nm to 30 nm thick), wherein the high-k dielectric layer comprises a second thickness (Figure 1A, col 5, lines 11-14, teaches the dielectric layer has a thickness in the range from 0.1 nm to 10 nm. In some embodiments, the dielectric layer has a thickness in the range from 0.3 nm to 3 nm) smaller than the first thickness, as claimed. PNG media_image1.png 505 495 media_image1.png Greyscale Regarding claim 8, Huang (US Patent Application Publication US 2022/0139935 A1) further teaches the semiconductor device of claim 7, wherein the oxide semiconductor layer comprises a third thickness (Figure 1A, col 5, lines 37-42, teaches the channel layer has a thickness in the range from 0.1 nm to 100 nm. In some embodiments, the channel layer has a thickness in the range from 2 nm to 30 nm. In some embodiments, the channel layer has a thickness in the range from 5 nm to 20 nm) greater than the second thickness, as claimed. PNG media_image1.png 505 495 media_image1.png Greyscale Regarding claim 10, Huang (US Patent Application Publication US 2022/0139935 A1) teaches a device structure (integrated circuit device 100A, Figure 1A, col 4, line 40), comprising: a metal layer (gate electrode 105A, Figure 1A, col 5, line 48-49, teaches the gate electrode is formed with metals); a ferroelectric layer disposed on the metal layer (ferroelectric layer 107A, Figure 1A, col 4, lines 49-50, teaches the gate electrode is underneath the ferroelectric layer); a high-k dielectric layer disposed over the ferroelectric layer (dielectric layer 109A, Figure 1A, col 4, lines 48-49, teaches the ferroelectric layer and the channel layer are separated by a dielectric layer); a first contact feature and a second contact feature disposed on over the high-k dielectric layer (source coupling 117A & drain coupling 113A, Figure 1A); and an oxide semiconductor layer disposed over the high-k dielectric layer and extending between the first contact feature and the second contact feature (channel layer 111A, Figure 1A, col 4 lines 48-49 +col 5 lines 27-28, teaches the ferroelectric layer and the channel layer are separated by a dielectric layer...the channel layer is or includes an oxide semiconductor), as claimed. PNG media_image1.png 505 495 media_image1.png Greyscale Regarding claim 11, Huang (US Patent Application Publication US 2022/0139935 A1) further teaches the device structure of claim 10, wherein the ferroelectric layer comprises hafnium zirconium oxide (HfZrO), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium cerium oxide (HfCeO), hafnium oxide (HfO), hafnium gadolinium oxide (HfGdO), or hafnium silicate (HfSiO) (col 4 line 64 - col 5 line 2, teaches ferroelectric materials that may be used include, without limitation, hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium cerium oxide (HfCeO), hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium gadolinium oxide (HFGdO), or the like). Regarding claim 13, Huang (US Patent Application Publication US 2022/0139935 A1) further teaches the device structure of claim 10, wherein the oxide semiconductor layer comprises zinc oxide, indium tungsten oxide, indium gallium zinc oxide, indium zinc oxide, or indium tin oxide (col 5, lines 28-37, teaches oxide semiconductors that may be suitable for the channel layer include, without limitation, zinc oxide (ZnO), magnesium oxide (MgO), gadolinium oxide (GdO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium zinc tin oxide (InGaZnSnO or IGZTO), indium tin oxide (InSnO or ITO), combinations thereof, or the like. In some embodiments, the channel layer is or includes polysilicon, amorphous silicon, silicon geranium (SiGe), or the like), as claimed. Regarding claim 21, Huang (US Patent Application Publication US 2022/0139935 A1) teaches a semiconductor device (integrated circuit device 100A, Figure 1A, col 4, line 40), comprising: an electrode (gate electrode 105A, Figure 1A) in a first dielectric layer (substrate 103A, Figure 1A, col 4 lines 51-52 & col 6 lines 20-23, teaches the gate electrode may be buried in a substrate...The substrate may be or include a dielectric material. For example, the substrate may be a dielectric substrate or may include a dielectric layer on a semiconductor substrate); a ferroelectric layer over and interfacing the electrode and the first dielectric layer (ferroelectric layer 107A, Figure 1A, col 4, lines 49-50, teaches the gate electrode is underneath the ferroelectric layer); a high-k dielectric layer over and interfacing the ferroelectric layer (dielectric layer 109A, Figure 1A, col 4, lines 48-49, teaches the ferroelectric layer and the channel layer are separated by a dielectric layer); an oxide semiconductor layer over and interfacing the high-k dielectric layer (channel layer 111A, Figure 1A, col 4 lines 48-49 + col 5 lines 27-28, teaches the ferroelectric layer and the channel layer are separated by a dielectric layer...the channel layer is or includes an oxide semiconductor); a second dielectric layer (interlevel dielectric 115A, Figure 1A) over and interfacing the oxide semiconductor layer and the high- k dielectric layer; and a first contact feature and a second contact feature (source coupling 117A & drain coupling 113A, Figure 1A, col 4, lines 52-54, teaches the source coupling and the drain coupling may be vias in an interlevel dielectric) extending through the second dielectric layer to contact a top surface of the oxide semiconductor layer, as claimed. PNG media_image1.png 505 495 media_image1.png Greyscale Regarding claim 25, Huang (US Patent Application Publication US 2022/0139935 A1) further teaches the device structure of claim 21, wherein the oxide semiconductor layer comprises zinc oxide, indium tungsten oxide, indium gallium zinc oxide, indium zinc oxide, or indium tin oxide (col 5, lines 28-37, teaches oxide semiconductors that may be suitable for the channel layer include, without limitation, zinc oxide (ZnO), magnesium oxide (MgO), gadolinium oxide (GdO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium zinc tin oxide (InGaZnSnO or IGZTO), indium tin oxide (InSnO or ITO), combinations thereof, or the like. In some embodiments, the channel layer is or includes polysilicon, amorphous silicon, silicon geranium (SiGe), or the like), as claimed . Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-20-02-aia AIA This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 07-21-aia AIA Claim (s) 5, 9, 12, 14-15, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Huang (US Patent Application Publication US 2022/0139935 A1) in view of Manfrini (US Patent Application Publication US 2022/0376075 A1) . Regarding claim 5, Huang (US Patent Application Publication US 2022/0139935 A1) the semiconductor device of claim 1, as claimed. Huang (US Patent Application Publication US 2022/0139935 A1) is silent to teach wherein the high-k dielectric layer comprises aluminum oxide (AlO), titanium oxide (titanium oxide), niobium oxide (NbO), or lanthanum oxide (La 2 O 3 ). In an analogous art, Manfrini (US Patent Application Publication US 2022/0376075 A1) teaches wherein the high-k dielectric layer comprises aluminum oxide (AlO), titanium oxide (titanium oxide), niobium oxide (NbO), or lanthanum oxide (La 2 O 3 ) (gate dielectric 30, col 13 line 67 - col 14 line 5, gate dielectric material may include, but is not limited to, silicon oxide, silicon oxynitride, a high-k dielectric metal oxide (such as hafnium oxide, zirconium oxide, hafnium zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, lanthanum oxide, aluminum oxide, etc.), or a stack thereof). Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Huang (US Patent Application Publication US 2022/0139935 A1) by replacing the dielectric layer with the high-k dielectric material of Manfrini (US Patent Application Publication US 2022/0376075 A1) thereby increasing the durability and reliability of the ferroelectric layer by suppressing interface trap generation. Regarding claim 9, Huang (US Patent Application Publication US 2022/0139935 A1) the semiconductor device of claim 1 as claimed. Huang (US Patent Application Publication US 2022/0139935 A1) is silent to teach wherein the second dielectric layer contacts the oxide semiconductor layer and the high-k dielectric layer. In an analogous art, Manfrini (US Patent Application Publication US 2022/0376075 A1) teaches wherein the second dielectric layer (dielectric layer 48, Figure 9B) contacts the oxide semiconductor layer (active layer 20, Figure 9B) and the high-k dielectric layer (gate dielectric 30, Figure 9B) (col 16, lines 16-19, teaches the dielectric layer laterally surrounds the active layer...and contacts the entirety of a top surface of the gate dielectric). PNG media_image2.png 198 356 media_image2.png Greyscale Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Huang (US Patent Application Publication US 2022/0139935 A1) with the teachings of Manfrini (US Patent Application Publication US 2022/0376075 A1) thereby encasing the oxide semiconductor layer and the high-k dielectric layer within the second dielectric layer. Regarding claim 12, Huang (US Patent Application Publication US 2022/0139935 A1) the device structure of claim 10, as claimed. Huang (US Patent Application Publication US 2022/0139935 A1) is silent to teach wherein the high-k dielectric layer comprises aluminum oxide (AlO), titanium oxide (titanium oxide), niobium oxide (NbO), or lanthanum oxide (La 2 O 3 ). In an analogous art, Manfrini (US Patent Application Publication US 2022/0376075 A1) teaches wherein the high-k dielectric layer comprises aluminum oxide (AlO), titanium oxide (titanium oxide), niobium oxide (NbO), or lanthanum oxide (La 2 O 3 ) (col 13 line 67 - col 14 line 5, teaches the gate dielectric material may include, but is not limited to, silicon oxide, silicon oxynitride, a high-k dielectric metal oxide (such as hafnium oxide, zirconium oxide, hafnium zirconium oxide, titanium oxide, tantalum oxide, yttrium oxide, lanthanum oxide, aluminum oxide, etc.), or a stack thereof). Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Huang (US Patent Application Publication US 2022/0139935 A1) by replacing the dielectric layer with the high-k dielectric material of Manfrini (US Patent Application Publication US 2022/0376075 A1) thereby increasing the durability and reliability of the ferroelectric layer by suppressing interface trap generation. Regarding claim 14, Huang (US Patent Application Publication US 2022/0139935 A1) the device structure of claim 10, as claimed, Huang (US Patent Application Publication US 2022/0139935 A1) further teaches wherein each of the first contact feature and the second contact feature comprises a barrier layer in contact with the oxide semiconductor layer and a metal fill layer over the barrier layer (col 5, lines 42-54, teaches the source coupling, the drain coupling, and the gate electrode, may be formed of any suitable conductive materials...the source coupling, the drain coupling, and the gate electrode are formed with metals...One or more of the source coupling, the drain coupling, and the gate electrode may further include a diffusion barrier layer, a glue layer, or other such layer). Huang (US Patent Application Publication US 2022/0139935 A1) is silent to teach wherein the metal fill layer is spaced apart from the oxide semiconductor layer by the barrier layer. In an analogous art, Manfrini (US Patent Application Publication US 2022/0376075 A1) teaches wherein the metal fill layer (source metallic fill material portion 54 & drain metallic fill material portion 58, Figure 9B) is spaced apart from the oxide semiconductor layer (active layer 20, Figure 9B) by the barrier layer (source metallic liner 53 & drain metallic liner 57, Figure 9B). PNG media_image3.png 380 592 media_image3.png Greyscale Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Huang (US Patent Application Publication US 2022/0139935 A1) with the teachings of Manfrini (US Patent Application Publication US 2022/0376075 A1) thereby having the metal fill layers of the first and second contact features separated from the oxide semiconductor layer by the barrier layers of the first and second contact features. Regarding claim 15, Huang (US Patent Application Publication US 2022/0139935 A1) and Manfrini (US Patent Application Publication US 2022/0376075 A1) teach the device structure of claim 14, as claimed. Huang (US Patent Application Publication US 2022/0139935 A1) further teaches wherein the barrier layer comprises titanium nitride (col 5, lines 55-59, teaches materials that may be used for a diffusion barrier layer or a glue layer are titanium nitride (TiN), tantalum nitride (TaN), molybdenum nitride (MoN), zirconium nitride (ZrN), hafnium nitride (HfN), and the like), wherein the metal fill layer comprises tungsten (col 5, lines 49-52, teaches metals that may be used are tungsten (W), copper (Cu), ruthenium (Ru), molybdenum (Mo), cobalt (Co), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), and the like, and alloys thereof). Regarding claim 22, Huang (US Patent Application Publication US 2022/0139935 A1) the device structure of claim 21, as claimed. Huang (US Patent Application Publication US 2022/0139935 A1) is silent to teach wherein the second dielectric layer interfaces sidewalls of the oxide semiconductor layer. In an analogous art, Manfrini (US Patent Application Publication US 2022/0376075 A1) teaches wherein the second dielectric layer interfaces sidewalls of the oxide semiconductor layer (Figure 9B). PNG media_image4.png 256 430 media_image4.png Greyscale Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified the teachings of Huang (US Patent Application Publication US 2022/0139935 A1) with the teachings of Manfrini (US Patent Application Publication US 2022/0376075 A1) thereby extending the coverage of the second dielectric layer to interface with the sidewalls of the oxide semiconductor layer. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREEM M MOHAMED-ALY whose telephone number is (571)270-0312. The examiner can normally be reached Monday – Friday 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571) 270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K.M.A./Examiner, Art Unit 2898 /Leonard Chang/Supervisory Patent Examiner, Art Unit 2898 Application/Control Number: 18/620,250 Page 2 Art Unit: 2898 Application/Control Number: 18/620,250 Page 3 Art Unit: 2898 Application/Control Number: 18/620,250 Page 4 Art Unit: 2898 Application/Control Number: 18/620,250 Page 5 Art Unit: 2898 Application/Control Number: 18/620,250 Page 6 Art Unit: 2898 Application/Control Number: 18/620,250 Page 7 Art Unit: 2898 Application/Control Number: 18/620,250 Page 8 Art Unit: 2898 Application/Control Number: 18/620,250 Page 9 Art Unit: 2898 Application/Control Number: 18/620,250 Page 10 Art Unit: 2898 Application/Control Number: 18/620,250 Page 11 Art Unit: 2898 Application/Control Number: 18/620,250 Page 12 Art Unit: 2898 Application/Control Number: 18/620,250 Page 13 Art Unit: 2898 Application/Control Number: 18/620,250 Page 14 Art Unit: 2898 Application/Control Number: 18/620,250 Page 15 Art Unit: 2898 Application/Control Number: 18/620,250 Page 16 Art Unit: 2898
Prosecution Insights