Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-14) in the reply filed on 6/29/26 is acknowledged. Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Accordingly, claims 1–14 are examined on the merits in the present Office action. Claims 15–20 remain withdrawn from consideration as being directed to non-elected subject matter.
Election was made without traverse in the reply filed on 6/29/26.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 8 and 14 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 8 recites, in pertinent part, “wherein the body contact is connected to a biasing voltage source and/or further comprising a bit line contact electrically connected to one or more of the plurality of bit lines, wherein the bit line contact is electrically isolated from the body contact.”
The use of “and/or” renders the scope of claim 8 unclear because it is uncertain which combination of the recited limitations is required. Specifically, it is unclear whether claim 8 requires (i) the body contact to be connected to a biasing voltage source, (ii) a bit line contact electrically connected to one or more of the plurality of bit lines and electrically isolated from the body contact, or (iii) both limitations. Accordingly, the metes and bounds of claim 8 cannot be determined with reasonable certainty.
For purposes of examination and application of the prior art, the Examiner interprets the “and/or” limitation as encompassing the alternatives expressly recited in the claim. Thus, the Examiner interprets claim 8 as encompassing, inter alia, an embodiment in which the body contact is connected to a biasing voltage source, without requiring the alternatively recited bit line contact limitation.
Claim 14 recites, in pertinent part, “further comprising at least a second plurality of p-doped bridges extending between adjacent channels in the first row and between adjacent channels in the second row.”
Claim 14 depends from claim 13, which ultimately depends from claim 10. Claim 10 already requires “a plurality of p-doped bridges extending between adjacent channels in the first row and between adjacent channels in the second row.” Claim 14 then introduces “at least a second plurality of p-doped bridges” having the same recited relationship to adjacent channels.
The phrase “at least a second plurality” renders the scope of claim 14 unclear because it does not clearly identify the number or structural relationship of the additional p-doped bridges relative to the plurality of p-doped bridges already required by claim 10. In particular, it is unclear whether “at least a second plurality” requires one additional plurality of p-doped bridges, two or more additional pluralities of p-doped bridges, or merely another set of p-doped bridges without specifying the number of additional sets. Further, because both the plurality of claim 10 and the “second plurality” of claim 14 are recited as extending between adjacent channels in the first and second rows, the claim does not clearly define how the “second plurality” is distinguished structurally from the previously recited plurality.
Accordingly, the scope of claim 14 cannot be determined with reasonable certainty.
For purposes of examination and application of the prior art, the Examiner interprets “at least a second plurality of p-doped bridges” as requiring at least one additional plurality of p-doped bridges, distinct from the plurality recited in claim 10, with the additional plurality likewise extending between adjacent channels in the first row and between adjacent channels in the second row.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 5-6 and 10-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pandey et al. (US 20180374855; in the IDS on 12/17/24).
Regarding claim 1, Pandey discloses a vertical cell dynamic random-access memory (DRAM) array (Figs. 1–1C; [0013]-[0030]; see particularly [0030], disclosing one-transistor-one-capacitor (1T1C) memory cells), comprising:
a plurality of bit lines arranged in a first horizontal direction (digit/bit lines BL1-BL3 extending along the column direction/axis 7; Fig. 1; [0014], [0018], [0029]);
a plurality of word lines arranged in a second horizontal direction (wordlines WL1-WL3 extending along the row direction/axis 5; Fig. 1; [0014], [0016], [0021]), wherein the row direction/axis 5 is transverse to the column direction/axis 7;
a plurality of channels extending in a vertical direction that is generally orthogonal to the first horizontal direction and the second horizontal direction (channel regions 28 extending vertically within semiconductor pillars 17 between upper source/drain regions 24 and lower source/drain regions 26; Fig. 1A; [0013]-[0016]);
such that the plurality of bit lines intersect with a source/drain region of the plurality of channels (digit/bit lines BL1-BL3 coupled with lower source/drain regions 26; Figs. 1 and 1A; [0015], [0018]), wherein Pandey discloses that the lower source/drain regions 26 merge with the digit lines;
and the plurality of word lines intersect with gate regions of the plurality of channels (wordlines WL1-WL3 comprising gates 30 along channel regions 28; Figs. 1 and 1A; [0016]-[0017]), wherein Pandey discloses that gates 30 are along channel regions 28 and are comprised by regions of wordlines WL1-WL3; and
a p-doped bridge extending between a first channel of the plurality of channels and a second channel of the plurality of channels, wherein the first channel is spaced apart from the second channel in a row extending in the second horizontal direction (body connection line 40 comprising conductive material 42, extending between adjacent channel-containing semiconductor pillars 17 along the row direction/axis 5, parallel to wordlines WL1-WL3; Figs. 1 and 1A; [0020], [0023]-[0024]). Pandey discloses that the pillars 17 are spaced from one another along the row direction of axis 5, and that body connection lines 40 extend parallel to the wordlines. Pandey further discloses that body connection lines 40 comprise conductive material 42, which may comprise p-type doped silicon, and that the body connection lines 40 directly contact body regions of the access transistors within pillars 17, with lateral edges 43 penetrating into the pillars 17 ([0023]-[0024]).
Regarding claim 3, Pandey further discloses The vertical cell dynamic random access memory (DRAM) array of claim 1, Pandey further discloses a shallow trench isolation defined between the first channel and the second channel, the shallow trench isolation having a height extending from a first end to a second end (insulative material 32 disposed between adjacent semiconductor pillars 17 containing channel regions 28; Fig. 1B; [0020]). Pandey discloses that the pillars 17 are spaced from one another by insulative material 32 along the row direction of axis 5, and that insulative material 32 may comprise silicon dioxide. Pandey further discloses that insulative material 32 is formed within trenches 66 and may comprise silicon oxide [0036]. Fig. 1B shows insulative material 32 extending between adjacent channel-containing pillars 17 and having a height extending from a first end to a second end.
Regarding claim 5, Pandey further discloses The vertical cell dynamic random access memory (DRAM) array of claim 1, Pandey further discloses that the p-doped bridge is formed from crystalline silicon (body connection line 40 comprising conductive material 42; [0023]). Pandey expressly discloses that conductive material 42 of body connection lines 40 may comprise p-type doped silicon and may comprise, consist essentially of, or consist of polycrystalline silicon.
Regarding claim 6, Pandey further discloses The vertical cell dynamic random access memory (DRAM) array of claim 1, Pandey further discloses at least a third channel of the plurality of channels spaced apart from the second channel in the row extending in the second horizontal direction, wherein a second p-doped bridge extends between the second channel and the third channel (Fig. 1A; [0014]-[0016], [0020], [0023]-[0024]).
As shown in Fig. 1A, Pandey discloses a first channel region 28, an adjacent second channel region 28, and an adjacent third channel region 28 within respective semiconductor pillars 17, the channel-containing pillars being spaced apart along the row direction/axis 5 [0020]. Fig. 1A further shows a first body connection line 40 comprising conductive material 42 extending between the first and second channel-containing pillars 17, and a second body connection line 40 comprising conductive material 42 extending between the second and third channel-containing pillars 17. Pandey discloses that body connection lines 40 extend parallel to the wordlines and comprise conductive material 42, which may comprise p-type doped silicon [0023], and that body connection lines 40 directly contact the body regions of the access transistors within pillars 17, with lateral edges 43 penetrating into the pillars 17 [0024].
Regarding claim 10, Pandey discloses a vertical cell dynamic random-access memory (DRAM) array (Figs. 1–1C; [0013]-[0030]; see also [0030], disclosing one-transistor-one-capacitor (1T1C) memory cells), comprising:
a plurality of bit lines arranged in a first horizontal direction (digit/bit lines BL1-BL3 extending along the column direction/axis 7; Fig. 1; [0014], [0018], [0029]);
a plurality of word lines arranged in a second horizontal direction (wordlines WL1-WL3 extending along the row direction/axis 5; Fig. 1; [0014], [0016], [0021]), wherein the row direction/axis 5 is transverse to the column direction/axis 7;
a first plurality of spaced apart channels in a first row extending in the second horizontal direction (a first plurality of channel regions 28 within respective semiconductor pillars 17, spaced apart and arranged in a first row extending along the row direction/axis 5, e.g., the row associated with WL1; Figs. 1 and 1A; [0014]-[0016], [0020]);
a second plurality of spaced apart channels in a second row extending in the second horizontal direction, spaced apart from the first row (a second plurality of channel regions 28 within respective semiconductor pillars 17, spaced apart and arranged in a second row extending along the row direction/axis 5, e.g., the row associated with WL2, the second row being spaced apart from the first row in the column direction/axis 7; Figs. 1 and 1A; [0014]-[0016], [0020]-[0021]);
a plurality of p-doped bridges extending between adjacent channels in the first row and between adjacent channels in the second row (body connection lines 40 comprising conductive material 42, extending between adjacent channel-containing semiconductor pillars 17 along the respective rows and parallel to wordlines WL1-WL3; Figs. 1 and 1A; [0023]-[0024]). Pandey discloses that body connection lines 40 comprise conductive material 42, which may comprise p-type doped silicon, and that body connection lines 40 directly contact body regions of the access transistors within pillars 17, with lateral edges 43 penetrating into the pillars 17; and
wherein each channel of the first plurality of spaced apart channels and the second plurality of spaced apart channels extends in a vertical direction that is generally orthogonal to the first horizontal direction and the second horizontal direction such that the plurality of bit lines intersect with a source/drain region of each channel of the first plurality of spaced apart channels and the second plurality of spaced apart channels, and the plurality of word lines intersect with gate regions of each channel of the first plurality of spaced apart channels and the second plurality of spaced apart channels (channel regions 28 extending vertically within respective semiconductor pillars 17 between upper source/drain regions 24 and lower source/drain regions 26; digit/bit lines BL1-BL3 coupled with lower source/drain regions 26; and wordlines WL1-WL3 comprising gates 30 along channel regions 28; Figs. 1 and 1A; [0015]-[0018]). Pandey discloses that lower source/drain regions 26 merge with the digit lines and that gates 30 along channel regions 28 are comprised by regions of wordlines WL1-WL3.
Regarding claim 11, Pandey discloses The vertical cell dynamic random access memory (DRAM) array according to claim 10, Pandey further discloses a shallow trench isolation defined between adjacent channels in each row, the shallow trench isolation having a height extending from a first end to a second end (insulative material 32 disposed between adjacent semiconductor pillars 17 containing channel regions 28 in each row; Figs. 1, 1A and 1B; [0020]). Pandey discloses that the pillars 17 are spaced from one another by insulative material 32 along the row direction of axis 5, and that insulative material 32 may comprise silicon dioxide. Fig. 1 shows the arrangement of the channel-containing pillars 17 in rows, and Figs. 1A and 1B show insulative material 32 disposed between adjacent channel-containing pillars 17 and extending vertically from a first end to a second end.
Pandey further discloses that insulative material 32 is formed within trenches 66 and may comprise silicon oxide [0036].
Regarding claim 12, Pandey discloses The vertical cell dynamic random access memory (DRAM) array according to claim 10, Pandey further discloses second shallow trench isolations between adjacent channels in the first row and the second row, and a gate formed along an exterior surface of the second shallow trench isolations (insulative material 32 disposed between adjacent channel-containing semiconductor pillars 17, and gates 30 formed along exterior surfaces of insulative material 32; Figs. 1 and 1B; [0016], [0020]).
As shown in Fig. 1B, Pandey discloses insulative material 32 between adjacent semiconductor pillars 17 containing channel regions 28, with gates 30 extending along exterior surfaces of the insulative material 32. Pandey discloses that pillars 17 are spaced from one another by insulative material 32, which may comprise silicon dioxide [0020]. Pandey further discloses that gates 30 extend along channel regions 28 and are comprised by regions of wordlines WL1-WL3 [0016].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Pandey et al. (US 20180374855; in the IDS on 12/17/24) in view of Or-Bach et al. (US 20180269229).
Regarding claim 2, Pandey discloses the vertical cell DRAM array of claim 1, including p-type doped body connection material 40/42 extending between adjacent channel regions, as discussed above. Pandey further discloses doped channel regions [0034).
But Pandey does not expressly disclose that the p-doped bridge has a doping level greater than a doping level of the first and second channels.
However, Or-Bach discloses P-type channel regions 4128 and highly doped P-type body contacts 4248 associated with and extending between the P-type channel regions (Fig. 42E; [0346]-[0347]). Thus, Or-Bach teaches a P-type body-contact region having a greater doping level than the P-type channel regions.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide Pandey's p-type body connection material 40/42 with a greater doping level than Pandey's channel regions, as taught by Or-Bach, in order to provide a highly doped P-type body-contact/body-connection region for electrically connecting the transistor bodies.
Accordingly, the combination of Pandey and Or-Bach teaches the limitation that “the p-doped bridge has a doping level greater than or about 1.6 times a doping level of the first channel and the second channel,” because Or-Bach teaches the claimed “greater than” alternative.
Regarding claim 7, Pandey discloses the limitations of claim 3 as discussed above, including p-type doped body connection lines 40/42 extending between and directly contacting body regions of adjacent channel-containing semiconductor pillars ([0023]-[0024]). Pandey further teaches that body connection lines 40 may be coupled with a common reference voltage 44 [0025].
But Pandey does not expressly disclose a separate body contact in electrical connection with the p-doped bridge.
However, Or-Bach discloses a body contact 4248 providing a connection to P-type channel/body regions 4218 (Fig. 42E; [0346]-[0347]). Or-Bach expressly teaches that body contact 4248 may comprise highly doped P-type polysilicon or other conductive material forming the body connection, and further teaches applying a voltage to the body contact to control the transistor body, including to absorb generated majority carriers.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide Pandey's p-type body connection line 40/42 with a body contact as taught by Or-Bach, in order to provide an electrical connection to the body connection line and permit application of a desired body/reference voltage thereto, consistent with Pandey's express teaching that body connection lines 40 are coupled to reference voltage 44.
Regarding claim 8, Pandey in view of Or-Bach discloses The vertical cell dynamic random access memory (DRAM) array of claim 7 as discussed above, Pandey in view of Or-Bach further discloses the limitation wherein the body contact is connected to a biasing voltage source.
As discussed above regarding claim 7, Or-Bach teaches providing a body contact 4248 for electrically contacting a P-type body/channel region, including a highly doped P-type body contact for providing the body connection (Or-Bach, Fig. 42E; [0346]-[0347]).
Pandey further expressly teaches that the body connection lines 40 may all be coupled with a common reference voltage 44, as diagrammatically illustrated in Fig. 1C, and that reference voltage 44 may be any suitable reference voltage, including a ground voltage or a common plate voltage (Pandey, Fig. 1C; [0025]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to connect the body contact, as taught by Or-Bach and provided in electrical connection with Pandey's p-type body connection line 40/42 as discussed above regarding claim 7, to a biasing voltage source, in order to apply a desired body/reference voltage to the body connection line and thereby control the body potential, consistent with Pandey's express teaching of coupling body connection lines 40 to common reference voltage 44.
Claims 4 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Pandey et al. (US 20180374855; in the IDS on 12/17/24).
Regarding claim 4, Pandey discloses the limitations of claim 3 as discussed above, including a shallow trench isolation 32 defined between the first and second channels and a p-type body connection line 40/42 extending between and directly contacting body regions of the adjacent channels (Pandey, Figs. 1A-1B; [0020], [0023]-[0024]).
But Pandey does not expressly disclose that the p-type body connection line 40/42 is disposed in the shallow trench isolation at about 20% to about 80% of the height of the shallow trench isolation.
However, the vertical position of the body connection line relative to the adjacent transistor body/channel regions and isolation structure is a result-effective design variable, because the position of the body connection determines the location at which the transistor bodies are electrically interconnected and contacted and thus affects electrical access to and control of the transistor body. Pandey itself teaches that body connection lines 40 directly contact the body regions of the access transistors and are provided for electrically coupling those body regions to a reference voltage [0024]-[0025]. Thus, one of ordinary skill in the art would have recognized the position of the body connection line relative to the body/channel and surrounding isolation as a variable affecting implementation of the desired body connection.
Thus, it therefore would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to select and optimize the vertical position of Pandey's p-type body connection line 40/42 within the shallow trench isolation 32 to provide a suitable location for electrically connecting the adjacent transistor bodies while accommodating the surrounding isolation and transistor structures. Selection of a workable position would have involved no more than routine optimization of a known result-effective variable.
The claimed range of about 20% to about 80% of the height encompasses a broad portion—approximately the central 60%—of the shallow trench isolation and therefore encompasses ordinary intermediate positions available for placement of the body connection line. One of ordinary skill performing such routine optimization would have arrived at a position within the claimed range with a reasonable expectation of successfully providing the desired body connection.
Moreover, the Specification does not establish that the endpoints of about 20% and about 80% are critical or that positioning the p-doped bridge within the claimed range produces an unexpected result compared with positions outside the claimed range. Rather, the claimed range represents a broad range of intermediate positions for the p-doped bridge. Accordingly, the claimed range does not distinguish the claimed subject matter from the routine optimization of Pandey's known body connection structure.
Therefore, it would have been obvious to one of ordinary skill in the art to dispose Pandey's p-type body connection line 40/42 within shallow trench isolation 32 at a position of about 20% to about 80% of the height of the shallow trench isolation, as a matter of routine optimization of the vertical position of the body connection, thereby arriving at the subject matter of claim 4.
Regarding claim 13, Pandey discloses the limitations of claim 11 as discussed above, including body connection lines 40 comprising conductive material 42, which may comprise p-type doped silicon [0023].
But Pandey does not expressly disclose a conductive material overlying each p-doped bridge.
However, Pandey discloses the body connection lines 40/42 underlying insulative material 50, as shown in Fig. 1B, and expressly teaches that the body connection lines 40 may all be coupled with a common reference voltage 44, as diagrammatically illustrated in Fig. 1C [0025].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide conductive material overlying each body connection line 40/42 in order to provide an electrical connection to the underlying body connection lines and thereby implement Pandey's expressly disclosed electrical coupling of body connection lines 40 to common reference voltage 44. Providing such overlying conductive material would have been a predictable use of a known conductive interconnection to electrically access the underlying body connection structure.
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 9, the prior art of record fails to teach or suggest, in combination with all of the limitations of claim 9, a second p-doped bridge extending between the same first channel and second channel, in addition to the p-doped bridge extending between the first channel and second channel already required by claim 9.
Although the prior art of record teaches p-type body connection structures extending between adjacent semiconductor channels, the Examiner has not identified a teaching or suggestion of two separate p-doped bridges extending between the same first channel and second channel. In particular, the prior art of record does not teach or suggest providing a second p-doped bridge between the same pair of channels in addition to the first p-doped bridge recited in claim 9.
Accordingly, claim 9 is allowable because the prior art of record, whether considered individually or in combination, fails to teach or suggest the above-identified second p-doped bridge in combination with the remaining limitations of claim 9.
Claim 14 would be allowable if amended to overcome the rejection under 35 U.S.C. 112(b) without introducing new matter or otherwise materially altering the scope of the allowable subject matter.
In particular, the prior art of record fails to teach or suggest, in combination with all of the limitations of the claims from which claim 14 depends, an additional plurality of p-doped bridges, distinct from the plurality of p-doped bridges recited in claim 10, extending between adjacent channels in the first row and between adjacent channels in the second row.
Although the prior art of record teaches p-type body connection structures extending between adjacent semiconductor channels, the prior art does not teach or suggest the claimed arrangement having an additional plurality of p-doped bridges extending between adjacent channels of the respective rows, as claim 14 is interpreted for purposes of examination.
Accordingly, if claim 14 is amended to overcome the rejection under 35 U.S.C. 112(b) while retaining the above-identified allowable subject matter, claim 14 would be allowable.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Changhyun Yi whose telephone number is (571)270-7799. The examiner can normally be reached Monday-Friday: 10A-3P.
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/Changhyun Yi/Primary Examiner, Art Unit 2812
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