DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made that applicant's Amendment, filed on August 10th, 2026, has been entered.
Upon entrance of the Amendment, claims 1, 8, 16, and 19 were amended. Claims 1-20 are currently pending.
Response to Arguments
Applicant’s arguments with respect to independent claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-6, and 8-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yaginuma et al. (U.S. Patent Application Publication No. 2012/0153277).
Regarding to claim 1, Yaginuma teaches display device comprising:
a substrate (Fig. 2B, element 1);
a first transistor including:
a first bottom gate electrode disposed on the substrate (Fig. 2B, element 2),
a first active layer disposed on the first bottom gate electrode (Fig. 2B, element 4) and including a first channel region (Fig. 2, portion of active layer 4 that not overlap electrodes 6 and 7), a first drain region (Fig. 2, portion of active layer 4 that overlaps source electrode 6), and a first source region (Fig. 2, portion of active layer 4 that overlaps drain electrode 7), and
a first top gate electrode on a portion of the first active layer including the first channel region (Fig. 2B, element 20);
a first insulating layer between the first bottom gate electrode and the first active layer (Fig. 2B, element 3); and
a second insulating layer disposed between the first active layer and the first top gate electrode (Fig. 2B, element 30),
wherein the second insulating layer has a first thickness across its entire length that overlaps the first channel region (Fig. 2B, please see annotations in the attached figure), and
wherein the second insulating layer has a second thickness smaller than the first thickness across its entire length that overlaps the first source region and across its entire length that overlaps the first drain region (Fig. 2B, please see annotations in the attached figure).
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Regarding to claim 2, Yaginuma teaches the first channel region includes: a lower layer portion adjacent to the first bottom gate electrode, and an upper layer portion adjacent to the first top gate electrode, and the lower layer portion of the first channel region has a first length, and the upper layer portion of the first channel region has a second length greater than the first length (Fig. 2B, the claimed features are inherently met by arbitrary defining, please see the attached figure).
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Regarding to claim 3, Yaginuma teaches in a cross-section of the first active layer, the first channel region has an inverted trapezoidal shape of which a length increases as being closer to the upper layer portion from the lower layer portion (Fig. 2B, please see the attached figure above).
Regarding to claim 5, Yaginuma teaches the second insulating layer includes an upper layer portion in contact with the first top gate electrode, and the upper layer portion of the second insulating layer and the first top gate electrode have a same pattern shape (Fig. 2B, please see the attached figure below).
Regarding to claim 6, Yaginuma teaches the second insulating layer includes an upper layer portion in contact with the first top gate electrode, and the upper layer portion of the second insulating layer and the first top gate electrode have a same area (Fig. 2B, please see the attached figure below).
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Regarding to claim 8, Yaginuma teaches the second insulating layer has a step portion having a stair shape where it overlaps with an interface between the first channel region and the first source region and where it overlaps with an interface between the first channel region and the first drain region (Fig. 2B).
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Regarding to claim 9, Yaginuma teaches a third insulating layer covering the second insulating layer and the first top gate electrode (in the display, entire thinfilm transistor is encapsulated in insulating layer under the emitting layers).
Regarding to claim 10, Yaginuma teaches at least one of: a first drain electrode disposed on the third insulating layer and connected to the first drain region through a first contact hole penetrating through the second insulating layer and the third insulating layer; and a first source electrode disposed on the third insulating layer and connected to the first source region through a second contact hole penetrating through the second insulating layer and the third insulating layer, wherein the second insulating layer entirely covers the first active layer except for a portion where at least one of the first contact hole and the second contact hole is formed (Fig. 1H).
Regarding to claim 11, Yaginuma teaches the first bottom gate electrode is electrically connected to the first top gate electrode (both gate electrodes must contact a controller to turn on/off the transistor).
Regarding to claim 12, Yaginuma teaches a pixel including the first transistor (this TFT is a part of a display, to control emission of a pixel).
Regarding to claim 13, Yaginuma teaches the pixel further includes a second transistor, and the second transistor includes: a second active layer disposed on the first insulating layer and including a second channel region, a second drain region, and a second source region; and a second top gate electrode disposed on the second insulating layer and disposed on a portion of the second active layer including the second channel region (only one TFT of a display in shown in the figure, the display contains thousands of pixels with thousands of identical TFTs).
Regarding to claim 14, Yaginuma teaches the second insulating layer covers the second active layer, and includes: a third portion disposed on a portion of the second active layer including the second channel region and having the first thickness, and a fourth portion disposed on a remaining portion of the second active layer and having the second thickness (only one TFT of a display in shown in the figure, the display contains thousands of pixels with thousands of identical TFTs).
Regarding to claim 15, Yaginuma teaches the first active layer and the second active layer include a same oxide semiconductor (only one TFT of a display in shown in the figure, the display contains thousands of pixels with thousands of identical TFTs).
Allowable Subject Matter
Claims 16-20 are allowed.
Claims 4 and 7 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 4 the prior art fails to anticipate or render obvious the claimed limitations including “the lower layer portion of the first channel region has a higher carrier concentration than the upper layer portion of the first channel region” in combination with the limitations recited in claim 1 and the rest of limitations in claim 4.
Regarding to claim 7 the prior art fails to anticipate or render obvious the claimed limitations including “a side surface of the first top gate electrode and a side surface of the second insulating layer have an inclined surface having a continuously connected form” in combination with the limitations recited in claim 1.
Regarding to claim 19 the prior art fails to anticipate or render obvious the claimed limitations including “using a same mask as a mask used in etching of the conductive film or using the top gate electrode as a mask so as to give the second insulating layer a first thickness across its entire length that overlaps a channel region of the active layer and to give the second insulating layer a second thickness smaller than the first thickness across its entire length that overlaps a source region of the active layer and across its entire length that overlaps a drain region of the active layer” in combination with the rest of limitations in claim 19.
Claim 16 has been rewritten in independent form including all of the limitations of the base claim. The reasons for allowance of claim 16 were indicated in the previous Office Action.
Claims 17-18 and 20 are allowable for same reasons with the claims which they are dependent from.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VU A VU/Primary Examiner, Art Unit 2897
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