DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The status of the claims is as follows: Claims 1-20 are pending.
Claims 12-20 are withdrawn in response to restriction requirement. An action on the merits for claims 1-11 follows.
Election/Restrictions
Applicants’ election with traverse of Group I (corresponding to Claims 1-10) in the reply filed on 07/21/2026 is acknowledged. The traversal is on the grounds that there is no serious search burden between a semiconductor device and a method of manufacturing a semiconductor device. This is not found persuasive because applicant neither refutes the reasons for search burden given in the requirement for restriction sent 06/04/2026 (of requiring different search strategies and being classified in different CPC groups) nor articulates any supporting rationale as to a search for a semiconductor device would necessarily result in a search for a method of manufacturing a semiconductor device for the claimed device/method of this application. Accordingly, claims 12-20, reading on the non-elected Group II, have been withdrawn from consideration at this time. Claim 11 is considered with Group I because it does not appear to have any search burden with Claim 1.
Claim Rejections - 35 USC § 102
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 8-11 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Guler et al. (US 20240105716 A1), hereinafter Guler.
Regarding Claim 1, Guler teaches a semiconductor device ("integrated circuit structure" (149); Figs. 1A-1D, Paragraph [0038]), comprising:
first transistors (1T; Annotated Fig. 1D) positioned over a substrate ("substrate," (102); Fig. 1D, Paragraph [0033]) and arranged along a first row in a first direction (D1; Annotated Fig. 1D) substantially parallel to a working surface of the substrate (102);
second transistors (2T; Annotated Fig. 1D) positioned over the substrate (102) and arranged along a second row in the first direction (D1), each first transistor (1T) aligned with a respective second transistor (2T; Fig. 1D) in a second direction (D2; Annotated Fig. 1D) substantially parallel to the working surface of the substrate (102); and
an isolation wall structure ("dielectric plug," (148); Paragraph [0037]) positioned between the first transistors (1T) and the second transistors (2T).
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Regarding Claim 8, Guler teaches the semiconductor device of claim 1, wherein:
the isolation wall structure (148) consists of a dielectric material ("dielectric plug;" Paragraph [0037]) in a cross section substantially perpendicular (i.e. , in the direction of D3; Annotated Fig. 1D) to the working surface of the substrate (102).
Regarding Claim 9, Guler teaches the semiconductor device of claim 8, wherein:
the isolation wall structure (148) is continuous and seamless in the cross section (Fig. 1D).
Regarding Claim 10, Guler teaches the semiconductor device of claim 8, wherein:
the cross section is substantially parallel (Annotated Fig. 1D) to the first direction (D1).
Regarding Claim 11, Guler teaches a method of manufacturing a semiconductor device ("integrated circuit structure" (149); Figs. 1A-1D, Paragraph [0038]), the method comprising:
forming first transistors (1T; Annotated Fig. 1D) over a substrate ("substrate," (102); Fig. 1D, Paragraph [0033]), the first transistors (1T) arranged along a first row in a first direction (D1; Annotated Fig. 1D) substantially parallel to a working surface of the substrate (102);
forming second transistors (2T; Annotated Fig. 1D) over the substrate (102), the second transistors (2T) arranged along a second row in the first direction (D1), each first transistor (1T) aligned with a respective second transistor (2T; Fig. 1D) in a second direction (D2; Annotated Fig. 1D) substantially parallel to the working surface of the substrate (102); and
forming an isolation wall structure ("dielectric plug," (148); Paragraph [0037]) between the first transistors (1T) and the second transistors (2T).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-7 are rejected under 35 U.S.C. 103 as being unpatentable over Guler in view of Song et al. (US 20250275235 A1), hereinafter Song.
Regarding Claim 2, Guler teaches the semiconductor device of claim 1.
Guler does not explicitly teach wherein:
the isolation wall structure includes slab structures and block structures arranged alternatingly along the first direction, and
the slab structures are thinner than the block structures in the second direction.
Song teaches at least a semiconductor device ("semiconductor device," (30); Fig. 3A, Paragraph [0056]), wherein:
the isolation wall structure (119, 219) includes slab structures ("isolation wall," (119); Fig. 3A, Paragraph [0059]) and block structures ("gate cut structures," (219); Paragraph [0056]) arranged alternatingly along the first direction ("D1 direction," (D1); Paragraph [0061]), and
the slab structures (119) are thinner than the block structures (219) in the second direction ("D2 direction," (D2); Paragraph [0060]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the isolation wall structure of Song with the device of Guler to include slab and block structures arranged alternatingly along the first direction. This is because the wider block structure is more likely to ensure isolation between transistors by having a higher margin of acceptable misalignment in the formation process that still isolates gate regions (Song, Paragraph [0060]).
Regarding Claim 3, Guler as modified by Song teaches the semiconductor device of claim 2, wherein:
the slab structures (Song, 119) consist of a first dielectric material (Song, "formed of a dielectric material;" Paragraph [0039, 0056]).
Regarding Claim 4, Guler as modified by Song teaches the semiconductor device of claim 3, further comprising:
a second dielectric material (Guler, "cut gate structure," (132A); Fig. 1D, Paragraph [0037]) formed on opposing sides of each of the slab structures (Song, 119) as well as formed between gate contact structures (Guler, "gate electrode," (134A); Fig. 1D, Paragraph [0037]) of the first transistors (Guler, 1T) and source/drain (S/D) contact structures (Guler, "trench contact structure," (140); Fig. 1D, Paragraph [0037]) of the first transistors (Guler, 1T). (Note: by modifying the isolation wall structure of Guler with that of Song, the slab structures of Song would implicitly be contacted on both sides by the second dielectric material of Guler).
Regarding Claim 5, Guler as modified by Song teaches the semiconductor device of claim 3.
Guler as modified by Song does not explicitly teach a sidewall structure consisting of the first dielectric material and positioned parallel to and away from the slab structures.
Song further teaches a semiconductor device ("semiconductor device," (30); Fig. 3A, Paragraph [0056]) comprising:
a sidewall structure (Song, “2nd isolation wall,” (129); Paragraph [0056]) consisting of the first dielectric material (Song, “formed of a dielectric material;" Paragraphs [0039, 0056]) and positioned parallel to and away from (Song, Fig. 3A) the slab structures (Song, 119).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further combine the teachings of Song with the device of Guler as to include a sidewall structure consisting of the first dielectric material and positioned parallel to and away from the slab structures. This is because the sidewall structure has the added benefit of further isolating adjacent transistor from each other in a second direction (Paragraph [0060]).
Regarding Claim 6, Guler as modified by Song teaches the semiconductor device of claim 2, wherein: the slab structures (Song, 119) are co-planar (Song, Fig. 3A).
Regarding Claim 7, Guler as modified by Song teaches the semiconductor device of claim 2, wherein:
the slab structures (Song, 119) are positioned between source/drain (S/D) structures (Song, "source/drain patterns," (115, 125); Fig. 3A, Paragraphs [0040, 0056]) of the first transistors (Song, "1st transistor," (100); Paragraphs [0033,0056]) and the second transistors (Song, "2nd transistor," (200); Paragraphs [0033, 0056]), and
the block structures (Song, 219) are positioned between gate structures (Song, "gate structures," (151, 152); Paragraph [0060]) of the first transistors (Song, 100) and the second transistors (Song, 200).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Patel et al. (US 20240222447 A1) teaches an isolation wall structure between two rows of transistors.
Chen et al. (US 20220131004 A1) teaches an isolation wall with alternating structures of different thicknesses.
Guler et al. (US 20230299081 A1) teaches an isolation wall structure with different components separating gate structures and source/drain structures.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nolan Stuessy whose telephone number is (571) 645-5843. The examiner can normally be reached on M-F; 9:00-5:00 (EST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/NOLAN GABRIEL STUESSY/Examiner, Art Unit 2812 /DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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