DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot in view of the new ground of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US2020/0303030 A1) and further in view of Liao et al (US20200303030A1).
Claim 1: Lee teaches a testing circuit (e.g. The test control circuits (114, 124, 134, 144) perform BIST on the plurality of chips- Abstract ), configured to test ([0042])a plurality of electrical devices (e.g. items 110, 120, 130, fig. 1), wherein the testing circuit comprises:
a mechanism for triggering the devices to sequentially perform a testing operation (e.g. [0044], [0134]-[0139]; Fig. 14. A test start signal (BIST_START) is sequentially activated based on the deactivation of an upper chip's control signal); and
a mechanism for outputting the delayed trigger signal to the corresponding electrical devices (e.g. The control signal generator (414) outputs a test start signal (BIST_START) to trigger the command/address generation circuit (430) of a corresponding chip. Fig. 11, 13; Par. [0122]-[0124], [0132]. The BIST_START signal is the "trigger" that initiates the chip's internal test operation);
wherein each of the electrical devices comprises: a storage circuit, being configured to receive the delayed trigger signal and store a latency counter value of the electrical device (e.g. Each chip has a counting circuit (4144) that generates a counting signal (BISTCNT) by counting test pulse signals (BISTENP). Fig. 13; Par. [0124]. The BISTCNT value is a stored counter that identifies the chip's sequence), wherein the latency counter value is obtained by adding a corresponding reference counter value with a delayed time period of corresponding trigger signal (e.g. The counting signal (BISTCNT) is generated by counting the number of times the test pulse signal (BISTENP) toggles. Par. [0124] states, "The counting circuit 4144 may generate a counting signal BISTCNT<0:1> by counting the number of times the test pulse signal BISTENP toggles." The BISTENP signal is derived from and thus inherently includes the "delayed time period" of the preceding chip's deactivation. The BISTCNT value for a given chip is, in effect, the sum of all previous trigger events (a reference state) plus its own trigger event. Fig. 13; Par. [0124], [0133]. The BISTCNT increments with each sequential trigger, functioning as a cumulative latency counter),
wherein each of the electrical devices determines a time point for outputting the testing result according to the latency counter value (e.g. The counting signal (BISTCNT) is generated by counting the number of times the test pulse signal (BISTENP) toggles. Par. [0124] states, "The counting circuit 4144 may generate a counting signal BISTCNT<0:1> by counting the number of times the test pulse signal BISTENP toggles." The BISTENP signal is derived from and thus inherently includes the "delayed time period" of the preceding chip's deactivation. The BISTCNT value for a given chip is, in effect, the sum of all previous trigger events (a reference state) plus its own trigger event. Fig. 13; Par. [0124], [0133]. The BISTCNT increments with each sequential trigger, functioning as a cumulative latency counter).
Lee does not teach disposing the trigger pad or the delay circuits on a scribe line of a substrate. However, Wang teaches test pads and test elements, are disposed in the scribe line regions of a semiconductor wafer [Wang, Abstract, Par. [0006]]. Wang establishes that using the scribe line for test circuitry is a well-known, conventional practice in semiconductor manufacturing to conserve space on the active die area and facilitate testing [Wang, Par. [0008]].Therefore, it would have been an obvious matter of design choice to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to place the known test control circuitry of Lee into the known, conventional location for test circuitry as taught by Wang, since such a modification would have involved placing a known element in a location routinely used for such a purpose, especially when motivated by a recognized advantage such as space conservation and efficient testing (MPEP § 2143).
As per claim 11, the claimed features are rejected similarly to claim 1 above.
Claim 2: Lee and Wang teach the testing circuit according to claim 1, but fail to teach that wherein the testing circuit further comprises: a plurality of second pads, disposed on the scribe line of the substrate, and electrically connected to the electrical devices, wherein the second pads are configured to receive a clock signal, a power signal, and a test command and output the clock signal, the power signal, and the test command to the electrical devices, wherein the electrical devices perform the testing operation according to the clock signal, the power signal, and the test command. However, Wang teaches that it is conventional to form test key structures, including input/output pads for receiving test signals, power, and clock, within the scribe line region of a wafer (see Wang, Abstract, Par. [0006]-[0008]). Therefore, it would have been obvious to a person of ordinary skill in the art to implement the signal distribution function required by Lee's testing system using the conventional scribe-line pad layout taught by Wang. Placing signal pads in the scribe line to conserve active die area and facilitate centralized test access is a well-known design practice motivated by efficiency and space conservation.
As per claim 12, the claimed features are rejected similarly to claim 2 above.
Claim 3: Lee and Wang teach the testing circuit according to claim 2, wherein each of the electrical devices further comprises: a logic circuit, electrically connected to the second pads, and configured to receive and output the clock signal and the test command; a built-in self-test circuit, electrically connected to the logic circuit, and configured to perform the testing operation according to the clock signal and the test command; and a data bus, electrically connected to the built-in self-test circuit, and configured to output the testing result. For instance, Lee’s semiconductor chips (110–140) include an internal circuit (core region) that performs a test operation (Lee ¶0043). The internal circuit includes a logic circuit (e.g., command reception circuit 112 and internal control logic) for receiving and processing commands, a BIST circuit (e.g., test control circuits 114, 124, 134, 144 and associated internal circuitry) for performing the test operation (Lee ¶¶0042, 0044), and a data bus for outputting test results, which is a conventional and necessary component in BIST-equipped devices for communicating test status.
As per claim 13, the claimed features are rejected similarly to claim 3 above.
Claim 4: Lee and Wang teach the testing circuit according to claim 3, but fail to teach that each of the electrical devices comprises: an input pad, electrically connected to the corresponding delay circuit, and configured to receive and output the delayed trigger signal. However, Lee’s system inherently requires each chip to receive a control signal (e.g., BISTEN_SUM or BIST_START) to initiate testing. Thus, it would have been obvious to provide an input pad on each device to receive such a signal from the scribe-line circuitry. Wang teaches that test structures in the scribe line include pads for electrical connection and probing (Wang, Abstract). It is a direct and conventional extension of this teaching to provide a dedicated input pad on a test circuit to receive a control signal. Therefore, given that Wang establishes the scribe line as the standard location for test circuitry with input/output pads, it would have been obvious to provide each test-control block (as taught by Lee) with its own input pad in that location to receive its triggering control signal. This is a straightforward application of conventional interconnection methods to a known testing circuit layout.
As per claim 14, the claimed features are rejected similarly to claim 4 above.
As per claims 5-7, 9, 15-17 and 19, the claims recite that each device includes a storage circuit (e.g., a register) connected to the input pad and configured to receive the delayed trigger signal from the input pad. Lee's system teaches a functional equivalent: each chip's control signal generation circuit (410) receives a triggering input (the sum signal BISTEN_SUM from an upper chip via through-electrodes) (Par. [0107]). Within this circuit, the counting circuit (4144) and associated logic function as a storage circuit that receives and processes this input to determine when to activate the test (Par. [0124], [0134]-[0138]). Therefore, Lee discloses the functional relationship where a storage/processing circuit is configured to receive a triggering signal. And Wang teaches that test circuits and their interconnected components are conventionally placed in the scribe line, with pads for electrical access (Wang, Abstract, Par. [0006]). Once it is rendered obvious by the combination of Lee and Wang to implement a test control block with an input pad in the scribe line (as established for claim 4), it would be a trivial and obvious matter of ordinary design to electrically connect the internal components of that block. Specifically, connecting the input pad to the storage/logic circuit that must process the incoming signal is a necessary and conventional step in implementing any functional circuit, requiring no more than routine skill.
As per claim 8, the claim is an obvious design alternative to the embodiment of claims 5–7, which is a fundamental and predictable choice in digital logic design to route a control signal either directly to functional circuitry or through a configurable storage element. Lee and Wang fail to teach that the logic circuit is further electrically connected to the input pad and configured to receive and output the delayed trigger signal, and the built-in self-test circuit is further configured to perform the testing operation according to the delayed trigger signal so as to output the testing result. However, Lee teaches test control signals provided directly to internal command logic and BIST circuitry (LEE Fig. 2; ¶0054). Accordingly, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to implement the system such that the delayed trigger signal is provided directly to the logic and BIST circuits, thereby achieving a simpler, non-configurable sequential triggering scheme.
As per claim 18, the claimed features are rejected similarly to claim 8 above.
Claim 10: Lee and Chatterjee et al teach the testing circuit according to claim 1, wherein each of the electrical devices is a memory chip. For instance, Lee’s stacked semiconductor device comprises semiconductor chips 110, 120, 130, and 140 that are memory chips (Lee ¶0035).
As per claim 20, the claimed features are rejected similarly to claim 10 above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US8,952,497.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 2/9/2026