DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application is being examined under the pre-AIA first to invent provisions.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 38-55 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With regards to claim 38,The claim recites that “said bipolar device and said access device are electrically connected in series “but it contradicts that structure of the specification. The specification discloses [0125]that the bipolar devices is not separate but an inherent in the floating body transistor formed by the buried well region, and the source drain regions. Claiming an inherent region or internal component of a transistor as a distinct element connected in series leaves the scope of the invention unclear rendering the structural arrangement ambiguous.
With regards to claim 44,The claim recites that “said bipolar device and said access device are electrically connected in series “but it contradicts that structure of the specification. The specification discloses [0125]that the bipolar devices is not separate but an inherent in the floating body transistor formed by the buried well region, and the source drain regions. Claiming an inherent region or internal component of a transistor as a distinct element connected in series leaves the scope of the invention unclear rendering the structural arrangement ambiguous.
With regards to claim 50,The claim recites that “said bipolar device and said access device are electrically connected in series “but it contradicts that structure of the specification. The specification discloses [0125]that the bipolar devices is not separate but an inherent in the floating body transistor formed by the buried well region, and the source drain regions. Claiming an inherent region or internal component of a transistor as a distinct element connected in series leaves the scope of the invention unclear rendering the structural arrangement ambiguous.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of pre-AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(e) the invention was described in (1) an application for patent, published under section 122(b), by another filed in the United States before the invention by the applicant for patent or (2) a patent granted on an application for patent by another filed in the United States before the invention by the applicant for patent, except that an international application filed under the treaty defined in section 351(a) shall have the effects for purposes of this subsection of an application filed in the United States only if the international application designated the United States and was published under Article 21(2) of such treaty in the English language.
Claim(s)38,39, 41, 43, 44,45,47,49, 50,51,53,55 is/are rejected under pre-AIA 35 U.S.C. 102(e) as being anticipated by Widjaja (US Pub no. 2014/0036577 A1)
The applied reference has a common inventor with the instant application. Based upon the pre-AIA 35 U.S.C. 102(e) date of the reference, it constitutes prior art. This rejection under pre-AIA 35 U.S.C. 102(e) might be overcome either by a showing under 37 CFR 1.132 that any invention disclosed but not claimed in the reference was derived from the inventor or joint inventors (i.e., the inventive entity) of this application and is thus not the invention “by another,” or if the same invention is not being claimed, by an appropriate showing under 37 CFR 1.131(a).
Regarding claim 38, Widjaja et al discloses A semiconductor memory cell comprising:
a bipolar device (531 or 532 of 530)having a floating body region(24)[0240], wherein an amount of charge stored in said floating body region(24) represents a state of said memory cell selected from at least first and second states (“0” and “1”)[0246-0247]; wherein current flow through said memory cell is larger when said memory cell is in one of said at least first and second states than when said memory cell (5)is in another of said at least first and second states[0246-0247]; and an access device(528 or 529)[0240]; wherein said state of said memory cell is maintained[0246];wherein said bipolar device(531 or 532 of 530) and said access device(528 or 529) are electrically connected in series fig. 49; and wherein said bipolar device(531 or 532 of 530) comprises a buried well region(23)[0240-0241].
Regarding claim 39, Widjaja et al discloses wherein said access device (528 or 529) comprises a metal-oxide-semiconductor transistor[0240].
Regarding claim 41, Widjaja et al discloses wherein said bipolar device (531 or 532 of 530) comprises at least two stable states(0 and 1)[0246-0247].
Regarding claim 43, Widjaja et al discloses wherein said bipolar device(531 or 532 of 530) comprises a gate region(60) [0240].
Regarding claim 44, Widjaja et al discloses A semiconductor memory array comprising a plurality of semiconductor memory cells arranged in a matrix of rows and columns(word line rows and bit line columns of array 81)(fig. 58)[0248], wherein each of said semiconductor memory cells (5)comprises: a bipolar device(531 or 532 of 530) having a floating body region(24)[0240], wherein an amount of charge stored in said floating body region(24) represents a state of said memory cell (5)selected from at least first and second states(0 and 1) [0246-0247];
wherein current flow through said memory cell (5)is larger when said memory cell is in one
of said at least first and second states than when said memory cell(5) is in another of said at least first and second states[0246-0247]; and an access device(528 or 529); wherein said state of said memory cell is maintained[0246-0247]; wherein said bipolar device (531 or 532 of 530) and said access device (528 or 529) are electrically connected in series fig. 49; and wherein said bipolar device (531 or 532 of 530) comprises a buried well region(23)[0240-0241].
Regarding claim 45, Widjaja et al discloses wherein said access device(528 or 529) comprises a metal-oxide-semiconductor transistor[0240].
.Regarding claim 47, Widjaja et al discloses wherein said bipolar device (531 or 532 of 530) comprises at least two stable states(0 and 1)[0246-0247].
Regarding claim 49, Widjaja et al discloses wherein said bipolar device(531 or 532 of 530) comprises a gate region(60) [0240].
Regarding claim 50, Widjaja et al discloses An integrated circuit comprising:
a semiconductor memory array comprising a plurality of semiconductor memory cells (5)arranged in a matrix of rows and columns(word line rows and bit line columns of array 81)(fig. 58)[0248], wherein each of said semiconductor memory cells (5)comprises: a bipolar device(531 or 532 of 530) having a floating body region(24)[0240], wherein an amount of charge stored in said floating body region represents a state of said memory cell (5)selected from at least first and second states (“0” and “1”) [0246-0247]; wherein current flow through said memory cell is larger when said memory cell(5) is in one of said at least first and second states than when said memory cell is in another of said at least first and second states[0246-0247]; and an access device(528 or 529)[0240]; wherein said state of said memory cell is maintained[0246-0247]; wherein said bipolar device (531 or 532 of 530) and said access device (528 or 529)are electrically connected in series fig. 49; and a sensing circuit(90)to read said state of said memory cell(5)[0249].
Regarding claim 51, Widjaja et al discloses wherein said access device(528 or 529) comprises a metal- oxide-semiconductor transistor[0240].
Regarding claim 53, Widjaja et al discloses wherein said bipolar device (531 or 532 of 530) comprises at least two stable states(0 and 1)[0246-0247].
Regarding claim 55, Widjaja et al discloses wherein said bipolar device(531 or 532 of 530) comprises a gate region(60) [0240].
Claim Rejections - 35 USC § 103
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 40,46, & 52 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Widjaja (US Pub no. 2014/0036577 A1) in view of Rao (US Pub no. 2011/0228594 A1)
Regarding claim 40, Widjaja et al discloses all the claim limitations of claim 38 but fails to teach wherein said access device comprises a bipolar transistor.
However, Rao et al discloses memory cells using bipolar transistor for controlling access [0037]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the access transistor of Widjaja et al with the bipolar access transistor of Rao et al the substitution of one known element for another yields predictable results to one of ordinary skill in the art. In re Fout, 675 F.2d 297, 213 USPQ 532 (CCPA 1982)
Regarding claim 46, Widjaja et al discloses all the claim limitations of claim 44 but fails to teach wherein said access device comprises a bipolar transistor.
However, Rao et al discloses memory cells using bipolar transistor for controlling access [0037]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the access transistor of Widjaja et al with the bipolar access transistor of Rao et al the substitution of one known element for another yields predictable results to one of ordinary skill in the art. In re Fout, 675 F.2d 297, 213 USPQ 532 (CCPA 1982)
Regarding claim 52, Widjaja et al discloses all the claim limitations of claim 50 but fails to teach wherein said access device comprises a bipolar transistor.
However, Rao et al discloses memory cells using bipolar transistor for controlling access [0037]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the access transistor of Widjaja et al with the bipolar access transistor of Rao et al the substitution of one known element for another yields predictable results to one of ordinary skill in the art. In re Fout, 675 F.2d 297, 213 USPQ 532 (CCPA 1982)
Claim 42,48, & 54 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Widjaja (US Pub no. 2014/0036577 A1) in view of Kakoschke (US Pub no 2009/0045467 A1)
Regarding claim 42, Widjaja et al discloses all the claim limitations of claim 38 but fails to teach wherein said semiconductor memory cells are formed in fin structures.
However, Kakoschke et al discloses finned bipolar transistors (100) incorporated in a memory cell[0021]. Since using a finned bipolar transistor is one of finite solutions to allow operations of small memory cell elements with a useful switching current as taught by Kakoschke et al , it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to try in Widjaja et al because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense (KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (U.S. 2007))
Regarding claim 48, Widjaja et al discloses all the claim limitations of claim 44 but fails to teach wherein said semiconductor memory cells are formed in fin structures.
However, Kakoschke et al discloses finned bipolar transistors (100) incorporated in a memory cell[0021]. Since using a finned bipolar transistor is one of finite solutions to allow operations of small memory cell elements with a useful switching current as taught by Kakoschke et al , it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to try in Widjaja et al because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense (KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (U.S. 2007))
Regarding claim 54, Widjaja et al discloses all the claim limitations of claim 50but fails to teach wherein said semiconductor memory cells are formed in fin structures.
However, Kakoschke et al discloses finned bipolar transistors (100) incorporated in a memory cell[0021]. Since using a finned bipolar transistor is one of finite solutions to allow operations of small memory cell elements with a useful switching current as taught by Kakoschke et al , it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to try in Widjaja et al because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense (KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (U.S. 2007))
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM.
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/LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
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