DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of 1-12 in the reply filed on 9/1/26 is acknowledged.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1,3-7,9,11,12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita et al., (Yamashita) US 2011/0039376 in view of Hoya US 2023/0420323.
Regarding claim 1, Yamashita discloses and shows in FIG. 2-4, an apparatus, comprising: a partitioned leadframe (2)[0066] including an inner leadframe portion (2h,2d)[0066,0067] and an outer leadframe portion (2e)[0090], the inner leadframe portion (2d) being at least partially surrounded by the outer leadframe portion (portion shown in FIG. 4, top view, surrounding chip 3) and being electrically isolated from the outer leadframe portion (portion of 2e); a first die (3)[0066] attached to the partitioned leadframe (2d); a second die (4)[0066] attached to the partitioned leadframe (2e); and a molding material (5) encapsulating the first die (3), the second die (4), and at least a portion of the partitioned leadframe.
Yamashita differs from the claimed invention because he does not explicitly disclose a device wherein the molding material being recessed between the inner leadframe portion and the outer leadframe portion so as to leave a cavity on a side of the partitioned leadframe opposite the first die.
Hoya discloses and shows in FIG. 15, a device wherein the molding material (42A, darker portion)[0080] being recessed (portion between 31d,32a) between the inner leadframe portion (31d)[0127] and the outer leadframe portion (32c)[0141] so as to leave a cavity (the recessed up shape) on a side of the partitioned leadframe opposite the first die (21).
Hoya is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Yamashita. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Hoya in the device of Yamashita because it will improve the heat dissipation while reducing the cost of a semiconductor module [0007].
Regarding claim 3, Yamashita, in view of Hoya discloses and shows in FIG. 2-4, an apparatus wherein the first die (3) and the second die (4) are both fabricated using a substrate of a same substrate material.
Regarding claim 4, Yamashita in view of Hoya discloses and shows in FIG. 2-4, an apparatus wherein: the first die (3) is attached to the inner leadframe portion (2d); the second die (4) is attached to the outer leadframe portion (2e); the apparatus further comprises a die interconnect (6)[0066] electrically connecting a top side of the first die (3) to a top side of the second die (4); and the molding material (5) further encapsulates the die interconnect (6)[0066].
Regarding claim 5, Yamashita in view of Hoya discloses and shows in FIG. 2-4, an apparatus wherein: the first die (3) is attached to the inner leadframe portion; the second die (4) is attached to the outer leadframe portion (2a); the apparatus further comprises a die interconnect (6)[0066] electrically connecting the inner leadframe portion to a top side of the second die (4); and a bottom side of the first die (3) is electrically connected to the inner leadframe portion (2d) and the molding material (5) further encapsulates the die interconnect (6)[0066].
Regarding claim 6, Yamashita in view of Hoya discloses and shows in FIG. 2-4, an apparatus wherein: the partitioned leadframe further includes a plurality of leads 2h,2a) arranged adjacent to the outer leadframe portion; and the apparatus further comprises a first die interconnect (6) electrically connecting the first die (3) to a first lead of the plurality of leads (2a) and a second die (4) interconnect electrically connecting the second die (4) to a second lead of the plurality of leads (2a).
Regarding claim 7, Yamashita in view of Hoya discloses and shows in FIG. 2-4, an apparatus wherein the cavity (formed by portion 41a) has a trapezoidal cross section between the inner leadframe portion and the outer leadframe portion.
Regarding claim 9, Yamashita in view of Hoya discloses and shows in FIG. 2-4, an apparatus comprising: A partitioned leadframe including an inner leadframe portion (2d) and an outer leadframe portion (2e), the inner leadframe portion (2d) being at least partially surrounded by the outer leadframe portion (portion and area shown in FIG. 4) and being and electrically isolated from the outer leadframe portion (2e); a first die (3) attached to the partitioned leadframe (2d); a second die (4) attached to the partitioned leadframe (2e); a molding (5) material encapsulating the first die, the second die, and at least a portion of the partitioned leadframe.
Yamashita differs from the claimed invention because he does not explicitly disclose a device having a first molding material filling at least a portion of a space between the inner leadframe portion and the outer leadframe portion.
Hoya discloses and shows in FIG. 15, a device having a first molding material (41A) filling at least a portion of a space between the inner leadframe portion (31d) and the outer leadframe portion (32c).
Hoya is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Yamashita. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Hoya in the device of Yamashita because it will improve the heat dissipation while reducing the cost of a semiconductor module [0007].
Regarding claim 11, Yamashita in view of Hoya discloses and shows in FIG. 2-4,
an apparatus wherein: the first die (3) is attached to the inner leadframe portion (2d); the second die (4) is attached to the outer leadframe portion (2e); the apparatus further comprises a die interconnect (6)[0066] electrically connecting the first die (3) to the second die (4); and the second molding material (5) further encapsulates the die interconnect.
Regarding claim 12, Yamashita in view of Hoya discloses and shows in FIG. 2-4, an apparatus wherein the first molding material (5) is different from the second molding material (molding 41A of Hoya).
Hoya is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Yamashita. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Hoya in the device of Yamashita because it will improve the heat dissipation while reducing the cost of a semiconductor module [0007].
Claim(s) 2,10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita in view of Hoya as applied to claims 1,3-7,9,11,12, and further in view of Osumi et al., (Osumi) US 2022/0068776.
Regarding claims 2,10, Yamashita in view of Hoya discloses an apparatus wherein the first die (3) is fabricated using a silicon substrate [0065].
Yamashita in view of Hoya differs from the claimed invention because he does not explicitly disclose that the second die is fabricated using a silicon carbide substrate.
Osumi discloses [0058,0059], a device wherein the second die is fabricated using a silicon carbide substrate.
Osumi is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Yamashita in view of Hoya. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Osumi in the device of Yamashita because it will help the device prevent electrical breakdown of the chip [0028].
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamashita in view of Hoya as applied to claims 1,3-7,9,11,12, and further in view of Beer et al., (Beer) US 2022/0102253.
Regarding claim 8, Yamashita in view of Hoya discloses a first die (3) and a second die (4); the first die (3) is attached to the inner leadframe portion (2d); and the second die (4) is attached to the outer leadframe portion (2e).
Yamashita in view of Hoya differs from the claimed invention because he does not explicitly disclose an apparatus that implements a discrete cascode circuit; implements a first transistor of the discrete cascode circuit; and implements a second transistor of the discrete cascode circuit.
Beer discloses [0051,0085] an apparatus that implements a discrete cascode circuit; implements a first transistor (in 11) of the discrete cascode circuit; and implements a second transistor (in 12) of the discrete cascode circuit [0051,0085].
Beer is evidence that ordinary workers skilled in the art would find reasons, suggestions or motivations to modify the device of Yamashita in view of Hoya. Therefore, at the time the invention was made; It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the teaching of Beer in the device of Yamashita because it will the thermal and electrical performance of the package [0094].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC-ANTHONY ARMAND whose telephone number is (571)272-5178. The examiner can normally be reached 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
MARC - ANTHONY ARMAND
Primary Examiner
Art Unit 2813
/MARC-ANTHONY ARMAND/Primary Examiner, Art Unit 2813
Prosecution Insights