DETAILED ACTION
This correspondence is in response to the communications received July 22, 2026. Claims 1-8, 10 and 11 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restrictions
Applicant’s election without traverse of Group I (structure claims) and Species II (“wherein an orthogonal projection of the second portion of the dummy patterns does not overlap an orthogonal projection of the bit line”) in the reply filed on July 22, 2026 is acknowledged. Claims 9 and 12-20 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Group II/Species I, there being no allowable generic or linking claim. Election was made without traverse in the reply filed.
Relevant Prior Art
Huang et al. (US 2023/0141463) Fig. 14A, shown below. “DSL dummy touch sensing lines”, ¶ 0050.
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Munetaka et al. (US 2023/0363148) Fig. 3A, shown below.
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Tsai et al. (US 2023/0118367 or US 11,876,048 – US Application 17/504546) Fig. 1A, shown below. “dummy structures DS”, ¶ 0019.
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Lee et al. (US 2017/0103993) Figs. 33-34, shown below. (prior art examiner used to reject above application…)
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Furuhashi (US 8,753,973) Fig. 20, 21 and 23, shown below. “a dummy memory cell structure DM1”, col. 6, lines 48-49.
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Fukano (US 8,437,170) Fig. 6 and 10, shown below.
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(Samsung) Park et al. (US 8,339,859) Fig. 3, shown below. “conductive dummy lines 316 … conductive dummy lines 326”, col. 10, lines 25-36.
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Futatsuyama et al. (US 7,700,997) Fig. 19, shown below. “dummy patterns 82”, col. 11, line 39.
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Okajima (US 9,093,642) Fig. 6A, shown below. “dummy wirings DL”, col. 4, line 23.
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Han et al. (US 2024/0138143) Fig. 10, shown below.
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Park et al. (US 2022/0189968, US 11,889,682) Fig. 8, shown below
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Park et al. (US 9,634,012) Fig. 20, shown below.
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Cheon et al. (US 2024/0196603) Figs. 2 and 7, shown below.
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Srivastava et al. (US 2023/0335581) Fig. 4G, shown below.
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Wang et al. (US 2023/0170224) Figs. 2 and 15, shown below.
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Chung et al. (US 2020/0111678) Fig. 3A and 6, shown below.
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Lee et al. (US 2019/0221669) Figs. 3,
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Kim et al. (US 2014/0327087) Figs. 1,
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Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, the Applicant discloses in Fig. 1G, a semiconductor structure having a central region (102a, ¶ 0014) and a periphery region (102b, ¶ 0014) surrounding the central region (discussed at least in ¶ 0014),
the semiconductor structure (100, ¶ 0014) comprising:
a plurality of target layer patterns (“target layer patterns are active areas 112”, ¶ 0020) formed in the central region (in 102a); and
a plurality of dummy patterns (“dummy active areas 114”, ¶ 0020) formed in the periphery region (in 102b), and all of the target layer patterns and the dummy patterns made from a target layer (“target layer 104”, ¶ 0020),
wherein the dummy patterns (114) comprise a first portion (114a) and a second portion (114b),
wherein an extending direction of the second portion is different from an extending direction of each of the target layer patterns (114b extend in different direction than 112, see Fig. 1G), and the first portion (114a) and the second portion (114b) extend in different directions (shown in Fig. 1G),
wherein the second portion of one of the dummy patterns (114a) is connected to one of the target layer patterns (112 by 116) or the first portion (114a connected to 114b).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 5 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Tomoyama (US 2016/0233297) in view of Li et al. (US 10,998,235).
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Regarding claim 1, the prior art of Tomoyama discloses in Figs. 2, 3, 4 and 7, a semiconductor structure (see title, “Semiconductor Device Having Shallow Trench Isolation Structure”, and “semiconductor device 1”, ¶ 0029) having a central region (“a rectangular active cell area AC”, ¶ 0016) and a periphery region (“The dummy cell area is composed of a first dummy cell area DC1 disposed along the first side 10Y and a second dummy cell area DC2”, ¶ 0016) surrounding the central region (“dummy cell area encircling the active cell area AC”, ¶ 0016),
the semiconductor structure (“semiconductor device 1”, ¶ 0029) comprising:
a plurality of target layer patterns (“cell active regions k1 and k2”, ¶ 0017) formed in the central region (k1 and k2 are formed in AC); and
a plurality of dummy patterns (“guard active regions GLa and GLb”, ¶ 0031, which are formed in DC1, “The dummy cell active regions 11a include no memory cell and therefore make no contribution to the operation of the semiconductor device 100 serving as the DRAM.”, ¶ 0019. The names are understood merely to be labels for non-functioning layers GLa and GLb, their non-functionality renders them as dummy structures which perform no electrical signal handling or transforming capacity. Therefore, as their purpose matches the function of “dummy”, they satisfy the term “dummy”, and can be considered dummy structures) formed in the periphery region (“dummy cell area encircling the active cell area AC”, ¶ 0016, thus if the dummy cell area encircles the active area, then the dummy cell area is thus on the periphery and of the periphery region, also shown in the figures), and all of the target layer patterns and the dummy patterns made from a target layer (All of GLa, GLb, k1 and k2 are formed from the semiconductor substrate as can be seen in the figures. Where “semiconductor substrate 2”, ¶ 0017 and each feature is a fin made from the semiconductor material substate, the “target layer” being the semiconductor substrate 2),
wherein the dummy patterns (GLa and GLb) comprise a first portion (GLa) and a second portion (GLb),
wherein an extending direction of the second portion is different from an extending direction of each of the target layer patterns (GLb extends horizontally in its longest dimension in Fig. 4, whereas k’s extend at a diagonal type direction in their longest dimension), and the first portion and the second portion extend in different directions (GLa extends vertically in Fig. 4, whereas GLb extends horizontally),
wherein the second portion of one of the dummy patterns is connected to one of the target layer patterns or the first portion (GLb is connected to GLa).
Tomoyama does not explicitly label the GLa and GLb regions as “dummy”, but since they are located in the “dummy cell area DC1”, ¶ 0016, it would have been obvious to one of ordinary skill in the art, that the structures in that region would be considered to be “dummy” as they are non-functioning structures.
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Fig. 1C, where “at least one dummy semiconductor fin 116 is formed on the substrate 110”, col. 3, lines 51-52.
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to utilize the “dummy patterns”, as disclosed by Li in the system of Tomoyama, for the purpose of utilizing non-functioning solid material serving no functional purpose for signal handling to be used in the region providing the function of protecting the inner active devices from externally originating stresses. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Regarding claim 2, the prior art of Tomoyama disclose the semiconductor structure of claim 1, wherein the target layer (102) is a substrate or a semiconductor material layer (“semiconductor substrate 2”, ¶ 0017), and an area of each of the dummy patterns (either of GLa or GLB) is greater than an area of each of the target layer patterns (in Fig. 4, it can be seen that either of GLa or GLb have greater area than any of the k).
Regarding claim 4, the prior art of Tomoyama disclose the semiconductor structure of claim 1, and Tomoyama discloses in Fig. 2, further comprising:
a bit line (Fig. 2, “bit lines BL”, ¶ 0024) extending in different directions than each of the target layer patterns (BL extend horizontally in Fig. 2, whereas K extend diagonally in Fig. 2),
wherein the first portion of one of the dummy patterns (GLb) extends in a same direction as each of the target layer patterns (in Fig. 2, GLb has portions which extend in the direction as plural k).
Regarding claim 5, the prior art of Tomoyama disclose the semiconductor structure of claim 1, and Tomoyama discloses, wherein an angle between the first portion and the second portion of the dummy patterns is not less than 20 degrees and is less than 180 degrees (k are oriented in what appears to be 30 degrees from GLb, and 60 degrees from GLa).
Regarding claim 11, the prior art of Tomoyama disclose the semiconductor structure of claim 1, and Tomoyama discloses, wherein an orthogonal projection of the second portion of the dummy patterns (GLb) does not overlap an orthogonal projection of the bit line (BL and GLb do not overlap, see Fig. 2).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Tomoyama (US 2016/0233297) in view of Li et al. (US 10,998,235) in view of Cheon et al. (US 2024/0196603).
Regarding claim 3, the prior art of Tomoyama disclose the semiconductor structure of claim 1, however Tomoyama is silent on, “wherein a width of the second portion is greater than a width of each of the target layer patterns.”
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Cheon discloses in Figs. 2 and 7, wherein a width of the second portion is greater than a width of each of the target layer patterns (the width of edge located semiconductor substrate patterns A2 are wider than the active region fins A1 made also from the semiconductor substrate, “a substrate 110 in which a plurality of cell active regions A1 and a peripheral circuit active region A2 are defined”, ¶ 0032, “the substrate 110 may include silicon”, ¶ 0033).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to utilize the “wherein a width of the second portion is greater than a width of each of the target layer patterns.”, as disclosed by Cheon in the system of Tomoyama, for the purpose of utilizing non-functioning solid material serving no functional purpose for signal handling to be used in the region providing the function of protecting the inner active devices from externally originating stresses. (G) Some teaching, suggestion, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention.
Allowable Subject Matter
Claims 6-8 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of Tomoyama (US 2016/0233297) disclose in Figs. 3 and 4, a similar device to that of the instant application, however Tomoyama does not disclose a plurality of second portions, which then cannot be compared in the manner as claimed (italicized portion below).
“6. The semiconductor structure of claim 1, wherein adjacent ones of the second portion of the dummy patterns are separated by a first distance, and the first portion of the dummy patterns are separated from an adjacent one of the target patterns by a second distance equal to the first distance.”
The prior art of Tomoyama (US 2016/0233297) disclose in Figs. 3 and 4, a similar device to that of the instant application, however Tomoyama does not disclose that the second portion of the dummy patterns is connected to the target layer patterns (italicized portion below).
“7. The semiconductor structure of claim 1, further comprising:
a bit line extending in different directions than each of the target layer patterns,
wherein the second portion of one of the dummy patterns is connected to the first portion and is not connected to the target layer patterns, and
an extending direction of the first portion is perpendicular to an extending direction of the bit line, wherein the second portion of another one of the dummy patterns is connected to the target layer patterns.”
Claim 8 is object to, due to its dependency upon claim 7.
“8. The semiconductor structure of claim 7, further comprising:
a plurality of contacts formed on each of the target layer patterns to electrically connect the target layer patterns to the bit line (“each bit line BL is formed on the surface of an interlayer dielectric film 10 made of a silicon nitride film covering the surface of the semiconductor substrate 2, and is connected to the diffusion layer D1 in the corresponding cell active region k via a bit line contact plug 12 penetrating the interlayer dielectric film 10”, ¶ 0025, see Fig. 7),
wherein the contacts are not formed on the first portion (12 not shown in DC1 where GLa is formed).”
The prior art of Tomoyama (US 2016/0233297) disclose in Figs. 3 and 4, a similar device to that of the instant application, however Tomoyama only shows where GLa is in contact with GLb, so does not show the limitation of claim 10.
“10. The semiconductor structure of claim 1, wherein adjacent ones of the dummy patterns are separated from each other.”
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eduardo A Rodela whose telephone number is (571)272-8797. The examiner can normally be reached M-F, 8:30-5:00pm ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara B Green can be reached on (571) 270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDUARDO A RODELA/Primary Examiner, Art Unit 2893
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