DETAILED ACTION
Claims 1-20 are pending before the Office for review.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 10-14 and 19-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by FU et al (CN 110730411 as evidenced by the machine translation).
With regards to claim 1, Fu discloses a manufacturing method of a micro electro mechanical system (MEMS) device, comprising: forming a buffer protection layer (120) on a semiconductor structure, wherein the semiconductor structure includes a wafer (100), a MEMS membrane (110), and an isolation layer (102) between the wafer (100) and the MEMS membrane (110), and the buffer protection layer (102) is located in a slit (111) of the MEMS membrane (110) and on a surface of the MEMS membrane facing away from the isolation layer (Pages 6-7 Figure 3); etching the wafer (100) to form a cavity (103) such that a portion of the isolation layer is exposed though the cavity (Page 8 Figure 6 first etching process); etching said portion of the isolation layer (102) (Page 8 Figure 6 second etching process); and removing the buffer protection layer (120) (Page 10 removing remaining sacrificial layer 120 Figure 11).
With regards to claim 2, Fu discloses wherein the buffer protection layer (120) is in direct contact with the MEMS membrane (110) (Pages 6-7 Figure 3).
With regards to claim 3, Fu discloses wherein the buffer protection layer (120) extends from the surface of the MEMS membrane (110) into the slit (111) of the MEMS membrane (110) (Pages 6-7 Figure 3).
With regards to claim 4, Fu discloses wherein the buffer protection layer (120) covers the entire surface of the MEMS membrane (110) (Pages 6-7 Figure 3).
With regards to claim 10, Fu discloses after etching said portion of the isolation layer (102) and before removing the buffer protection layer (120), attaching a surface of the wafer facing away from the isolation layer to an adhesive tape (150) (Pages 8-10 Figure 8 performing a second etching process on exposed etch stop layer 103 to form a second opening in the etch stop layer 102; a protective film 150 is attached to the surface of the first substrate 100 facing away from the supporting substrate 140; Figure 11 the remaining sacrificial layer 120 is subsequently removed).
With regards to claim 11, Fu discloses bonding the semiconductor structure to a carrier (140) by using a temporary bonding layer (130), such that the temporary bonding layer (130) is located between the buffer protection layer (120) and the carrier (140) (Page 7-8 Figure 4 S130).
With regards to claim 12, Fu discloses using a laser (160) to focus on an interface between the temporary bonding layer (130) and the carrier (140); removing the carrier (140); and removing the temporary bonding layer (130) (Pages 9-10 Figures 9-11).
With regards to claim 13, Fu discloses a manufacturing method of a micro electro mechanical system (MEMS) device, comprising: forming a buffer protection layer (120) on a semiconductor structure, wherein the semiconductor structure includes a wafer (100) and a MEMS membrane (110), and the buffer protection layer (102) is located in a slit (111) of the MEMS membrane (110) and a surface of the MEMS membrane facing away from the wafer (Pages 6-7 Figure 3); bonding the semiconductor structure to a carrier (140) by using a temporary bonding layer (130), such that the temporary bonding layer (130) is located between the buffer protection layer (120) and the carrier (140) (Page 7-8 Figure 4 S130); etching the wafer (100) to form a cavity (103) (Page 8 Figure 6 first etching process); removing the carrier (140); and removing the temporary bonding layer (130) (Pages 9-10 Figures 9-11); and removing the buffer protection layer (120) (Page 10 removing remaining sacrificial layer 120 Figure 11).
With regards to claim 14, Fu discloses wherein the buffer protection layer (120) is in direct contact with the MEMS membrane (110) (Pages 6-7 Figure 3).
With regards to claim 19, Fu discloses before removing the buffer protection layer (120), attaching a surface of the wafer facing away from the MEMS membrane to an adhesive tape (150) (Pages 8-10 Figure 8 performing a second etching process on exposed etch stop layer 103 to form a second opening in the etch stop layer 102; a protective film 150 is attached to the surface of the first substrate 100 facing away from the supporting substrate 140; Figure 11 the remaining sacrificial layer 120 is subsequently removed).
With regards to claim 20, Fu discloses using a laser (160) to focus on an interface between the temporary bonding layer (130) and the carrier (140) (Pages 9-10 Figures 9-11).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over FU et al (CN 110730411 as evidenced by the machine translation) in view of PIECHOCINSKI (U.S. Patent Application Publication 2020/0137501).
With regards to claim 5, Fu discloses the limitations of claim 1 as previously discussed.
However Fu does not explicitly disclose wherein the buffer protection layer is a polyimide film.
Piechocinski discloses a method of manufacturing a micro electro mechanical system (MEMS) device comprising depositing a sacrificial layer which may easily released wherein the sacrificial layer comprises a polyimide film which may fill bleed holes (Paragraphs [0058]-[0059], [0065]-[0066]). Fu discloses forming a sacrificial layer wherein the sacrificial layer fills the holes (Page 7). As such Fu as modified by Piechocinski renders obvious wherein the buffer protection layer (sacrificial layer) is a polyimide film (Piechocinski [0058]-[0059], [0065]-[0066]).
It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the invention to modify the method of Fu to include the polyimide film as rendered obvious by Piechocinski because the reference of Piechocinski teaches that polyimide is preferable as a sacrificial layer as it can be easily spun onto a substrate and easily removed with an oxygen plasma clean (Paragraph [0058]) and one of ordinary skill in the art prior to the effective filing date of the invention would have had a reasonable expectation of predictably achieving the desired MEMS manufacturing using the polyimide as rendered obvious by Piechocinski. MPEP 2143D
Claims 6 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over FU et al (CN 110730411 as evidenced by the machine translation) in view of CHENG et al (U.S. Patent Application Publication 2021/0179419).
With regards to claim 6, Fu discloses the limitations of claim 1 as previously discussed including performing a thinning process on the first substrate 100 (Page 8).
However Fu does not explicitly disclose grinding a surface of the wafer facing away from the isolation layer to reduce a thickness of the wafer.
Cheng discloses a method of manufacturing a micro electro mechanical system (MEMS) device comprising first matric material layer 10L made of a semiconductor material and a MEMS substrate 50 on the opposite side of the structure made to have a thickness wherein the matrix material layer 10L is thinned to matric material layer 10T by performing grinding, polishing, an isotropic etch process, an anisotropic etch process or a combination thereof (Paragraphs [0042]-[0050]). As such Fu as modified by Cheng renders obvious grinding a surface of the wafer facing away from the isolation layer to reduce a thickness of the wafer. (Fu Page 8, Cheng Paragraph [0050])
It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the invention to modify the method of Fu to include the grinding as rendered obvious by Cheng because one of ordinary skill in the art prior to the effective filing date of the invention would have had a reasonable expectation of predictably achieving the desired MEMS manufacturing using the grinding as rendered obvious by Cheng. MPEP 2143D
With regards to claim 15, Fu discloses the limitations of claim 13 as previously discussed including performing a thinning process on the first substrate 100 (Page 8).
However Fu does not explicitly grinding a surface of the wafer facing away from the MEMS membrane to reduce a thickness of the wafer.
Cheng discloses a method of manufacturing a micro electro mechanical system (MEMS) device comprising first matric material layer 10L made of a semiconductor material and a MEMS substrate 50 on the opposite side of the structure made to have a thickness wherein the matrix material layer 10L is thinned to matric material layer 10T by performing grinding, polishing, an isotropic etch process, an anisotropic etch process or a combination thereof (Paragraphs [0042]-[0050]). As such Fu as modified by Cheng renders obvious grinding a surface of the wafer facing away from the MEMS membrane to reduce a thickness of the wafer. (Fu Page 8, Cheng Paragraph [0050])
It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the invention to modify the method of Fu to include the grinding as rendered obvious by Cheng because one of ordinary skill in the art prior to the effective filing date of the invention would have had a reasonable expectation of predictably achieving the desired MEMS manufacturing using the grinding as rendered obvious by Cheng. MPEP 2143D
Claims 7-9 and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over FU et al (CN 110730411 as evidenced by the machine translation) in view of CHENG et al (U.S. Patent Application Publication 2021/0179419), as applied to claims 6 and 15, in further view of PIECHOCINSKI (U.S. Patent Application Publication 2020/0137501).
With regards to claim 7-9, Fu discloses the limitations of claim 1 as previously discussed.
However Fu does not explicitly disclose forming a patterned photoresist layer on the surface of the wafer; wherein etching the wafer to form the cavity further comprises: etching a portion of the wafer not covered by the photoresist layer and after etching the portion of the wafer not covered by the photoresist layer, removing the photoresist layer.
Piechocinski discloses a method of manufacturing a micro electro mechanical system (MEMS) device comprising etching from underneath the substrate up to the dielectric layer wherein the etching involves patterning the backside of the water with resist; this pattern is then transfer on the back of the wafer and subsequently removed (Paragraph [0076] Figures 15a-15c discloses etching 101 using a photoresist to form cavity 133 wherein the resist is not present in subsequent steps 15c). Fu discloses etching substrate 100 to forming opening 103 penetrating the first substrate 100 Page 8 Figure 6). As such Fu as modified by Piechocinski renders obvious forming a patterned photoresist layer on the surface of the wafer; wherein etching the wafer to form the cavity further comprises: etching a portion of the wafer not covered by the photoresist layer and after etching the portion of the wafer not covered by the photoresist layer, removing the photoresist layer.
It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the invention to modify the method of Fu to include the photoresist and etching as rendered obvious by Piechocinski because one of ordinary skill in the art prior to the effective filing date of the invention would have had a reasonable expectation of predictably achieving the desired MEMS manufacturing using the photoresist as rendered obvious by Piechocinski. MPEP 2143D
With regards to claims 16-18, Fu discloses the limitations of claim 13 as previously discussed.
However Fu does not explicitly disclose forming a patterned photoresist layer on the surface of the wafer; wherein etching the wafer to form the cavity further comprises: etching a portion of the wafer not covered by the photoresist layer and after etching the portion of the wafer not covered by the photoresist layer, removing the photoresist layer.
Piechocinski discloses a method of manufacturing a micro electro mechanical system (MEMS) device comprising etching from underneath the substrate up to the dielectric layer wherein the etching involves patterning the backside of the water with resist; this pattern is then transfer on the back of the wafer and subsequently removed (Paragraph [0076] Figures 15a-15c discloses etching 101 using a photoresist to form cavity 133 wherein the resist is not present in subsequent steps 15c). Fu discloses etching substrate 100 to forming opening 103 penetrating the first substrate 100 Page 8 Figure 6). As such Fu as modified by Piechocinski renders obvious forming a patterned photoresist layer on the surface of the wafer; wherein etching the wafer to form the cavity further comprises: etching a portion of the wafer not covered by the photoresist layer and after etching the portion of the wafer not covered by the photoresist layer, removing the photoresist layer.
It would have been prima facie obvious to one of ordinary skill in the art prior to the effective filing date of the invention to modify the method of Fu to include the photoresist and etching as rendered obvious by Piechocinski because one of ordinary skill in the art prior to the effective filing date of the invention would have had a reasonable expectation of predictably achieving the desired MEMS manufacturing using the photoresist as rendered obvious by Piechocinski. MPEP 2143D
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHANIE P. DUCLAIR whose telephone number is (571)270-5502. The examiner can normally be reached 9-6:30 M-F.
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/STEPHANIE P DUCLAIR/Primary Examiner, Art Unit 1713
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