DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 7, 8, 14, 15, 24, and 25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Granahan (US PG Pub 2015/0348784)
Regarding claim 1, figure 4 of Granahan discloses a method of making a semiconductor device, comprising:
providing a substrate (402);
forming a semiconductor layer (404) having a first conductivity type (¶ 30) over the substrate;
forming a trench (406) through the semiconductor layer;
forming an epitaxial layer (408) having a second conductivity type (¶ 35) opposite the first conductivity type over a surface of the semiconductor layer and a side surface of the trench; and
diffusing the epitaxial layer into the semiconductor layer (¶ 36) to form a first column (410) of semiconductor material having the second conductivity type within the semiconductor layer (404).
Regarding claim 2, figure 4 of Granahan discloses retaining a portion of the semiconductor layer (404) as a second column of semiconductor material having the first conductivity type adjacent to the first column (410) of semiconductor material.
Regarding claim 3, figure 4 of Granahan discloses
Regarding claim 7, figure 4 of Granahan discloses a method of making a semiconductor device, comprising:
providing a substrate (402);
forming a semiconductor layer (404) over the substrate;
forming a trench (406) through the semiconductor layer;
forming an epitaxial layer (408) over a surface of the semiconductor layer and a side surface of the trench; and
diffusing the epitaxial layer into the semiconductor layer (¶ 36) to form a first column (410) of semiconductor material within the semiconductor layer (404).
Regarding claim 8, figure 4 of Granahan discloses the semiconductor layer (404) has a first conductivity type and diffusing the epitaxial layer (408) forms a first column (410) of semiconductor material having a second conductivity type opposite the first conductivity type with a remaining portion of the semiconductor layer providing a second column of semiconductor material having the first conductivity type adjacent to the first column of semiconductor material.
Regarding claim 14, figure 4 of Granahan discloses a semiconductor device, comprising:
a substrate (402);
a semiconductor layer (404) formed over the substrate;
a trench (406) formed through the semiconductor layer; and
an epitaxial layer (408) formed over a surface of the semiconductor layer and a side surface of the trench and diffused into the semiconductor layer (¶ 36).
Regarding claim 15, figure 4 of Granahan discloses the semiconductor layer (404) has a first conductivity type and diffusing the epitaxial layer (408) forms a first column of semiconductor material having a second conductivity type opposite the first conductivity type within the semiconductor layer with a remaining portion of the semiconductor layer providing a second column of semiconductor material having the first conductivity type adjacent to the first column of semiconductor material.
Regarding claim 24, figure 4 of Granahan discloses a method of making a semiconductor device, comprising:
providing a substrate (402);
forming a semiconductor layer (404) over the substrate;
forming a trench (406) through the semiconductor layer;
forming an epitaxial layer (408) over a surface of the semiconductor layer and a side surface of the trench using atomic layer deposition (¶ 35); and
diffusing the epitaxial layer into the semiconductor layer (¶ 36) to form a first column (410) of semiconductor material within the semiconductor layer (404).
Regarding claim 25, figure 4 of Granahan discloses the semiconductor layer (404) has a first conductivity type and diffusing the epitaxial layer (408) forms a first column of semiconductor material having a second conductivity type opposite the first conductivity type with a remaining portion of the semiconductor layer providing a second column of semiconductor material having the first conductivity type adjacent to the first column of semiconductor material.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4, 9-10, 13, 16-18, 20-23, 26-27, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Granahan in view of OSUMI et al. (US PG Pub 2024/0153944, hereinafter Osumi).
Regarding claims 3, 4, 9, 10, 16, 17, 26, and 27, Granahan does not explicitly disclose forming a first insulating layer over the side surface of the trench (406);
forming a body region within the semiconductor layer (404) from the epitaxial layer (408) diffused into the semiconductor layer;
forming a source region within the body region;
forming a gate region within the body region;
forming a second insulating layer over the trench;
forming a third insulating layer over the second insulating layer;
forming a conductive via through the third insulating layer to the source region; and
forming a conductive layer over the third insulating layer in electrical contact with the conductive via.
In the same field of endeavor, figure 11 of Osumi discloses forming a first insulating layer (86A) over the side surface of a trench;
forming a body region (80) within a semiconductor layer;
forming a source region (90) within the body region;
forming a gate region (82) within the body region;
forming a second insulating layer (85A) over the trench;
forming a third insulating layer (30) over the second insulating layer;
forming a conductive via (203) through the third insulating layer to the source region; and
forming a conductive layer (33) over the third insulating layer in electrical contact with the conductive via.
In light of such teachings, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the claimed layers in the device of Granahan as taught by Osumi for the purpose of forming a complete trench gate device (see ¶2 of Granahan).
Regarding claims 13, 20, and 30, Granahan does not explicitly disclose the trench is 0.5 micrometers or less in width.
However, it would have been obvious to form the trench with a width within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 18, Granahan does not explicitly disclose the trench extends to the substrate.
However, it would have been obvious to form the trench with a depth within a range that extends to the subtrate, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claims 21-23, Granahan does not explicitly disclose the semiconductor layer (404) is doped using atomic layer deposition.
However, ALD is well known in the art and it would have been obvious to dope the semiconductor layer using ALD for the purpose of selecting a suitable and well-known process for doping the layer.
Allowable Subject Matter
Claims 5-6, 11-12, 19 and 28-29 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU-HSI DAVID SUN whose telephone number is (571)270-5773. The examiner can normally be reached Mon-Fri 8am-4pm ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/YU-HSI D SUN/ Primary Examiner, Art Unit 2817
Prosecution Insights