DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
2. This Non-Final office action is in response to application 18/623,050, application filed on 04/01/2024. Claims 1-16 are currently pending in this application.
Priority
3. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 04/01/2024 and 08/05/2024, respectively, is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claim(s) 1-4, 7-12 and 15-16 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by KIM et al. (US PG Pub No. 2021/0004514).
7. With respect to independent claims 1 and 9, KIM teaches:
performing a static timing analysis (STA) (static timing analysis, para 17) on a circuit model under test (synthesis and design for test, para 29) to select a plurality of selected signal paths violating timing constraints from the circuit model under test (static timing analysis performed on a plurality of paths, para 17; see STA analysis on critical paths where critical paths violate design rules for process conditions, para 37-39);
obtaining a plurality of timing information of each of the plurality of selected signal paths under a plurality of operating conditions (for path violations, determining hold/setup violation, under certain PVT process conditions, process corner change, timing information, para 37-39, 44-45); and
selecting a plurality of selected timing information from the plurality of timing information according to a first threshold (selecting PVT corner information for timing critical paths after STA analysis, para 4, 8, 52; see PVT corners exceeding a first threshold, para 55), and
calculating a timing reference value corresponding to each of the plurality of operating conditions according to the plurality of selected timing information (see determining whether PVT corner information is less than reference values D1, D2, para 43).
8. With respect to claims 2 and 10, KIM teaches:
setting the circuit model under test under each of the plurality of operating conditions to perform the static timing analysis (see analysis when PVT conditions are changed from one corner to another, and for different process conditions, para 42);
according to the first threshold, selecting signal paths to be recorded violating the timing constraints under each of the plurality of operating conditions from the circuit model under test; and combining the signal paths to be recorded under each of the plurality of operating conditions into the plurality of selected signal paths (selecting signal paths based on criteria for critical paths and timing violations by selecting PVT corner information for timing critical paths after STA analysis, para 4, 8, 52; see PVT corners exceeding a first threshold, para 55).
9. With respect to claims 3 and 11, KIM teaches:
for each of the plurality of selected signal paths, determining a plurality of timing slack values violating the timing constraints under the plurality of operating conditions as the plurality of timing information (see obtaining hold and setup slack values, para 15; see minimum and maximum extreme hold sensitivity values, para 55); and
for each of the plurality of selected signal paths, selecting a minimum slack value from the plurality of corresponding timing slack values as the selected timing information (see extreme minimum or maximum slack path and slack value, para 55).
10. With respect to claims 4 and 12, KIM teaches:
for each of the plurality of operating conditions, calculating a proportion value of the plurality of minimum slack values corresponding to the plurality of operating conditions relative to all the minimum slack values as each of the plurality of timing reference values (see extreme minimum or maximum slack path and slack value with respect to slowest and fastest delta delays and PVT operation condition process corners, para 55-56).
11. With respect to claims 7 and 15, KIM teaches:
according to the plurality of timing reference values, selecting at least one selected operating condition from the plurality of operating conditions, wherein a sum of at least one timing reference value corresponding to the at least one selected operating condition is greater than or equal to a second threshold (see sum of data path delays, rate of change from one PVT corner to another, exceeding a threshold, para 55-56).
12. With respect to claims 8 and 16, KIM teaches:
correcting the plurality of selected signal paths in the circuit model under test (see correcting chip design, para 38; correcting clock paths with slack sensitivity analysis, para 59; timing paths corrected, para 61), and
setting the corrected circuit model under test under the at least one selected operating condition to perform the static timing analysis (static timing analysis performed on a plurality of paths, para 17; see STA analysis on critical paths where critical paths violate design rules for process conditions, para 37-39).
Allowable Subject Matter
13. Claims 5-6 and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
14. With respect to claims 5 and 13, the prior art made of record fails to teach the combination of steps recited in claims 5 and 13, including the following particular combination of steps as recited in claim 5 and similarly recited in claim 13, as follows:
wherein calculating each of the plurality of timing reference values comprises:
for each of the plurality of operating conditions, calculating a ratio of a number of the plurality of minimum slack values corresponding to each of the plurality of operating conditions divided by a total number of all the plurality of minimum slack values, and using the ratio as each of the plurality of timing reference values.
15. With respect to claims 6 and 14, the prior art made of record fails to teach the combination of steps recited in claims 6 and 14, including the following particular combination of steps as recited in claim 6 and similarly recited in claim 14, as follows:
wherein calculating each of the plurality of timing reference values comprises:
for each of the plurality of operating conditions, calculating a ratio of a sum of the plurality of minimum slack values corresponding to each of the plurality of operating conditions divided by a sum of all the plurality of minimum slack values, and using the ratio as each of the plurality of timing reference values.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUCHIN PARIHAR whose telephone number is (703)756-1970. The examiner can normally be reached on M-F 8am-5pm.
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/SUCHIN PARIHAR/
Primary Examiner, Art Unit 2851
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