DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of claims 11-20 in the reply filed on 07/01/2026 is acknowledged. The traversal is on the ground(s) that “The process claims (claims 1-10) are directed to a process for making the presently claimed semiconductor device and correspond to the product invention as claimed in claims 11-20”. This is not found persuasive because per MPEP 806.05, “A process of making and a product made by the process can be shown to be distinct inventions if either or both of the following can be shown: (A) that the process as claimed is not an obvious process of making the product and the process as claimed can be used to make another materially different product; or (B) that the product as claimed can be made by another materially different process” the examiner has given materially different processes for making such a device in the restriction requirement sent on 05/06/2026.
The requirement is still deemed proper and is therefore made FINAL. Please note: “Where applicant elects claims directed to the product/apparatus, and all product/apparatus claims are subsequently found allowable, withdrawn process claims that include all the limitations of the allowable product/apparatus claims should be considered for rejoinder. All claims directed to a nonelected process invention must include all the limitations of an allowable product/apparatus claim for that process invention to be rejoined.” Per MPEP 806.05.
Claims 11-20 are examined in the action below.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 04/01/2024 is being considered by the examiner.
Drawings
The drawings submitted on 04/01/2024 are being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 11-15, 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US 20220376071 A1) in view of Chen et al. (US 20150372099 A1).
Regarding claim 11, Tsai discloses a semiconductor device, comprising:
a semiconductor substrate (10); ([0017], Fig. 1)
a gate structure (GS1) disposed on the semiconductor substrate (10); ([0019], Fig. 1)
a gate oxide layer (22) disposed between the gate structure (GS1) and the semiconductor substrate (10) in a vertical direction; (22)
a spacer structure (S1) disposed on a sidewall of the gate structure (GS1); and
a nickel silicide layer (S2) disposed in the semiconductor substrate (10), wherein a part of the nickel silicide layer (52) is located under the spacer structure (S1) in the vertical direction. ([0019], Fig. 1)
Tsai does not disclose:
and a length of the part of the nickel silicide layer in a horizontal direction is greater than or equal to 4 nanometers and less than or equal to 5 nanometers.
However, Chen discloses:
and a length of the part of the nickel silicide layer (270) in a horizontal direction is greater than or equal to 4 nanometers and less than or equal to 5 nanometers (per [0033]). (Fig. 8)
It would have been obvious to one skilled in the art before the effective filing date to combine ethe teachings of Tsai and Chen for a length of the part of the nickel silicide layer in a horizontal direction is greater than or equal to 4 nanometers and less than or equal to 5 nanometers in order to “prevent leakage and may increase a stress voltage tolerance for a contact to be formed on the silicide” (Chen , [0033])
Regarding claim 12, Tsai discloses the semiconductor device according to claim 11, wherein a sidewall (SW) of the gate oxide layer (22) comprises a C-shaped structure (per [0017]) in a cross-sectional diagram of the semiconductor device. (Fig. 1)
Regarding claim 13, Tsai discloses the semiconductor device according to claim 12, wherein the sidewall (SW) of the gate oxide layer (22) is located between the spacer structure (S1) and the semiconductor substrate (10) in the vertical direction. (Fig. 1)
Regarding claim 14, Tsai discloses the semiconductor device according to claim 11, wherein a part of the nickel silicide layer (52) is located under a sidewall (SW) of the gate oxide layer (22) in the vertical direction. (Fig. 1)
Regarding claim 15, Tsai discloses the semiconductor device according to claim11, wherein a sidewall (SW) of the gate oxide layer (22) is a concave structure (per [0023]). (Fig. 1)
Regarding claim 18, Tsai discloses the semiconductor device according to claim 11, wherein a part of the nickel silicide layer (52) is located under the gate oxide layer (22) in the vertical direction,
Tsai does not explicitly disclose:
and a length of the part of the nickel silicide layer located under the gate oxide layer in the horizontal direction is greater than or equal to 4 nanometers and less than or equal to 5 nanometers.
However, Chen discloses:
And a length of the part of the nickel silicide layer (270) located under the gate oxide layer (140) in the horizontal direction is greater than or equal to 4 nanometers and less than or equal to 5 nanometers (per [0033]). (Fig. 7)
It would have been obvious to one skilled in the art before the effective filing date to arrive at the claimed invention for similar reasons as mentioned beforehand.
Regarding claim 19, Tsai discloses the semiconductor device according to claim 11, wherein a distance (DS1) between the nickel silicide layer (52) and the gate structure (GS1) in the horizontal direction (Fig. 1)
Tsai does not explicitly disclose:
is greater than 21 nanometers.
However, Tsai discloses
“enlarging a distance (such as a distance DS1 shown in FIG. 1) between the first metal silicide layer 52 and the first gate structure GS1 in the horizontal direction (such as the second direction D2), the electrical field distribution between the first metal silicide layer 52 and the first gate structure GS1 may be changed, and the leakage current (Ioff) of the first transistor structure T1 may be reduced accordingly” per [0023])
Therefore, it would have been obvious to one skilled in the art before the effective filing date to us ethe teachings of Tsai for a distance between the nickel silicide layer and the gate structure in the horizontal direction is greater than 21 nanometers in order to achieve “the purpose of reducing the leakage current of the first transistor structure T1.” (Tsai, [0040]).
Claims 16 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US 20220376071 A1) in view of Chen et al. (US 20150372099 A1) as applied to claim 11 above, and further in view of Yamamoto et al. (US 20070072382 A1).
Regarding claim 16, Tsai discloses in view of Chen disclose the semiconductor device according to claim 11. Tsai in view of Chen do not disclose wherein a fluorine concentration within a region located in the semiconductor substrate and adjacent to the nickel silicide layer is greater than or equal to 2.5 atomic percent (at%) and less than or equal to 4.5 atomic percent.
However, Yamamoto discloses:
a fluorine concentration within a region (14) located in the semiconductor substrate (2) and adjacent to the nickel silicide layer (18), ([0064], Fig. 4)
Yamamoto does not explicitly disclose:
is greater than or equal to 2.5 atomic percent (at%) and less than or equal to 4.5 atomic percent.
However, Yamamoto does disclose:
“a technology for forming a steep concentration profile in the extension region 14 in the transverse direction by using a diffusion-suppressing substance such as nitrogen or fluorine for suppressing the diffusion of impurity. This technology is to steepen the concentration profile of impurity in the transverse direction by suppressing the diffusion of impurity in the transverse direction by adding the diffusion-suppressing substance in the annealing treatment by using the rapid thermal annealing system. In this embodiment, likewise, the diffusion-suppressing substance is introduced into the source/drain diffusion layer 22 to suppress the diffusion of impurity in the extension region 14 and to steepen the concentration profile in the transverse direction.” In [0068])
Therefore, it would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Tsai, Chen and Yamamoto for a fluorine concentration within a region located in the semiconductor substrate and adjacent to the nickel silicide layer is greater than or equal to 2.5 atomic percent (at%) and less than or equal to 4.5 atomic percent in order to “make it possible to shorten the overlapping length Lov and, hence, to shorten the physical gate length Lg1 yet maintaining the effective gate length Lg2 as long as possible. The second feature of this embodiment makes it possible to decrease chiefly the resistance Rov among the source/drain parasitic resistances.” (Yamamoto, [0068])
Regarding claim 17, Yamamoto discloses the semiconductor device according to claim 16, wherein the fluorine concentration within the region (14) located in the semiconductor substrate (2) and adjacent to the nickel silicide layer (18), ([0064], Fig. 4)
Yamamoto does not explicitly disclose:
is greater than or equal to 3 atomic percent and less than or equal to 4 atomic percent.
However, Yamamoto does disclose:
“a technology for forming a steep concentration profile in the extension region 14 in the transverse direction by using a diffusion-suppressing substance such as nitrogen or fluorine for suppressing the diffusion of impurity. This technology is to steepen the concentration profile of impurity in the transverse direction by suppressing the diffusion of impurity in the transverse direction by adding the diffusion-suppressing substance in the annealing treatment by using the rapid thermal annealing system. In this embodiment, likewise, the diffusion-suppressing substance is introduced into the source/drain diffusion layer 22 to suppress the diffusion of impurity in the extension region 14 and to steepen the concentration profile in the transverse direction.” In [0068])
Therefore, it would have been obvious to one skilled in the art before the effective filing date to use the teachings of Yamamoto to arrive at the claimed invention for similar reasons mentioned beforehand.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai et al. (US 20220376071 A1) as applied to claim 11 above, and further in view of Luo et al. (US 20120267706 A1).
Regarding claim 20, Tsai discloses the semiconductor device according to claim 11, further comprising:
a source/drain doped region (42) disposed in the semiconductor substrate (10) and located under the nickel silicide layer (52), ([0017], Fig. 1)
Tsai does not disclose:
wherein a distance between the source/drain doped region and the gate structure in the horizontal direction is greater than a distance between the nickel silicide layer and the gate structure in the horizontal direction.
However, Luo discloses:
a distance between the source/drain doped region (104) and the gate structure (110+109) in the horizontal direction is greater than a distance between the nickel silicide layer (106) and the gate structure (110+109) in the horizontal direction. ([0039], Fig. 9)
It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Tsai and Luo for a distance between the source/drain doped region and the gate structure in the horizontal direction is greater than a distance between the nickel silicide layer and the gate structure in the horizontal direction in order to “decrease the contact resistivity as well as the parasitic source/drain series resistance” (Luo, [0005])
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600.
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/ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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