DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I in the reply filed on July 20, 2026, is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Upon reconsideration, Examiner is of the opinion that the requirement for the Species restriction, starting on page 4, of the Requirement for Restriction/Election mailed May 18, 2026 was improper. The requirement for Species restriction is withdrawn but the restriction for inventions remains.
Claim Objections
Claim 1 is objected to because of the following informalities:
Line 11 the word “an” should be “a,” such that the line reads “performing a drive-in process”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-8 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 6, line 5 claims “forming a third dipole film on the first gate dielectric.” This would result in two dipole films (first and third) on the first gate dielectric and no dipole film on the third gate dielectric formed in line 4. Further, lines 7-8 claim the additional dopants from the third dipole film are driven into the third gate dielectric. For purposes of Examination, Examiner will interpret the claim to mean “forming a third dipole film on the third gate dielectric.”
Claims 7-8 would also be rejected because they are dependent on claim 6.
Regarding claim 7, Lines 15-17 claim a lower portion of the gate electrode is associated with the first transistor and an upper portion of the gate is electrode is associated with the second transistor. Claim 6 claims a third semiconductor channel region and first semiconductor channel region are at a same height and provide steps similar to that for forming the first transistor. While a third transistor is not claimed, line 2 of claim 7 reciting, “parts of upper transistors,” implies a third transistor is formed at the same level as the first transistor. However, the first transistor was already placed at a lower portion in claim 1. For purposes of examination, Examiner will interpret the first semiconductor channel region and third semiconductor region to be parts of lower transistors in CFET structures.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 9-10, and 21-27 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Thomas et. al. (US 20220199620 A1), hereinafter Thomas.
Regarding claim 1, Thomas teaches a method ([0053]) comprising: forming (Fig 4B block 420, [0054]) a first semiconductor channel region (Fig 2B channel region 115A, [0034]) and a second semiconductor channel region (Fig 2B channel region 115B, [0034]), wherein the second semiconductor channel region (Fig 2B channel region 115B, [0034]) overlaps the first semiconductor channel region (Fig 2B channel region 115A, [0034]); forming (Fig 4B block 470, [0058]) a first gate dielectric (Fig 5 high-k material 315, [0066]) on the first semiconductor channel region (Fig 5 channel region 215A, [0066]); forming (Fig 4B block 470, [0058]) a second gate dielectric (Fig 5 high-k material 315, [0066]) on the second semiconductor channel region (Fig 5 channel region 215B, [0066]); forming (Fig 4B block 470, [0058]) a first dipole film (Fig 5 Vt shifter source material 515, [0066]) on the first gate dielectric (Fig 5 high-k material 315, [0066]), wherein the first dipole film (Fig 5 Vt shifter source material 515, [0066]) comprises a first dipole dopant (Fig 5 dopant within Vt shifter source material 515, [0066]) of a first type (list for PMOS, [0047]); forming (Fig 4B block 470, [0058]) a second dipole film (Fig 5 Vt shifter source material 516, [0067]) on the second gate dielectric (Fig 5 high-k material 315, [0066]), wherein the second dipole film (Fig 5 Vt shifter source material 516, [0067]) comprises a second dipole dopant (Fig 5 dopant within Vt shifter source material 516, [0067]) of a second type (list for NMOS, [0047]) opposite to the first type (list for PMOS, [0047]); performing an drive-in process (Fig 4B block 480, [0061]) to drive dipole dopants in the first dipole film (Fig 5 Vt shifter source material 515, [0066]) and the second dipole film (Fig 5 Vt shifter source material 516, [0067]) into the first gate dielectric (Fig 5 high-k material 315, [0066]) and the second gate dielectric (Fig 5 high-k material 315, [0066]), respectively; removing (Fig 4B block 490, [0062]) the first dipole film (Fig 5 Vt shifter source material 515, [0066]) and the second dipole film (Fig 5 Vt shifter source material 516, [0067]); and forming (Fig 4B block 495, [0063]) a gate electrode on both of the first gate dielectric (Fig 5 high-k material 315, [0066]) and the second gate dielectric (Fig 5 high-k material 315, [0066]), wherein the first gate dielectric (Fig 5 high-k material 315, [0066]) and a lower portion of the gate electrode (Fig 5 metal 510A, [0068]) are comprised in a first transistor (Fig 5 transistor 151, [0025]), and the second gate dielectric (Fig 5 high-k material 315, [0066]) and an upper portion of the gate electrode (Fig 5 metal 510B, [0068]) are comprised in a second transistor (Fig 5 transistor 152, [0025]).
Regarding claim 2, Thomas teaches work function layers (Fig 2B not shown; a gate fill metal may be over the work function metal, [0038]) in the gate electrode (Fig 2B gate electrode 110, [0038]) have a mid-gap work function (gate electrode may include a mid-gap work function, [0038]), and wherein the first transistor (Fig 1 transistor 151, [0026]) and the second transistor (Fig 1 transistor 152, [0026]) comprise an n-type transistor (transistors 151 and 152 may be either n-type or p-type transistors, [0026]) and a p-type transistor (transistors 151 and 152 may be either n-type or p-type transistors, [0026]).
Regarding claim 3, Thomas teaches the first transistor (Fig 1 transistor 151, [0026]) is the p-type transistor (transistors 151 and 152 may be either n-type or p-type transistors, [0026]), and the second transistor (Fig 1 transistor 152, [0026]) is the n-type transistor (transistors 151 and 152 may be either n-type or p-type transistors, [0026]).
Regarding claim 4, Thomas teaches the first transistor (Fig 1 transistor 151, [0026]) is the n-type transistor (transistors 151 and 152 may be either n-type or p-type transistors, [0026]), and the second transistor (Fig 1 transistor 152, [0026]) is the p-type transistor (transistors 151 and 152 may be either n-type or p-type transistors, [0026]).
Regarding claim 5, Thomas teaches forming ([0056]) a first source/drain region (Fig 1 source and drain regions 106, [0026]) aside the first semiconductor channel region (Fig 5 channel region 215A, [0066]); and forming ([0056]) a second source/drain region (Fig 1 source and drain regions 106, [0026]) aside the second semiconductor channel region (Fig 5 channel region 215B, [0066]), wherein the second source/drain region (Fig 1 source and drain regions 106, [0026]) overlaps (the source and drain materials may be grown as separate crystals, [0056]) the first source/drain region (Fig 1 source and drain regions 106, [0026]).
Regarding claim 9, Thomas teaches the forming (Fig 4B block 470, [0058]) the first dipole film (Fig 5 Vt shifter source material 515, [0066]) and the second dipole film (Fig 5 Vt shifter source material 516, [0067]) comprises: depositing (Fig 5 operation 505, [0066]) the first dipole film (Fig 5 Vt shifter source material 515, [0066]) on both of the first gate dielectric (Fig 5 high-k material 315, [0066]) and the second gate dielectric (Fig 5 high-k material 315, [0066]); removing (Fig 5 operation 518, [0067]) the first dipole film (Fig 5 Vt shifter source material 515, [0066]) from the second gate dielectric (Fig 5 high-k material 315, [0066]); and forming (Fig 5 operation 522, [0067]) the second dipole film (Fig 5 Vt shifter source material 516, [0067]) on the second gate dielectric (Fig 5 high-k material 315, [0066]).
Regarding claim 10, Thomas teaches after the first dipole film (Fig 5 Vt shifter source material 515, [0066]) is deposited (Fig 5 operation 505, [0066]), forming (Fig 5 operation 510, [0066]) a sacrificial layer (dielectric material 520, [0066]); recessing ([0066]) the sacrificial layer (dielectric material 520, [0066]) to a level lower than ([0066]) the second gate dielectric (Fig 5 high-k material 315, [0066]), wherein the first dipole film (Fig 5 Vt shifter source material 515, [0066]) is removed from (Fig 5 operation 518, [0067]) the second gate dielectric (Fig 5 high-k material 315, [0066]) after the recessing ([0066]), and the second dipole film (Fig 5 Vt shifter source material 516, [0067]) is deposited (Fig 5 operation 522, [0067]) after the first dipole film (Fig 5 Vt shifter source material 515, [0066]) is removed from (Fig 5 operation 518, [0067]) the second gate dielectric (Fig 5 high-k material 315, [0066]); and removing ([0067]) the sacrificial layer (dielectric material 520, [0066]).
Regarding claim 21, Thomas teaches a method ([0053]) comprising: forming ([0053]) a lower transistor (Fig 5 transistor 151, [0025]) comprising: a first gate dielectric (Fig 5 high-k material 315, [0066]) on the first semiconductor channel region (Fig 5 channel region 215A, [0034]); and a first part (Fig 5 work function metal 510A, [0068]) of a gate electrode (Fig 1 gate electrode 110, [0068]) on the first gate dielectric (Fig 5 high-k material 315, [0066]); and forming ([0053]) an upper transistor (Fig 5 transistor 152, [0025]), wherein the lower transistor (Fig 5 transistor 151, [0025]) and the upper transistor (Fig 5 transistor 152, [0025]) comprise an n-type transistor (transistors 151 and 152 may be either n-type or p-type transistors, [0026]) and a p-type transistor (transistors 151 and 152 may be either n-type or p-type transistors, [0026]), and wherein the upper transistor (Fig 5 transistor 152, [0025]) comprises: a second semiconductor channel region (Fig 2B channel region 115B, [0034]) overlapping the first semiconductor channel region (Fig 2B channel region 115A, [0034]);a second gate dielectric (Fig 5 high-k material 315, [0066]) on the second semiconductor channel region (Fig 5 channel region 215B, [0066]); and a second part (Fig 5 work function metal 510B, [0068]) of the gate electrode (Fig 1 gate electrode 110, [0068]) on the second gate dielectric (Fig 5 high-k material 315, [0066]), wherein the first part (Fig 5 work function metal 510A, [0068]) and the second part are parts (Fig 5 work function metal 510B, [0068]) of a continuous gate electrode (Fig 1 gate electrode 110, [0068]) that are formed through a same deposition process (Fig 5 operation 530, [0068]; the metals for 510A and 10B may each be any of the metals described for gate electrode 110; so they can be the same).
Regarding claim 22, Thomas teaches both of the first part (Fig 5 work function metal 510A, [0068]) and the second part (Fig 5 work function metal 510B, [0068]) of the gate electrode (Fig 1 gate electrode 110, [0068]) comprise a work function layer having mid-gap work function (the metals for 510A and 10B may each be any of the metals described for gate electrode 110; so they can be mid-gap work function metals, [0038]).
Regarding claim 23, Thomas teaches the p-type transistor (transistors 151 and 152 may be either n-type or p-type transistors, [0026]) has a p-type effective work function (a p-type dipole Vt shifter is present only around p-type channel regions, [0027]), and the n-type transistor (transistors 151 and 152 may be either n-type or p-type transistors, [0026]) has an n-type effective work function (an n-type dipole Vt shifter is present only around n-type channel regions, [0027]).
Regarding claim 24, Thomas teaches the first gate dielectric (Fig 5 high-k material 315, [0066]) comprises a first dipole dopant (Fig 5 dopant within Vt shifter source material 515, [0066]) of a first type (list for PMOS, [0047]), and the second gate dielectric (Fig 5 high-k material 315, [0066]) comprise a second dipole dopant (Fig 5 dopant within Vt shifter source material 516, [0067]) of a second type (list for NMOS, [0047]) opposite to the first type (list for PMOS, [0047]).
Regarding claim 25, Thomas teaches the first dipole dopant (Fig 5 dopant within Vt shifter source material 515, [0066]) is an n-type dipole dopant (list for NMOS, [0047]) selected from the group consisting of La (La, [0047]), Sr, Y, Er, Sc, Mg, and combinations thereof.
Regarding claim 26, Thomas teaches the first dipole dopant (Fig 5 dopant within Vt shifter source material 515, [0066]) is a p-type dipole dopant (list for PMOS, [0047]) selected from the group consisting of Al (Al, [0047]), Ga, Zn, Ti, Ta, and combinations thereof.
Regarding claim 27, Thomas teaches the upper transistor (Fig 5 transistor 152, [0025]) is the n-type transistor (transistors 151 and 152 may be either n-type or p-type transistors, [0026]), and the lower transistor (Fig 5 transistor 151, [0025]) is the p-type transistor (transistors 151 and 152 may be either n-type or p-type transistors, [0026]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Thomas et. al. (US 20220199620 A1), hereinafter Thomas, in view of Bao et. al. (US 20230261074 A1), hereinafter Bao.
Regarding claim 6, Thomas fails to teach forming a third semiconductor channel region at a same height as the first semiconductor channel region; forming a third gate dielectric on the third semiconductor channel region; forming a third dipole film on the first gate dielectric, wherein the third dipole film comprises the first dipole dopant of the first type, and the third dipole film has a higher dipole dopant concentration than the first dipole film, wherein additional dipole dopants in the third dipole film are driven into the third gate dielectric; and after the drive-in process, removing the third dipole film.
However, Thomas teaches an integrated circuit including the transistor stack structure (Fig 1 transistor stack structure 100, [0029]) may have metallization levels interconnecting transistor terminals with other nodes in a circuit ([0029]). Further, Thomas teaches an IC (Fig 8 IC 850) that includes one or more transistor stack structures ([0082]). Bao teaches forming a plurality of semiconductor channel regions at the same height (Fig 1 nanosheets 115, [0035]). Further, Bao teaches depositing different amounts of dipole material around the nanosheets of different devices ([0034]) to change the concentration/gradient of dipole material located within the underlying layers to adjust the threshold voltage ([0034]). One having ordinary skill in the art before the effective filing date of the claimed invention would have combined the method used in Thomas and Bao to have a third semiconductor channel at the same height as the first semiconductor channel. Further, one having ordinary skill in the art before the effective filing date of the claimed invention would be motivated to apply the teachings of Bao to allowing for a change in the threshold voltage of different devices. Each element of the combination performs the same function as it does separately and the result of the combination would have been predictable. MPEP 2143(I)(G)
In combining Thomas and Bao, one having ordinary skill in the art before the effective filing date of the claimed invention would form (Thomas: Fig 4B block 420, [0054]) a third semiconductor channel region (Fig 10 nanosheets 115 within device D3, [0035] corresponds to Thomas: Fig 5 a second channel region 215A, [0066]) at a same height as the first semiconductor channel region (Fig 10 nanosheets 115 within device D2, [0035] corresponds to Thomas: Fig 5 a first channel region 215A, [0066]); forming (Thomas: Fig 4B block 470, [0058]) a third gate dielectric (Fig 10 gate dielectric 125 for device D3, [0036] corresponds to Thomas: Fig 5 a third high-k material 315, [0066]) on the third semiconductor channel region (Fig 10 nanosheets 115 within device D3, [0035] corresponds to Thomas: Fig 5 a second channel region 215A, [0066]); forming (Bao: [0040]-[0044]) a third dipole film (Fig 10 combination of layers 145 and 165) on the first gate dielectric (Fig 10 gate dielectric 125 for device D3, [0036] corresponds to Thomas: Fig 5 a third high-k material 315, [0066]), wherein the third dipole film (Fig 10 combination of layers 145 and 165) comprises the first dipole dopant (Bao: this would allow for transistors of the same level to have the same polarity but different threshold voltages, [0047]) of the first type (Al203, [0035] corresponds to Thomas: list of PMOS materials including AlOx, [0047]), and the third dipole film (Fig 10 combination of layers 145 and 165) has a higher dipole dopant concentration (there is a larger amount of dipole material) than the first dipole film (Fig 10 layer 165 corresponds to Thomas: Fig 5 Vt shifter source material, [0066]), wherein additional dipole dopants in the third dipole film (Fig 10 combination of layers 145 and 165) are driven into ([0045] corresponds to Thomas: Fig 4B block 480, [0061]) the third gate dielectric (Fig 10 gate dielectric 125 for device D3, [0036] corresponds to Thomas: Fig 5 a third high-k material 315, [0066]); and after the drive-in process ([0045] corresponds to Thomas: Fig 4B block 480, [0061]), removing ([0046] corresponds to Thomas: Fig 4B block 490, [0062]) the third dipole film (Fig 10 combination of layers 145 and 165).
Regarding claim 7, Thomas as modified in claim 6 teaches the first semiconductor channel region (Thoams: Fig 5 channel region 215A, [0066]) and the third semiconductor channel region (Bao: Fig 10 nanosheets 115 within device D3) are parts of upper transistors (It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that the semiconductor regions are parts of transistors in the same height since the channels themselves are in the same height) in Complemental Field- Effect Transistor (CFET) structures (Thomas: Fig 1 transistor stack structure with complementary polarities, [0102]).
Regarding claim 8, Thomas as modified in claim 6 teaches forming (Thomas: Fig 4B block 495, [0063]) an additional gate electrode (Bao: Fig 14 gate metal 240 on device D3, [0048]) on the third gate dielectric (Bao: Fig 10 gate dielectric 125 for device D3, [0036] corresponds to Thomas: Fig 5 a third high-k material 315, [0066]), wherein the gate electrode (Fig 5 metal 510, [0068]) and the additional gate electrode (Bao: Fig 14 gate metal 240 on device D3, [0048]) are formed in a same formation process (Bao: gate metal is formed on each of the devices, [0048]).
Claims 28-30 are rejected under 35 U.S.C. 103 as being unpatentable over Thomas et. al. (US 20220199620 A1), hereinafter Thomas.
Regarding claim 28, Thomas teaches a method ([0053]) comprising: forming ([0053]) a lower transistor (Fig 5 transistor 151, [0025]) comprising: a first gate dielectric (Fig 5 high-k material 315, [0066]) on the first semiconductor channel region (Fig 5 channel region 215A, [0066]); and a first source/drain region (Fig 1 source and drain regions 106, [0026]; the source and drain materials may be grown as separate crystals, [0056]) connecting to the first semiconductor channel region (Fig 5 channel region 215A, [0066]); and forming ([0053]) an upper transistor (Fig 5 transistor 152, [0025]) comprising: a second semiconductor channel region (Fig 2B channel region 115B, [0034]) overlapping the first semiconductor channel region (Fig 2B channel region 115A, [0034]);a second gate dielectric (Fig 5 high-k material 315, [0066]) on the second semiconductor channel region (Fig 5 channel region 215B, [0066]); and a second source/drain region (Fig 1 source and drain regions 106, [0026]; the source and drain materials may be grown as separate crystals, [0056]) connecting to the second semiconductor channel region (Fig 5 channel region 215B, [0066]), wherein the first source/drain region (Fig 1 source and drain regions 106, [0026]; the source and drain materials may be grown as separate crystals, [0056]) and the second source/drain region (Fig 1 source and drain regions 106, [0026]; the source and drain materials may be grown as separate crystals, [0056]) have opposite conductivity types (for CMOS stacks the source and drain regions comprise portions associated with each transistor, [0030]; this would imply to one having ordinary skill in the art before the effective filing date of the claimed invention that the conductivity types are opposite MPEP 2144.01); and in a same formation process ([0053]), forming (Fig 5 operation 530, [0068]) a common gate electrode (Fig 5work function metal 510A, [0068]) continuously extending from a first level lower (Fig 5) than the first semiconductor channel region (Fig 5 channel region 215A, [0066]) to a second level higher (Fig 5) than the second semiconductor channel region (Fig 5 channel region 215B, [0066]), wherein the common gate electrode (Fig 5 work function metal 510A, [0068]) comprises a mid-gap work function layer (the work function metal 510A may be any type described for gate electrode 110, [0068]; gate electrode 110 may be a mid-gap work function metal, [0038]).
Regarding claim 29, Thomas teaches the common gate electrode (Fig 5 work function metal 510A, [0068]) comprises: a lower portion (Fig 5 after operation 535 lower work function metal 510A, [0068]) acting as a first gate electrode (Fig 5 after operation 535 lower work function metal 510A, [0068]) of the lower transistor (Fig 5 transistor 151, [0025]); and an upper portion (Fig 5 after operation 540 upper work function metal 510B, [0068]) acting as a second gate electrode (Fig 5 after operation 540 upper work function metal 510B, [0068]) of the upper transistor (Fig 5 transistor 152, [0025]), wherein the lower portion (Fig 5 after operation 535 lower work function metal 510A, [0068]) and the upper portion (Fig 5 after operation 540 upper work function metal 510B, [0068]) are formed through a same deposition process (Fig 6 operation 535, [0073]).
However, Thomas teaches in [0068] the first work function metal 510A may be recess and another work function metal deposited on top. However, [0068] further discloses the metals may each be any of the metals described for gate electrode 110. This would allow for both work function metals 510A and 510B to be mid-gap. [0073] discloses multiple work function metals may be deposited. In that case, the structure would resemble that of Fig 5.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention that the single work function metal 510 after operation of Fig 6 and the single work function metal 510A after operation 530 of Fig 5 are the same. Thus, either Fig 5 or Fig 6 would allow for a single mid-gap work function metal.
Regarding claim 30, Thomas teaches the first gate dielectric (Fig 5 high-k material 315, [0066] corresponds to Fig 2B gate insulator 217A, [0042]) and the second gate dielectric (Fig 5 high-k material 315, [0066] corresponds to Fig 2B gate insulator 217A, [0042]) comprise dipole dopants (Fig 3 not shown dipole metal M2, [0046]) having opposite conductivity types (list of metals M2 for PMOS and NMOS).
However, Thomas teaches a list of metals M2 for both PMOS and NMOS transistors.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use the appropriate dipole metal M2 for the type of transistor needed.
Conclusion
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALVIN L LEE whose telephone number is (703)756-1921. The examiner can normally be reached Monday - Friday 8:30 am - 5 pm (ET).
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/ALVIN L LEE/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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