DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 10-20 are objected to because of the following informalities:
Claim 10 recites “front side conductive lines and extending” which should be replaced with “front side conductive lines extending”, to improve claim language.
Claim 13 recites “a fourth one of the front side conductive lines is configured to receive a control signal, an input signal, an output signal” which should be replaced with “a fourth one of the front side conductive lines is configured to receive a control signal, an input signal, or an output signal”, to improve claim language.
Claim 15 recites “to receive a control signal, an input signal, an output signal” (lines 3 and 5) which should be replaced with “to receive a control signal, an input signal, or an output signal”, to improve claim language.
Claim 16 recites “at and that” (line 3) which should be replaced with “that”, to improve claim language.
Claim 16 recites “at and extending” (line 7) which should be replaced with “extending”, to improve claim language.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-8, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0123751 to Thyagarajan et al. (cited in IDS of 04/01/2024, hereinafter Thyagarajan) in view of Chen et al. (US 2022/0084561, cited in IDS of 04/01/2024, hereinafter Chen).
With respect to claims 1 and 5-8, Thyagarajan discloses a semiconductor device (e.g., memory device comprising a plurality of cells) (Thyagarajan, Figs. 2A-2B, ¶0008-¶0010, ¶0013-¶0030), comprising:
at a front side (e.g., FS) of a semiconductor substrate (e.g., memory device disposed on a substrate) (Thyagarajan, Figs. 2A-2B, ¶0019, ¶0022), a first front side conductive line (e.g., FS/M0) (Thyagarajan, Figs. 2A-2B, ¶0022, ¶0029) extending in a first direction (e.g., a horizontal direction in Fig. 2B); and
at a back side of the semiconductor substrate (e.g., backside power rails buried in the substrate) (Thyagarajan, Figs. 2A-2B, ¶0019, ¶0022), a first back side power rail (e.g., rail segment S1 in the BS/BM0 metal layer to receive power signals VDDP) (Thyagarajan, Figs. 2A-2B, ¶0024, ¶0027-¶0028), a second back side power rail (e.g., rail segment S4 in the BS/BM0 metal layer to receive power signals VDDPE), a third back side power rail (e.g., rail segment S5 in the BS/BM0 metal layer to receive power signals VDDP) in a same back side metal layer (e.g., BS/BM0 metal layer) and each extending in the first direction (e.g., the horizontal direction in Fig. 2B); and
wherein:
within a span of a first cell (e.g., within cell boundary (CB)) (Thyagarajan, Fig. 2B, ¶0024) that is defined relative to a second direction,
the second back side power rail (e.g., rail segment S4) is between the third and the first back side power rails (e.g. rail segments S1 and S5) relative to the second direction;
each of the first (e.g., rail segment S1 in the BS/BM0 metal layer to receive power signals VDDP) (Thyagarajan, Figs. 2A-2B, ¶0024, ¶0027-¶0028), second (e.g., rail segment S4 in the BS/BM0 metal layer to receive power signals VDDPE), third (e.g., rail segment S5 in the BS/BM0 metal layer to receive power signals VDDP) back side power rails is configured to receive a corresponding one of reference voltages, the reference voltages (e.g., VDDP and VDDPE) (Thyagarajan, Figs. 2A-2B, ¶0029) being different from each other and including, a first reference voltage (e.g., VDDPP) and a second reference power voltage (e.g., VDDPE);
the first and second reference voltages are different from each other;
the first front side conductive line (e.g., FS/M0) (Thyagarajan, Figs. 2A-2B, ¶0022, ¶0029) is configured to receive a control signal, an input signal, an output signal or one of the reference voltages (e.g., a control signal SLEEP) (Thyagarajan, Figs. 2A-2B, ¶0029); and
relative to a center of the second back side power rail (e.g., rail segment S4) that is defined according to the first direction (e.g., the horizontal direction in Fig. 2B) and a substantially perpendicular second direction (e.g., the vertical direction in Fig. 2B), a distribution of the first and second reference voltages (VDDP and VDDPE) amongst the first, second and third back side power rails is (B) symmetric with respect to the second direction.
Further, Thyagarajan does not specifically disclose a fourth back side power rail and a fifth back side power rail in a same back side metal layer; and wherein: within a span of the first cell that is defined relative to the first direction, the second back side power rail is between the third and the fourth back side power rails relative to the first direction; each of the fourth and fifth back side power rails is configured to receive a corresponding one of reference voltages including a third reference voltage; the first, second and third reference voltages are different from each other; and a distribution of the first, second and third reference voltages amongst the first, second, third, fourth and fifth back side power rails is (A) symmetric with respect to the first direction (as claimed in claim 1); wherein: relative to the center of the second back side power rail, the third and fourth back side power rails are on opposite sides of the second back side power rail relative to the first direction (as claimed in claim 5); wherein: the second back side power rail is configured to receive the third reference voltage; and each of the third and fourth back side power rails is configured to receive the first reference voltage (as claimed in claim 6); wherein: relative to the center of the second back side power rail, the first and fifth back side power rails are on opposite sides of the second back side power rail relative to the second direction (as claimed in claim 7); wherein: the second back side power rail is configured to receive the third reference voltage; and each of the first and fifth back side power rails is configured to receive the second reference voltage (as claimed in claim 8).
However, Thyagarajan teaches that in some implementation (Thyagarajan, Fig. 2B, ¶0027), the second row (R2) has segmented power rail with multiple segments separated by the rail break (RB2).
Further, Chen teaches forming a device having backside power rails (Chen, Fig. 2, ¶0008-¶0009, ¶0029-¶0035) to provide backside power distribution network for memory application, wherein backside power rails are formed in the backside metal layer (BM0) (Chen, Fig. 2, ¶0029-¶0030) and includes a row configured with a plurality of rail breaks (RB) that interrupt continuity of the backside power rails to supply different power voltages within the same region (214). Specifically, within a memory region (214), backside power rail in a second row (R2) (Chen, Fig. 2, ¶0033-¶0034) includes two breaks (RB) such that a second back side power rail supplied a power voltage (VDDPE), a third backside power rail supplied with ground signal (VSSE), and a fourth back side power rail supplied with ground signal (VSSE) are disposed in the same back side metal layer (BM0) and extending in a first direction. Further, each of the third and fourth back side power rails is configured to receive the same reference power voltage (VSSE) (Chen, Fig. 2, ¶0032-¶0034); and a backside power rail in the first row has a power signal (VDDP) that is different from the ground signal (VSSE) of the third and fourth backside power rails, and the power voltage (VDDPE) of the second back side power rail. In the second row (R2), within a span of the memory region (214) that is defined relative to the first direction, the second back side power rail (VDDPE) is between the third and the fourth back side power rails (e.g., with voltage VSSE) relative to the first direction. Further, relative to the center of the second back side power rail, the third and fourth back side power rails are on opposite sides of the second back side power rail (VDDPE) relative to the first direction; and the second back side power rail is configured to receive the third reference voltage (VDDPE); and each of the third and fourth back side power rails is configured to receive the first reference voltage (VSSE). Further, Chen teaches that backside power rail (BPR) architecture includes a plurality of power rail rows (R1-R2) (Chen, Fig. 2, ¶0029).
Thus, a person of ordinary skill in the art would recognize that with a third power rail configured as a first power rail in the first row R1, a fifth back side power rail having a corresponding reference voltage (VDDP) would be formed in a same back side metal layer as the first to fourth power rails, and the fist power rail and the fifth power rail would have the same reference voltage VDDP, such that the first (VDDP), second (VSSE) and third (VDDPE) reference voltages would be different from each other; and a distribution of the first (VSSE), second (VDDPE) and third (VDDP) reference voltages amongst the first, second, third, fourth and fifth back side power rails would be (A) symmetric with respect to the first direction and (B) symmetric with respect to the second direction. In the backside power rail (BPR) architecture including three rows (R1-R2-R1), relative to the center of the second back side power rail (VDDPE), the first (e.g., in the first row R1) and fifth (e.g., in the third row, the same as the first row R1) back side power rails are on opposite sides of the second back side power rail relative to the second direction; and the second back side power rail is configured to receive the third reference voltage (VDDPE); and each of the first and fifth back side power rails is configured to receive the second reference voltage (VDDP). The backside power rails of Chen have low resistance for power distribution and an architecture to improve current-resistance drop, performance, and area efficiency of memory device (Chen, Fig. 2, ¶0032).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Thyagarajan by forming backside power network having a plurality of backside power rails (e.g., R1, R2, and R3) in a first backside metal layer (e.g., BM0) for providing power in multiple domains (e.g., VDDPE, VSSE, and VDDP) and having multiple rail breaks within a second backside row (R2) as taught by Chen to have the semiconductor device, comprising: a fourth back side power rail and a fifth back side power rail in a same back side metal layer; and wherein: within a span of the first cell that is defined relative to the first direction, the second back side power rail is between the third and the fourth back side power rails relative to the first direction; each of the fourth and fifth back side power rails is configured to receive a corresponding one of reference voltages including a third reference voltage; the first, second and third reference voltages are different from each other; and a distribution of the first, second and third reference voltages amongst the first, second, third, fourth and fifth back side power rails is (A) symmetric with respect to the first direction (as claimed in claim 1); wherein: relative to the center of the second back side power rail, the third and fourth back side power rails are on opposite sides of the second back side power rail relative to the first direction (as claimed in claim 5); wherein: the second back side power rail is configured to receive the third reference voltage; and each of the third and fourth back side power rails is configured to receive the first reference voltage (as claimed in claim 6); wherein: relative to the center of the second back side power rail, the first and fifth back side power rails are on opposite sides of the second back side power rail relative to the second direction (as claimed in claim 7); wherein: the second back side power rail is configured to receive the third reference voltage; and each of the first and fifth back side power rails is configured to receive the second reference voltage (as claimed in claim 8), in order to provide backside power distribution having an architecture to improve current-resistance drop, performance, and area efficiency of memory device (Chen, ¶0002, ¶0008, ¶0009, ¶0032).
Regarding Claim 2, Thyagarajan in view of Chen discloses the semiconductor device of claim 1. Further, Thyagarajan discloses the semiconductor device, wherein: the first front side conductive line (e.g., FS/M0) (Thyagarajan, Fig. 2B, ¶0022, ¶0029) is in a first front side metal layer (FS/M0, coupled to the gates through the vias V0 formed over the substrate) over the semiconductor substrate.
Regarding Claim 3, Thyagarajan in view of Chen discloses the semiconductor device of claim 2. Further, Thyagarajan discloses the semiconductor device, further comprising: a second front side conductive line (e.g., second FS/M0) (Thyagarajan, Fig. 2B, ¶0022, ¶0029) in the first front side metal layer.
With respect to claims 16-20, Thyagarajan discloses a method of fabricating a semiconductor device (e.g., forming a memory device comprising a plurality of cells) (Thyagarajan, Figs. 2A-2B, ¶0008-¶0010, ¶0013-¶0030), the method comprising:
at a front side (e.g., FS) of a semiconductor substrate (e.g., memory device disposed on a substrate) (Thyagarajan, Figs. 2A-2B, ¶0019, ¶0022), forming front side conductive lines (e.g., FS/M0) (Thyagarajan, Figs. 2A-2B, ¶0022, ¶0029) including a first front side conductive line at and that extends in a first direction (e.g., a horizontal direction in Fig. 2B); and
at a back side of the semiconductor substrate (e.g., backside power rails buried in the substrate) (Thyagarajan, Figs. 2A-2B, ¶0019, ¶0022), forming back side power rails including a first back side power rail (e.g., rail segment S1 in the BS/BM0 metal layer to receive power signals VDDP) (Thyagarajan, Figs. 2A-2B, ¶0024, ¶0027-¶0028), a second back side power rail (e.g., rail segment S4 in the BS/BM0 metal layer to receive power signals VDDPE), a third back side power rail (e.g., rail segment S5 in the BS/BM0 metal layer to receive power signals VDDP), the back side power rails being in a same back side metal layer (e.g., BS/BM0 metal layer) at and extending in the first direction (e.g., the horizontal direction in Fig. 2B), the forming back side power rails including:
within a span of a first cell (e.g., within cell boundary (CB)) (Thyagarajan, Fig. 2B, ¶0024) that is defined relative to a second direction,
locating the second back side power rail (e.g., rail segment S4) is between the third and the first back side power rails (e.g. rail segments S1 and S5) relative to the second direction;
configuring the front side conducting lines including configuring the first front side conductive line (e.g., FS/M0) (Thyagarajan, Figs. 2A-2B, ¶0022, ¶0029) to receive a control signal, an input signal, an output signal or a corresponding one of reference voltages (e.g., a control signal), the reference voltages (e.g., VDDP and VDDPE) including a first reference voltage, and a second reference voltage which are different from each other;
configuring the back side power rails including configuring each of the first (e.g., rail segment S1 in the BS/BM0 metal layer to receive power signals VDDP) (Thyagarajan, Figs. 2A-2B, ¶0024, ¶0027-¶0028), second (e.g., rail segment S4 in the BS/BM0 metal layer to receive power signals VDDPE), third (e.g., rail segment S5 in the BS/BM0 metal layer to receive power signals VDDP) back side power rails to receive a corresponding one of the first and second reference voltages; and
relative to a center of the second back side power rail (e.g., rail segment S4) that is defined according to the first direction (e.g., the horizontal direction in Fig. 2B) and a substantially perpendicular second direction (e.g., the vertical direction in Fig. 2B), arranging a distribution of the first and second reference voltages (VDDP and VDDPE) amongst the first, second and third back side power rails to be (B) symmetric with respect to the second direction.
Further, Thyagarajan does not specifically disclose forming a fourth back side power rail and a fifth back side power rail in a same back side metal layer, the forming back side power rails including: within a span of the first cell that is defined relative to the first direction, locating the second back side power rail between the third and the fourth back side power rails relative to the first direction; the reference voltages including a first reference voltage, a second reference voltage and a third reference voltage which are different from each other; configuring each of the fourth and fifth back side power rails to receive a corresponding one of reference voltages including a third reference voltage; and arranging a distribution of the first, second and third reference voltages amongst the first, second, third, fourth and fifth back side power rails to be (A) symmetric with respect to the first direction (as claimed in claim 16); wherein the forming back side power rails includes: relative to the center of the second back side power rail, locating the third and fourth back side power rails are on opposite sides of the second back side power rail relative to the first direction (as claimed in claim 17); wherein: the configuring the back side power rails includes: configuring the second back side power rail to receive the third reference voltage; and configuring each of the third and fourth back side power rails to receive the first reference voltage (as claimed in claim 18); wherein the forming back side power rails includes: relative to the center of the second back side power rail, locating the first and fifth back side power rails are on opposite sides of the second back side power rail relative to the second direction (as claimed in claim 19); wherein: the configuring the back side power rails includes: configuring the second back side power rail to receive the third reference voltage; and configuring each of the first and fifth back side power rails to receive the second reference voltage (as claimed in claim 20).
However, Thyagarajan teaches that in some implementation (Thyagarajan, Fig. 2B, ¶0027), the second row (R2) has segmented power rail with multiple segments separated by the rail break (RB2).
Further, Chen teaches forming a device having backside power rails (Chen, Fig. 2, ¶0008-¶0009, ¶0029-¶0035) to provide backside power distribution network for memory application, wherein backside power rails are formed in the backside metal layer (BM0) (Chen, Fig. 2, ¶0029-¶0030) and includes a row configured with a plurality of rail breaks (RB) that interrupt continuity of the backside power rails to supply different power voltages within the same region (214). Specifically, within a memory region (214), backside power rail in a second row (R2) (Chen, Fig. 2, ¶0033-¶0034) includes two breaks (RB) such that a second back side power rail supplied a power voltage (VDDPE), a third backside power rail supplied with ground signal (VSSE), and a fourth back side power rail supplied with ground signal (VSSE) are disposed in the same back side metal layer (BM0) and extending in a first direction. Further, each of the third and fourth back side power rails is configured to receive the same reference power voltage (VSSE) (Chen, Fig. 2, ¶0032-¶0034); and a backside power rail in the first row has a power signal (VDDP) that is different from the ground signal (VSSE) of the third and fourth backside power rails, and the power voltage (VDDPE) of the second back side power rail. In the second row (R2), within a span of the memory region (214) that is defined relative to the first direction, the second back side power rail (VDDPE) is between the third and the fourth back side power rails (e.g., with voltage VSSE) relative to the first direction. Further, relative to the center of the second back side power rail, the third and fourth back side power rails are on opposite sides of the second back side power rail (VDDPE) relative to the first direction; and the second back side power rail is configured to receive the third reference voltage (VDDPE); and each of the third and fourth back side power rails is configured to receive the first reference voltage (VSSE). Further, Chen teaches that backside power rail (BPR) architecture includes a plurality of power rail rows (R1-R2) (Chen, Fig. 2, ¶0029).
Thus, a person of ordinary skill in the art would recognize that with a third power rail configured as a first power rail in the first row R1, a fifth back side power rail having a corresponding reference voltage (VDDP) would be formed in a same back side metal layer as the first to fourth power rails, and the fist power rail and the fifth power rail would have the same reference voltage VDDP, such that the first (VDDP), second (VSSE) and third (VDDPE) reference voltages would be different from each other; and a distribution of the first (VSSE), second (VDDPE) and third (VDDP) reference voltages amongst the first, second, third, fourth and fifth back side power rails would be (A) symmetric with respect to the first direction and (B) symmetric with respect to the second direction. In the backside power rail (BPR) architecture including three rows (R1-R2-R1), relative to the center of the second back side power rail (VDDPE), the first (e.g., in the first row R1) and fifth (e.g., in the third row, the same as the first row R1) back side power rails are on opposite sides of the second back side power rail relative to the second direction; and the second back side power rail is configured to receive the third reference voltage (VDDPE); and each of the first and fifth back side power rails is configured to receive the second reference voltage (VDDP). The backside power rails of Chen have low resistance for power distribution and an architecture to improve current-resistance drop, performance, and area efficiency of memory device (Chen, Fig. 2, ¶0032).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the method of Thyagarajan by forming backside power network having a plurality of backside power rails (e.g., R1, R2, and R3) in a first backside metal layer (e.g., BM0) for providing power in multiple domains (e.g., VDDPE, VSSE, and VDDP) and having multiple rail breaks within a second backside row (R2) as taught by Chen to have the method comprising: forming a fourth back side power rail and a fifth back side power rail in a same back side metal layer, the forming back side power rails including: within a span of the first cell that is defined relative to the first direction, locating the second back side power rail between the third and the fourth back side power rails relative to the first direction; the reference voltages including a first reference voltage, a second reference voltage and a third reference voltage which are different from each other; configuring each of the fourth and fifth back side power rails to receive a corresponding one of reference voltages including a third reference voltage; and arranging a distribution of the first, second and third reference voltages amongst the first, second, third, fourth and fifth back side power rails to be (A) symmetric with respect to the first direction (as claimed in claim 16); wherein the forming back side power rails includes: relative to the center of the second back side power rail, locating the third and fourth back side power rails are on opposite sides of the second back side power rail relative to the first direction (as claimed in claim 17); wherein: the configuring the back side power rails includes: configuring the second back side power rail to receive the third reference voltage; and configuring each of the third and fourth back side power rails to receive the first reference voltage (as claimed in claim 18); wherein the forming back side power rails includes: relative to the center of the second back side power rail, locating the first and fifth back side power rails are on opposite sides of the second back side power rail relative to the second direction (as claimed in claim 19); wherein: the configuring the back side power rails includes: configuring the second back side power rail to receive the third reference voltage; and configuring each of the first and fifth back side power rails to receive the second reference voltage (as claimed in claim 20), in order to provide backside power distribution having an architecture to improve current-resistance drop, performance, and area efficiency of memory device (Chen, ¶0002, ¶0008, ¶0009, ¶0032).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0123751 to Thyagarajan in view of Chen (US 2022/0084561) as applied to claim 1, and further in view of Lim et al. (US 2022/0102266, hereinafter Lim).
Regarding Claim 4, Thyagarajan in view of Chen discloses the semiconductor device of claim 1. Further, Thyagarajan does not specifically disclose that each of the first, second, third, fourth and fifth back side power rails is in a first back side metal layer beneath the semiconductor substrate.
However, Lim teaches forming back side routing including a plurality of the back side conductive lines (e.g., 306(1)-306(4) and 314 (1) and 314(2)) (Lim, Figs. 1A, 3A-3E, ¶0037-¶0040) that are disposed under the semiconductor substrate (304P/304N), to lift a power signal routed in in the back side routing to a front side metal line to conserve the area and reduce routing complexity.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Thyagarajan/Chen by forming back side routing including a plurality of the back side conductive lines as taught by Lim to have the semiconductor device, wherein: each of the first, second, third, fourth and fifth back side power rails is in a first back side metal layer beneath the semiconductor substrate, in order to conserve the area and reduce routing complexity (Lim, ¶0005, ¶0006, ¶0037, ¶0039).
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0123751 to Thyagarajan in view of Chen (US 2022/0084561) as applied to claim 5, and further in view of Fan et al. (US 2018/0145070, cited in IDS of 04/01/2024, hereinafter Fan).
Regarding Claim 9, Thyagarajan in view of Chen discloses the semiconductor device of claim 5. Further, Thyagarajan does not specifically disclose the semiconductor device, wherein: the third reference power voltage is true VDD (TVDD); the second reference power voltage is virtual VDD (VVDD); and the first reference power voltage is VSS. However, Fan teaches forming the cell of the semiconductor device (Fan, Figs. 1-3, ¶0018) including a first source voltage signal (a true source voltage signal VDD) (Fan, Figs. 1-3, ¶0018) connected to a first source/drain terminal of a first transistor (e.g., NFET or PFET 230/240) and a second source voltage signal (a virtual source voltage signal VDD) connected to second source/drain terminal of the first transistor (230/240), and a first reference voltage signal (a true reference voltage signal VSS) (Fan, Figs. 1-3, ¶0019) connected to a first source/drain terminal of a second transistor (e.g., NFET or PFET 270/280) and a second reference voltage signal (a virtual reference voltage signal VSS) connected to second source/drain terminal of the second transistor (270/280).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to further modify the semiconductor device of Thyagarajan/Chen by forming a semiconductor device including a cell having true and virtual source voltage rails and true and virtual reference voltage rails as taught by Fan, wherein the true and virtual power signals (e.g., including a first reference power voltage) are provided to the front side metallization of Thyagarajan and routed to the back side metallization and distributed therein using a plurality of back side metal lines to provide different power signals to have the semiconductor device, wherein: the third reference power voltage is true VDD (TVDD); the second reference power voltage is virtual VDD (VVDD); and the first reference power voltage is VSS in order to provide improved layout that is susceptible to electromigration to avoid an open circuit and a short circuit in the semiconductor device (Fan, ¶0001, ¶0014, ¶0022).
Claims 10-15 are rejected under 35 U.S.C. 103 as being unpatentable over US 2022/0123751 to Thyagarajan in view of Chen (US 2022/0084561) and Lim (US 2022/0102266).
With respect to claim 10, Thyagarajan discloses a semiconductor device (e.g., memory device comprising a plurality of cells) (Thyagarajan, Figs. 2A-2B, ¶0008-¶0010, ¶0013-¶0030) comprising:
at a front side (e.g., FS) of a semiconductor substrate (e.g., memory device disposed on a substrate) (Thyagarajan, Figs. 2A-2B, ¶0019, ¶0022), front side conductive lines (e.g., FS/M0) (Thyagarajan, Figs. 2A-2B, ¶0022, ¶0029) and extending in a first direction (e.g., a horizontal direction in Fig. 2B); and
at a back side of the semiconductor substrate (e.g., backside power rails buried in the substrate) (Thyagarajan, Figs. 2A-2B, ¶0019, ¶0022), a first back side power rail (e.g., rail segment S1 in the BS/BM0 metal layer to receive power signals VDDP) (Thyagarajan, Figs. 2A-2B, ¶0024, ¶0027-¶0028), a second back side power rail (e.g., rail segment S4 in the BS/BM0 metal layer to receive power signals VDDPE), a third back side power rail (e.g., rail segment S5 in the BS/BM0 metal layer to receive power signals VDDP) in a same back side metal layer (e.g., BS/BM0 metal layer) and each extending in the first direction (e.g., the horizontal direction in Fig. 2B); and
wherein:
the first back side power rail (e.g., rail segment S1) (Thyagarajan, Fig. 2B, ¶0028) is configured to receive a first reference power voltage (e.g., VDDP);
the second back side power rail (e.g., rail segment S4) (Thyagarajan, Fig. 2B, ¶0028) is configured to receive a second reference power voltage (e.g., VDDPE);
within a span of a first cell region (e.g., within cell boundary (CB)) (Thyagarajan, Fig. 2B, ¶0024) that is defined relative to a second direction,
the second back side power rail (e.g., rail segment S4) is between the third and the first back side power rails (e.g. rail segments S1 and S5) relative to the second direction;
the first reference voltage and the second reference voltage are different from each other.
Further, Thyagarajan does not specifically disclose (1) a fourth back side power rail and a fifth back side power rail in a same back side metal layer; and wherein: each of the third and fourth back side power rails is configured to receive a third reference voltage; within a span of the first cell that is defined relative to the first direction, the second back side power rail is between the third and the fourth back side power rails relative to the first direction; the first reference voltage, the second reference voltage, and the third reference voltage are different from each other; (2) first and second ones of the front side conductive lines are configured to receive the first reference voltage; a third one of the front side conductive lines is configured to receive the third reference voltage.
Regarding (1), Thyagarajan teaches that in some implementation (Thyagarajan, Fig. 2B, ¶0027), the second row (R2) has segmented power rail with multiple segments separated by the rail break (RB2).
Further, Chen teaches forming a device having backside power rails (Chen, Fig. 2, ¶0008-¶0009, ¶0029-¶0035) to provide backside power distribution network for memory application, wherein backside power rails are formed in the backside metal layer (BM0) (Chen, Fig. 2, ¶0029-¶0030) and includes a row configured with a plurality of rail breaks (RB) that interrupt continuity of the backside power rails to supply different power voltages within the same region (214). Specifically, within a memory region (214), backside power rail in a second row (R2) (Chen, Fig. 2, ¶0033-¶0034) includes two breaks (RB) such that a second back side power rail supplied a power voltage (VDDPE), a third backside power rail supplied with ground signal (VSSE), and a fourth back side power rail supplied with ground signal (VSSE) are disposed in the same back side metal layer (BM0) and extending in a first direction. Further, each of the third and fourth back side power rails is configured to receive the same reference power voltage (VSSE) (Chen, Fig. 2, ¶0032-¶0034); and a backside power rail in the first row has a power signal (VDDP) that is different from the ground signal (VSSE) of the third and fourth backside power rails, and the power voltage (VDDPE) of the second back side power rail. In the second row (R2), within a span of the memory region (214) that is defined relative to the first direction, the second back side power rail (VDDPE) is between the third and the fourth back side power rails (e.g., with voltage VSSE) relative to the first direction. Further, Chen teaches that backside power rail (BPR) architecture includes a plurality of power rails (R1-R2).
Thus, a person of ordinary skill in the art would recognize that with a third power rail configured as a first power rail in the first row R1, a fifth back side power rail having a corresponding reference voltage (VDDP) would be formed in a same back side metal layer as the first to fourth power rails, and the fist power rail and the fifth power rail would have the same reference voltage VDDP, such that the first (VDDP), second (VSSE) and third (VDDPE) reference voltages would be different from each other. The backside power rails of Chen have low resistance for power distribution and an architecture to improve current-resistance drop, performance, and area efficiency of memory device (Chen, Fig. 2, ¶0032).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Thyagarajan by forming backside power network having a plurality of backside power rails (e.g., R1, R2, and R3) in a first backside metal layer (e.g., BM0) for providing power in multiple domains (e.g., VDDPE, VSSE, and VDDP) and having multiple rail breaks within a second backside row (R2) as taught by Chen to have the semiconductor device, comprising: a fourth back side power rail and a fifth back side power rail in a same back side metal layer; and wherein: each of the third and fourth back side power rails is configured to receive a third reference voltage; within a span of the first cell that is defined relative to the first direction, the second back side power rail is between the third and the fourth back side power rails relative to the first direction; the first reference voltage, the second reference voltage, and the third reference voltage are different from each other, in order to provide backside power distribution having an architecture to improve current-resistance drop, performance, and area efficiency of memory device (Chen, ¶0002, ¶0008, ¶0009, ¶0032).
Regarding (2), Lim teaches forming back-side-front side connection structure (Lim, Figs. 1A, 3A-3E, ¶0005-¶0006, ¶0037-¶0040) to lift a power signal routed in in the back side routing to a front side metal line, wherein the back side metal lines (e.g., 306(1)-306(4) and 314 (1) and 314(2)) are disposed under the semiconductor substrate (304P/304N); and first and second ones (e.g., 308(1)(1)-308(1)(2) and 308(2)) of the front side conductive lines are disposed above the semiconductor substrate (304P/304N) in the first metal layer (M1) and the second metal layer (M2) and configured to receive a corresponding reference voltage from the back side metal lines, to conserve the area and reduce routing complexity.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Thyagarajan/Chen by forming back-side-front side connection structure to lift a power signal routed in in the back side routing to a front side metal line as taught by Lim, wherein the power signal includes a corresponding reference voltage to have the semiconductor device, wherein first and second ones of the front side conductive lines are configured to receive the first reference voltage; a third one of the front side conductive lines is configured to receive the third reference voltage, in order to conserve the area and reduce routing complexity (Lim, ¶0005, ¶0006, ¶0037, ¶0039).
Regarding Claim 11, Thyagarajan in view of Chen and Lim discloses the semiconductor device of claim 10. Further, Thyagarajan discloses the semiconductor device, wherein: the first front side conductive lines (e.g., FS/M0) (Thyagarajan, Fig. 2B, ¶0022, ¶0029) are in a first front side metal layer (FS/M0, coupled to the gates through the vias V0 formed over the substrate) over the semiconductor substrate.
Regarding Claim 12, Thyagarajan in view of Chen and Lim discloses the semiconductor device of claim 10. Further, Thyagarajan does not specifically disclose that each of the first, second, third, fourth and fifth back side power rails is in a first back side metal layer beneath the semiconductor substrate.
However, Lim teaches forming back side routing including a plurality of the back side conductive lines (e.g., 306(1)-306(4) and 314 (1) and 314(2)) (Lim, Figs. 1A, 3A-3E, ¶0037-¶0040) that are disposed under the semiconductor substrate (304P/304N), to lift a power signal routed in in the back side routing to a front side metal line to conserve the area and reduce routing complexity.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Thyagarajan/Chen/Lim by forming back side routing including a plurality of the back side conductive lines as taught by Lim to have the semiconductor device, wherein: each of the first, second, third, fourth and fifth back side power rails is in a first back side metal layer beneath the semiconductor substrate, in order to conserve the area and reduce routing complexity (Lim, ¶0005, ¶0006, ¶0037, ¶0039).
Regarding Claim 13, Thyagarajan in view of Chen and Lim discloses the semiconductor device of claim 10. Further, Thyagarajana discloses the semiconductor device, wherein fourth one of the front side conductive lines (e.g., one of the front side lines FS/M1) (Thyagarajan, Fig. 2B, ¶0022, ¶0029) is configured to receive a control signal, an input signal, an output signal (e.g., a control signal).
Regarding Claims 14 and 15, Thyagarajan in view of Chen and Lim discloses the semiconductor device of claim 10. Further, Thyagarajana does not specifically disclose a first group including instances of a fourth one of the front side conductive lines is between the third and first front side conductive lines relative to the first direction; and a second group including instances of a fifth one of the front side conductive lines is between the third and second front side conductive lines relative to the first direction (as claimed in claim 14); wherein: each instance of the fourth front side conductive line in the first group is configured to receive a control signal, an input signal, an output signal; or each instance of the fifth front side conductive line in the second group is configured to receive a control signal, an input signal, an output signal (as claimed in claim 15).
However, Chen teaches a plurality of front side conductive lines (e.g., in the front side M0 layer) (Chen, Fig. 2, ¶0027, ¶0032) configured to receive the first reference voltage (e.g., VSSE) and the second reference voltage (VDDC), and including a fourth one of the front side conductive lines (e.g., in the secodont row R2) is between the third and first front side conductive lines (e.g., in the first row R1) relative to the first direction (e.g., horizontal direction in Fig. 2). Further, Chen teaches that conductive line architecture includes a plurality of conductive line rows (R1-R2) (Chen, Fig. 2, ¶0029).
Thus, a person of ordinary skill in the art would recognize that with a plurality of conductive line rows (R1-R2), a second group including a fifth one (e.g., in another second row R2) of the front side conductive lines would be between the third and second front side conductive lines (e.g., in the first rows R1) relative to the first direction.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the semiconductor device of Thyagarajan/Chen/Lim by forming a plurality of rows having frontside conductive lines extending over the backside power rails as taught by Chen, wherein one row having a frontside line is between adjacent rows having frontside conductive lines, and frontside conductive lines receive a corresponding signal to have the semiconductor device, wherein: a first group including instances of a fourth one of the front side conductive lines is between the third and first front side conductive lines relative to the first direction; and a second group including instances of a fifth one of the front side conductive lines is between the third and second front side conductive lines relative to the first direction (as claimed in claim 14); wherein: each instance of the fourth front side conductive line in the first group is configured to receive a control signal, an input signal, an output signal; or each instance of the fifth front side conductive line in the second group is configured to receive a control signal, an input signal, an output signal (as claimed in claim 15), in order to provide power distribution having an architecture to improve current-resistance drop, performance, and area efficiency of memory device (Chen, ¶0002, ¶0008, ¶0009, ¶0032).
Conclusion
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891