DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Status
Previous action: claims 11 through 20 rejected
Present action: claims 11 through 20 rejected.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s).
Claim(s) 11 through 16, 19, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ganesan (US 2021/0305162) in view of Gong (US 2016/0190041)
Regarding claim 11
Ganesan teaches:
A method for manufacturing an electronic package, comprising:
providing an electronic body (fig 5a:500a; [para 0042]) including a first side (fig 5d:570-2; [para 0045]) and a second side (fig 5f:570-1; [para 0046]) opposite to each other, wherein the electronic body (fig 5a:500a; [para 0042]) includes a base (fig 5a:514; [para 0042]) and a circuit portion (active layer; [para 0042]) formed on the base (fig 5a:514; [para 0042]), such that the base (fig 5a:514; [para 0042]) defines the second side (fig 5e:570-1), , and the base (fig 5a:514; [para 0042]) includes a plurality of conductive vias (fig 5a,5e:516; [para 0042]) connected with the circuit portion (active layer; [para 0042]) and exposed from the second side (fig 5e:570-1);
forming a plurality of metal pillars as first conductors (fig 5b,5e:592; [para 0043]) and a plurality of metal pillars as second conductors (fig 5f:598; [para 0047,0025]) on the first side (fig 5d:570-2; [para 0045]) and the second side (fig 5f:570-1; [para 0046]) of the electronic body (fig 5a:500a; [para 0042]), respectively, thereby connecting the first conductors (fig 5b,5e:592; [para 0043]) with the circuit portion (active layer; [para 0042]) and electrically connecting the second conductors (fig 5f:598; [para 0047,0025]) with the conductive vias (fig 5a,5e:516; [para 0042]);
forming a first insulating layer (fig 5c:594; [para 0044]) and a second insulating layer (fig 5g:595; [para 0048]) on the first side (fig 5d:570-2; [para 0045]) and the second side (fig 5f:570-1; [para 0046]) of the electronic body (fig 5a:500a; [para 0042]) and in contact with the first side (fig 5d:570-2; [para 0045]) and the second side (fig 5f:570-1; [para 0046]) of the electronic body (fig 5a:500a; [para 0042]), respectively, thereby encapsulating the first conductors (fig 5b,5e:592; [para 0043]) and the second conductors (fig 5f:598; [para 0047,0025]) by the first insulating layer (fig 5c:594; [para 0044]) and the second insulating layer (fig 5g:595; [para 0048]), respectively, to form an electronic structure (fig 5g:500g; [para 0048]), wherein the first conductors (fig 5b,5e:592; [para 0043]) are exposed (fig 5h) from the first insulating layer (fig 5c,5h:594; [para 0044]) and flush with a surface of the first insulating layer (fig 5c,5h:594; [para 0044]), and the first conductors (fig 5b,5e:592; [para 0043]) are combined with a plurality of conductive bumps (fig 6d:654; [para 0057]);
disposing the electronic structure (fig 6b,6e:100; [para 0055]) on a first circuit structure (fig 6e,6g:114-1; [para 0058]) disposed on a carrier board (fig 6c,6e:605; [para 0058,0059]) via the plurality of conductive bumps (fig 6d:654; [para 0057]), with a plurality of conductive pillars (fig 6a,6g:611,609; [para 0052]) being formed on the first circuit structure (fig 6e,6g:114-1; [para 0058]);
forming an encapsulating layer (fig 6c:630; [para 0056]) on the first circuit structure (fig 6e,6g:114-1; [para 0058]) for encapsulating the electronic structure (fig 6b,6e:100; [para 0055]) and the conductive pillars (fig 6a,6g:611,609; [para 0052]), wherein the encapsulating layer (fig 6c:630; [para 0056]) includes a first surface and a second surface opposite to each other, and the encapsulating layer (fig 6c,6e:630; [para 0056,0058]) is bonded to the first circuit structure (fig 6e,6g:114-1; [para 0058]) via the first surface;
and removing (fig 6f; [para 0059]) the carrier board (fig 6e,6f:605; [para 0059]).
Ganesan does not teach the circuit portion defines the first side of the base and is electrically connected to the first conductive via and first conductors.
Gong teaches:
wherein the electronic body (fig 4b:400; [para 0027]) includes a base (fig 4b:405; [para 0027]) and a circuit portion (fig 4b:450; [para 0032]) formed on the base (fig 4b:405; [para 0027]), such that the base (fig 4b:405; [para 0027]) defines the second side, and the circuit portion (fig 4b:450; [para 0032]) defines the first side, and the base (fig 4b:405; [para 0027]) includes a plurality of conductive vias (fig 4b:430; [para 0028]) electrically connected with the circuit portion (fig 4b:450; [para 0032]) and exposed from the second side; forming a plurality of metal pillars as first conductors (fig 4b:464; [para 0034]) on the first side of the electronic body (fig 4b:400; [para 0027]), thereby electrically connecting the first conductors (fig 4b:464; [para 0034]) with the circuit portion (fig 4b:450; [para 0032])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the circuit portion to define the first surface and be connected to the conductive vias and conductors in order that voltage can be redistributed to the appropriate locations of the surface (paragraph 5)
Regarding claim 12.
Ganesan in view of Gong teaches the method of claim 11, further
Ganesan teaches:
the second surface of the encapsulating layer (fig 6c,6g:630; [para 0056]) is flush with ends of the conductive pillars (fig 6a,6g:611,609; [para 0052]), the second insulating layer or the second conductors (fig 6a,6g:663; [para 0060]).
Regarding claim 13.
Ganesan in view of Gong teaches the method of claim 11, further
Ganesan teaches:
ends of the conductive pillars (fig 6a,6g:611,609; [para 0052]), the second insulating layer or the second conductors (fig 6a,6g:663; [para 0060]) are exposed from the second surface of the encapsulating layer (fig 6c,6g:630; [para 0056,0060]).
Regarding claim 14.
Ganesan in view of Gong teaches the method of claim 11, further
Ganesan teaches:
the plurality of conductive pillars (fig 6a,6g:611,609; [para 0052]) and the first conductors (fig 5b,5e:592; [para 0043]) of the electronic structure (fig 6b,6e:100; [para 0055]) are electrically connected with the first circuit structure (fig 6e,6g:114-1; [para 0058]).
Regarding claim 15.
Ganesan in view of Gong teaches the method of claim 14, further
Ganesan teaches:
the first conductors (fig 5b,5e:592; [para 0043]) are electrically connected with the first circuit structure (fig 6e,6g:114-1; [para 0058]) via the plurality of conductive bumps (fig 6d:654; [para 0057]).
Regarding claim 16.
Ganesan in view of Gong teaches the method of claim 11, further
Ganesan teaches:
after removing the carrier board (fig 6e,6f:605; [para 0059]), forming a plurality of conductive components (fig 6I; [para 0062]) on the first circuit structure (fig 6I:114-1; [para 0058]), thereby electrically connecting the plurality of conductive components (fig 6I; [para 0062]) with one or both of the conductive pillars (fig 6a,6g:611,609; [para 0052]) and the first conductors (fig 5b,5e:592; [para 0043]).
PNG
media_image1.png
279
583
media_image1.png
Greyscale
Regarding claim 19.
Ganesan in view of Gong teaches the method of claim 11, further
Ganesan teaches:
after removing the carrier (fig 6e,6f:605; [para 0059]), attaching an electronic component (fig 6I:606; [para 0062]) on the second surface of the encapsulating layer (fig 6I:630; [para 0061]), thereby electrically connecting the electronic component (fig 6I:606; [para 0062]) with one or both of the conductive pillars (fig 6I:611,609; [para 0062]) and the second conductors (fig 5f,6I:598; [para 0047]).
Regarding claim 20.
Ganesan in view of Gong teaches the method of claim 11, further
Ganesan teaches:
after disposing the electronic structure (fig 6b,6e:100; [para 0055]) on the carrier board (fig 6c,6d:605; [para 0058]), disposing an electronic component (fig 6e:114-2; [para 0058]) on the carrier board (fig 6c,6d:605; [para 0058]).
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ganesan (US 2021/0305162) in view of Gong (US 2016/0190041) as applied to claim 1 and further in view of Yu (US 2017/0263518).
Regarding claim 17.
Ganesan in view of Gong teaches the method of claim 11, above
Ganesan does not teach forming a second circuit structure on the second surface of the encapsulating layer.
Yu teaches:
before removing the carrier board (fig 13:54; [para 0029]), forming a second circuit structure (fig 14:60,62; [para 0031]) on the second surface of the encapsulating layer (fig 14:44; [para 0025]), thereby electrically connecting the second circuit structure (fig 14:60,62; [para 0031]) with the conductive pillars (fig 14:30; [para 0014]) and the second conductors (fig 14:58; [para 0030]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a second circuit structure in order that voltage can be redistributed to the appropriate locations of the surface (paragraph 26).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ganesan (US 2021/0305162) in view of Gong (US 2016/0190041) in view of Yu (US 2017/0263518) as applied to claim 17 and further in view of Chen (US 2014/0091471).
Regarding claim 18
Ganesan in view of Gong in view of Yu teaches the method of claim 17, above
Ganesan in view of Gong in view of Yu does not teach attaching an electronic component after removing the carrier
Chen teaches:
after removing the carrier (fig 12,13:910; [para 0036]), attaching an electronic component (fig 16:160; [para 0038]) on the second circuit structure (fig 16:110; [para 0038]), thereby electrically connecting the electronic component (fig 16:160; [para 0038]) with the second circuit structure (fig 16:110; [para 0038]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to attach an electronic component after removing the carrier in order to provide additional functions and utilities to the packaged device.
Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
Prosecution Insights