Prosecution Insights
Last updated: May 29, 2026
Application No. 18/623,879

ELECTRONIC PACKAGE, MANUFACTURING METHOD FOR THE SAME, AND ELECTRONIC STRUCTURE

Final Rejection §103
Filed
Apr 01, 2024
Priority
Aug 26, 2020 — TW 109129145 +1 more
Examiner
GOODWIN, DAVID J
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Siliconware Precision Industries Co. Ltd.
OA Round
4 (Final)
67%
Grant Probability
Favorable
5-6
OA Rounds
1y 0m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 67% — above average
67%
Career Allowance Rate
544 granted / 807 resolved
-0.6% vs TC avg
Strong +16% interview lift
Without
With
+16.3%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
36 currently pending
Career history
879
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
82.6%
+42.6% vs TC avg
§102
3.1%
-36.9% vs TC avg
§112
10.4%
-29.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 807 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 11 through 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hu (US 2013/0105213) in view of Shih (US 2018/0102311) in view of Tsou (US 2021/0375768) in view of Lin (US 2017/0162556) Regarding claim 11. Hu teaches a method for manufacturing an electronic package, comprising: providing an electronic body (fig 2d) including a first side and a second side (20b) opposite to each other (paragraph 28) (fig 2d), wherein the electronic body includes a base (20) and a circuit portion (21) formed on the base (20) (paragraph 27), such that the base (20) defines the second side (fig 2b,2c), and the circuit portion (21) defines the first side (fig 2d) (paragraph 28), and the base (20) includes a plurality of conductive vias (200) electrically connected with the circuit portion (21) and exposed from the second side (fig 2d) (paragraph 28); forming a plurality of first conductors (210) (fig 2d) (paragraph 27) and a plurality of second conductors (231,232) on the first side and the second side of the electronic body (fig 2h) (paragraph 37), respectively, thereby electrically connecting the first conductors with the circuit portion and electrically connecting the second conductors with the conductive vias (200) (fig 2h); PNG media_image1.png 224 612 media_image1.png Greyscale forming a first insulating layer (22) (paragraph 34) and a second insulating layer (230,24) (paragraph 40) on the first side and the second side of the electronic body (paragraph 36), and in contact with the first side and the second side of the electronic body, respectively, thereby encapsulating the first conductors (210) and the second conductors (231,232) by the first insulating layer (22) and the second insulating layer (23,24) (fig 2I”) (paragraph 40,41), respectively, to form an electronic structure, wherein the first conductors (210) are exposed from the first insulating layer (22) and flush with a surface of the first insulating layer (22) (fig 2I”) PNG media_image2.png 252 667 media_image2.png Greyscale Hu does not teach combining the first conductors with conductive bumps Shih teaches and the first conductors (208) are combined with a plurality of conductive bumps (210) (fig 3) (paragraph 27). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide conductive bumps in order to facilitate connection with a redistribution layer (Shih paragraph 47, fig 12) Hu does not teach conductive pillars and a carrier board. Tsou teaches disposing the electronic structure (405) on a first circuit structure (440) disposed on a carrier board (350), with a plurality of conductive pillars (486) being formed (fig 4a) (paragraph 50); forming an encapsulating layer (460) the electronic structure (405) and the conductive pillars (486) (fig 5), wherein the encapsulating layer (460) includes a first surface and a second surface opposite to each other (fig 5) (paragraph 52) and removing the carrier board (350) (fig 10) (paragraph 64) It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide conductive pillars in order provide fan out connectivity to subsequent devices (Tsou paragraph 48), it would have been obvious to one of ordinary skill in the art at the time of filing to provide a carrier in order to carry the structures during process. Hu does not teach the electronic structure is mounted to a first circuit structure via electronic bumps. Lin teaches disposing the electronic structure (23) on a first circuit structure (22) disposed on a carrier board (21) via the plurality of conductive bumps (25), with a plurality of conductive pillars (24) being formed on the first circuit structure (24) (paragraph 60) (fig 7); forming an encapsulating layer (27) on the first circuit structure (22) for encapsulating the electronic structure (23) and the conductive pillars (24), wherein the encapsulating layer (27) includes a first surface and a second surface opposite to each other, and the encapsulating layer (27) is bonded to the first circuit structure (22) via the first surface; and removing the carrier board (21) (fig 11). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a first circuit structure disposed on the carrier board in order to provide routing and redistribution without the need for providing a second carrier boards thereby eliminating the step of switching carrier boards, further it would have been obvious to one of ordinary skill in the art at the time of filing to use micro bumps to electrically couple first conductive elements to the routing circuitry (Lin paragraph 60). Regarding claim 12 Hu in view of Shih in view of Tsou in view of Lin teaches the structure of claim 11. Tsou teaches the second surface of the encapsulating layer (460) is flush with ends of the conductive pillars (486) (fig 5) (paragraph 53), the second insulating layer or the second conductors (428) (paragraph 34). Regarding claim 13. Hu in view of Shih in view of Tsou in view of Lin teaches the structure of claim 11. Tsou teaches ends of the conductive pillars (486), the second insulating layer or the second conductors (428) are exposed from the second surface of the encapsulating layer (460) (fig 5) (paragraph 53). Regarding claim 14. Hu in view of Shih in view of Tsou in view of Lin teaches the structure of claim 11. Tsou teaches the plurality of conductive pillars (486) and the first conductors (438) of the electronic structure (405) are electrically connected with the first circuit structure (440) (fig 11) (paragraph 66). Regarding claim 15. Hu in view of Shih in view of Tsou in view of Lin teaches the structure of claim 14. Tsou teaches the first conductors (438) are electrically connected with the first circuit structure (440) (fig 11) Lin teaches connecting with the first circuit structure via the plurality of conductive bumps (25) (fig 7) (paragraph 60). Regarding claim 16. Hu in view of Shih in view of Tsou in view of Lin teaches the structure of claim 11. Lin teaches after removing the carrier board (21) (fig 10,11), forming a plurality of conductive components (417) on the first circuit structure (22), thereby electrically connecting the plurality of conductive components (417) with one or both of the conductive pillars (24) and the first conductors (fig 19) (paragraph 70,71). It would have obvious to one of ordinary skill in the art to provide a plurality of conductive components in order to provide secondary traces that will fan out the circuitry and provide bonding sites (paragraph 79) Regarding claim 17. Hu in view of Shih in view of Tsou in view of Lin teaches the structure of claim 11. Tsou teaches before removing the carrier board (350), forming a second circuit structure (470) on the second surface of the encapsulating layer (460), thereby electrically connecting the second circuit structure with the conductive pillars (486) and the second conductors (428) (fig 6) (paragraph 54). Regarding claiming 18 Hu in view of Shih in view of Tsou in view of Lin teaches the structure of claim 17. Tsou teaches, after removing the carrier (350), attaching an electronic component (702) on the second circuit structure (470), thereby electrically connecting the electronic component (702) with the second circuit structure (470) (fig 8) (paragraph 59). Regarding claim 19 Hu in view of Shih in view of Tsou in view of Lin teaches the structure of claim 11. Lin teaches after removing the carrier (21) (fig 11), attaching an electronic component (53) on the second surface of the encapsulating layer (27) (fig 27), thereby electrically connecting the electronic component with one or both of the conductive pillars (24) and the second conductors (fig 27) (paragraph 82). PNG media_image3.png 172 320 media_image3.png Greyscale Regarding claim 20 Hu in view of Shih in view of Tsou in view of Lin teaches the structure of claim 11. Tsou teaches after disposing the electronic structure (405) on the carrier board (350), disposing an electronic component (701) on the carrier board (350) (fig 8) (paragraph 61). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide an electronic component in order to provide additional functionality, such as system on chip, to the package (Tsou paragraph 61) Response to Arguments Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely to the combination of references applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. The applicant argues that the prior art does not teach the currently amended claim. However, Hu (US 2013/0105213) in view of Shih (US 2018/0102311) in view of Tsou (US 2021/0375768) in view of Lin (US 2017/0162556) as applied above teaches the currently amended claim Newly applied reference Shih teaches the conductive bumps. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /D.J.G/Examiner, Art Unit 2817 /Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 December 5, 2025
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Prosecution Timeline

Show 2 earlier events
Oct 28, 2024
Non-Final Rejection mailed — §103
Jan 24, 2025
Response Filed
May 13, 2025
Final Rejection mailed — §103
Aug 13, 2025
Request for Continued Examination
Aug 14, 2025
Response after Non-Final Action
Dec 10, 2025
Non-Final Rejection mailed — §103
Mar 09, 2026
Response Filed
May 27, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
67%
Grant Probability
84%
With Interview (+16.3%)
3y 2m (~1y 0m remaining)
Median Time to Grant
High
PTA Risk
Based on 807 resolved cases by this examiner. Grant probability derived from career allowance rate.

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