DETAILED ACTION
This action is responsive to the following communications: the Amendment filed on December 22, 2025.
Claims 1-20 are pending. Claims 1, 8 and 17 are amended. Claims 1, 8 and 17 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 17 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Aritome et al. (US 20130033936).
Regarding independent claim 1, Aritome et al. disclose an operating method for controlling a NOR flash memory cell [the method for double level program verify can operate using a NAND memory array and can be used in other memory device architectures as well, para. 18. The connections of the cells to the bit lines determines whether the array is a NAND architecture, an AND architecture, or a NOR architecture, para. 39], the operating method comprising:
performing a first read operation to the memory cell according to a first verification voltage to obtain a first verification result [see Fig. 5, the Vt determination can be accomplished by performing two "read" operations at different word line voltages (e.g., LPV and PV), precharging the bit line, and evaluating its voltage after a read time. This determines the conductive state of the cell (e.g., if the bit line discharges or remains charged), para. 25. The dual verify levels (e.g., Program Verify (PV) and Low Program Verify (LPV)) generate three different voltage ranges into which the threshold voltage of the target memory cell will fall, para. 26];
performing a second read operation to the memory cell according to a second verification voltage less than the first verification voltage to obtain a second verification result [see Fig. 5, the Vt determination can be accomplished by performing two "read" operations at different word line voltages (e.g., LPV and PV), precharging the bit line, and evaluating its voltage after a read time. This determines the conductive state of the cell (e.g., if the bit line discharges or remains charged), para. 25. The dual verify levels (e.g., Program Verify (PV) and Low Program Verify (LPV)) generate three different voltage ranges into which the threshold voltage of the target memory cell will fall, para. 26. The LPV level could then be determined as some voltage that is less than PV, para. 27];
performing a program operation to the memory according to the first and second verification results [see Fig. 5, the location of the threshold voltage in relation to dual verify levels determines the subsequent bit line bias voltage for the bit line coupled to the target memory cell during a subsequent programming pulse, para. 26. After the new bit line voltage has been determined 511, 513, or 515, the bit line coupled to the target memory cell is biased at this voltage 517. Substantially simultaneously with the bit line being biased at the new Vbl, a programming voltage (e.g., programming pulse) is applied to the word line 519, para. 34], and a strength of the program operation being determined according to the second verification result [see Fig. 5, Aritome et al. use the compare to Low Program Verify (LPV) to choose how the next program is: if Vt < LPV, set bit line to 0V to enable full programming of the target memory cell (para. 28); if LPV < Vt <PV, set bit line to a variable voltage between 0 and Vcc (para. 29); if Vt > PV, inhibit programming with Vcc (para. 33). It further explains that the resulting Vt increase depends on the program pulse and Vbl, para. 34-35].
Regarding claim 2, Aritome et al. disclose when a threshold voltage of the memory cell is greater than or equal to the first verification voltage, a data information stored by the memory cell is set to a first value [if the determined threshold voltage is greater than or equal to the PV level 509, the target memory cell is considered to be programmed and should be inhibited from further programming, para. 33] and
when the threshold voltage of the memory cell is less than the first verification voltage, the data information stored by the memory cell is set to a second value [if the determined threshold voltage is less than to the PV level 509 (Vt < LPV or LPV < Vt <PV), the method teats the cell as not yet programmed to target and choose non inhibit bit line biases to continue programming, para. 28-29].
Regarding claim 3, Aritome et al. disclose when the data information stored by the memory cell is the second value, it is set for the program operation to be performed on the memory cell [if the determined threshold voltage is less than to the PV level 509 (Vt < LPV or LPV < Vt <PV), the method teats the cell as not yet programmed to target and choose non inhibit bit line biases to continue programming, para. 28-29. After selecting the new bit line voltage, the bit line is biased and a programming voltage is applied to the word line, para. 34].
Regarding claim 4, Aritome et al. disclose when a threshold voltage of the memory cell is greater than or equal to the second verification voltage, the strength of the program operation is set to a first strength [see Fig. 5, if LPV < Vt <PV, set bit line to a variable voltage between 0 and Vcc, para. 29], and
when the threshold voltage of the memory cell is less than the second verification voltage, the strength of the program operation is set to a second strength greater than the first strength [see Fig. 5, if Vt < LPV, set bit line to 0V to enable full programming of the target memory cell, para. 28. FIG. 6A shows that the memory cells with threshold voltages less than LPV are moved up faster than the memory cells with threshold voltages between LPV and PV, para. 37].
Regarding claim 5, Aritome et al. disclose the strength of the program operation is controlled by at least one of a program voltage and a program time [the threshold voltage of the target memory cell then increases by an amount that is determined by the programming pulse voltage and by Vbl, para. 34. FIG. 6A shows that the memory cells with threshold voltages less than LPV are moved up faster than the memory cells with threshold voltages between LPV and PV. The width of such a resulting distribution is tighter than a distribution obtained without changing the programming rate of memory cells through dual program verify and variable bit line biasing that progressively reduces the effective program pulse as a result of the increasing bit line voltage, para. 37].
Regarding independent claim 17, Aritome et al. disclose a memory system [Fig. 7: 720], configured to control operations of a NOR flash memory cell [Fig. 7: 730, the method for double level program verify can operate using a NAND memory array and can be used in other memory device architectures as well, para. 18. The connections of the cells to the bit lines determines whether the array is a NAND architecture, an AND architecture, or a NOR architecture, para. 39], the memory system comprising:
a memory array [Fig. 7: 730] comprising a memory cell [the memory device 700 includes an array 730 of non-volatile memory cells, para. 39];
a controller [Fig. 7: 770] coupled to the memory array [para. 42] and configured to:
perform a first read operation to the memory cell according to a first verification voltage to obtain a first verification result [see Fig. 5, the Vt determination can be accomplished by performing two "read" operations at different word line voltages (e.g., LPV and PV), precharging the bit line, and evaluating its voltage after a read time. This determines the conductive state of the cell (e.g., if the bit line discharges or remains charged), para. 25. The dual verify levels (e.g., Program Verify (PV) and Low Program Verify (LPV)) generate three different voltage ranges into which the threshold voltage of the target memory cell will fall, para. 26];
perform a second read operation to the memory cell according to a second verification voltage less than the first verification voltage to obtain a second verification result [see Fig. 5, the Vt determination can be accomplished by performing two "read" operations at different word line voltages (e.g., LPV and PV), precharging the bit line, and evaluating its voltage after a read time. This determines the conductive state of the cell (e.g., if the bit line discharges or remains charged), para. 25. The dual verify levels (e.g., Program Verify (PV) and Low Program Verify (LPV)) generate three different voltage ranges into which the threshold voltage of the target memory cell will fall, para. 26. The LPV level could then be determined as some voltage that is less than PV, para. 27]; and
perform a program operation to the memory according to the first and second verification results [see Fig. 5, the location of the threshold voltage in relation to dual verify levels determines the subsequent bit line bias voltage for the bit line coupled to the target memory cell during a subsequent programming pulse, para. 26. After the new bit line voltage has been determined 511, 513, or 515, the bit line coupled to the target memory cell is biased at this voltage 517. Substantially simultaneously with the bit line being biased at the new Vbl, a programming voltage (e.g., programming pulse) is applied to the word line 519, para. 34], and a strength of the program operation being determined according to the second verification result [see Fig. 5, Aritome et al. use the compare to Low Program Verify (LPV) to choose how the next program is: if Vt < LPV, set bit line to 0V to enable full programming of the target memory cell (para. 28); if LPV < Vt <PV, set bit line to a variable voltage between 0 and Vcc (para. 29); if Vt > PV, inhibit programming with Vcc (para. 33). It further explains that the resulting Vt increase depends on the program pulse and Vbl, para. 34-35]; and
a program circuit [Fig. 7: 710] coupled to the controller [a controller (e.g., control circuitry) 770 decodes signals provided on control connections 772 from the processor 710, para. 42] and configured to provide a program signal having a first strength or a second strength greater than the first strength to the memory cell according to the first and second verification results [FIG. 6A shows that the memory cells with threshold voltages less than LPV are moved up faster than the memory cells with threshold voltages between LPV and PV, para. 37].
Regarding claim 20, Aritome et al. disclose the strength of the program operation is controlled by at least one of a program voltage and a program time of the program signal [the threshold voltage of the target memory cell then increases by an amount that is determined by the programming pulse voltage and by Vbl, para. 34. FIG. 6A shows that the memory cells with threshold voltages less than LPV are moved up faster than the memory cells with threshold voltages between LPV and PV. The width of such a resulting distribution is tighter than a distribution obtained without changing the programming rate of memory cells through dual program verify and variable bit line biasing that progressively reduces the effective program pulse as a result of the increasing bit line voltage, para. 37].
Claims 8-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi (US 20040066685).
Regarding independent claim 8, Choi disclose an operating method for controlling NOR flash memory cells [see Fig. 3, a NOR-type flash memory device includes the cell array 110 shown in FIG. 3 corresponds to a sector or a block, para. 39], the operating method comprising:
performing a first read operation to memory cells in a first area according to a first verification voltage to obtain a first verification result [see Fig. 4, Choi describes the flash memory cells in a given sector are simultaneously erased using the NGBE erase verification. The erase verification operation is carried out in the same manner as the read operation except that the bias condition of the erase verification operation is different from that of the read operation para. 44-46]; and
performing an erase operation to the memory cells in the first area [Fig. 4: step 12, Choi performs NGBE erase using a voltage Vg of -10V is applied to the control gates of all flash memory cells in the sector (or word lines therein), and a voltage Vb of +6V is applied to the bulk (substrate), para. 45], and a strength of the erase operation being determined according to the first verification result [the verification operation checks whether the threshold voltages of flash memory cells selected by the initially set row and column addresses are distributed in the target threshold voltage range (+1V to +3V), para. 46].
Regarding claim 9, Choi discloses the strength of the erase operation is controlled by at least one of an erase voltage and an erase time [the NGBE operation is performed under the following bias condition: a voltage Vg of -10V is applied to the control gates of all flash memory cells in the sector (or word lines therein), and a voltage Vb of +6V is applied to the bulk (substrate), para. 45. Choi also states after a predetermined time under that NGBE bias condition (e.g., Vg=-10V, Vb=+6V), the erase verification operation is carried out under the following verification bias condition, e.g., Vg=+3V, Vd=+5V, Vs=0V, and Vb=0V, para. 46].
Regarding claim 10, Yang discloses when a largest threshold voltage of the memory cells in the first area is greater than or equal to the first verification voltage, the strength of the erase operation is set to a first strength [If at least one of the selected cells has its threshold voltage higher than the maximum value, the P/F check & control logic 200 checks whether the value PC of the loop counter 170 is equal to its maximum value PCmax (step 18). When the value PC is equal to the maximum value PCmax, the erase operation ends as an erase fail, para. 47], and
when the largest threshold voltage of the memory cells in the first area is less than the first verification voltage, the strength of the erase operation is set to a second strength less than the first strength [If the selected memory cells have their threshold voltages equal to or less than the maximum value (+3V) of the target threshold voltage range corresponding to the on cell (step 16) the P/F check & control logic 190 checks whether or not the value Y of the Y-counter 150 is equal to its maximum value Ymax (step 24). If the value Y is equal to the maximum value Ymax, the value X is checked to determine whether it has reached the maximum value Xmax (step 28). If the value X is equal to the maximum value Xmax, the erase operation ends as erase pass, para. 49].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-7 are rejected under 35 U.S.C. 103 as being unpatentable over Aritome et al. (US 20130033936) as applied to claim 1 and 17 above, and in view of Hemink et al. (US 6888758).
Regarding claim 6, Aritome et al. teach the limitation with respect to claim 1.
However, Aritome et al. are silent with respect to after the program operation, a third read operation is performed to the memory cell according to a third verification voltage between the first and second verification voltages to obtain a third verification result,
a preprogram operation is performed to the memory cell according to the third verification result, and a strength of the preprogram operation is determined according to the third verification result.
Hermink et al. teach after the program operation, a third read operation is performed to the memory cell according to a third verification voltage between the first and second verification voltages to obtain a third verification result [Fig. 15-16 showing three verify levels Vver1, Vver2 and Vver3, para. 49],
a preprogram operation is performed to the memory cell according to the third verification result, and a strength of the preprogram operation is determined according to the third verification result [see Fig. 15-16, para. 49].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Aritome et al. to the teaching of Hermink et al. such that modifying NOR flash memory of Aritome et al. by performing Hermink et al.’s third verify between the first and second verify levels after dual verify operation as taught by Aritome et al. and executing a preprogram whose strength is selected by third verification result to narrow the programmed threshold voltage distribution and get predictable outcomes.
Regarding claim 7, Aritome et al. in combination with Hermink et al. teach the limitation with respect to claim 6.
Furthermore, Hermink et al. teach when the threshold voltage of the memory cell is greater than or equal to the third verification voltage, the strength of the preprogram operation is set to a third strength [see Fig. 15-16, memory cells that have a threshold voltage in between Vver1 and Vver2 are slowed down by applying an intermediate bit line voltage of V1 during the subsequent programming step and are fully inhibited after that so that only one program impulse with bit line at V1 is performed], and
when the threshold voltage of the memory cell is less than the third verification voltage, the strength of the preprogram operation is set to a fourth strength greater than the third strength [see Fig. 15-16, memory cells that have their threshold voltage in between Vver3 and Vver2 during a verify operation are slowed down by applying an intermediate bit line voltage V2 during the subsequent programming step, wherein V2 and V1 are chosen in such a way that the threshold voltage shift on the next programming pulse is equal to one-third of the program step if the memory cell has just passed Vver2 and two-thirds of the program step if the memory step has just passed Vver3, para. 49].
Claims 11-14 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20040066685) as applied to claim 8 above, and in view of Choy et al. (US 20120201082).
Regarding claim 11, Choi teaches the limitation with respect to claim 8 above.
However, Choi is silent with respect to before the erase operation, a second read operation is performed to at least one selected memory cell according to a second verification voltage to obtain a second verification result, and
a preprogram operation is performed to the at least one selected memory cell coupled to a same word line in the first area, and a strength of the preprogram operation is determined according to the second verification result.
Choy et al. teach before the erase operation [see Fig. 3], a second read operation is performed to at least one selected memory cell according to a second verification voltage to obtain a second verification result [Fig. 3: step 301, during the preprogram verify test, the threshold voltage Vt of one or more memory cells is compared with a program verify threshold (PVT) voltage. If Vt is below the PVT voltage, perform a preprogramming of one or more memory cells in which a program pulse of a selected voltage level is applied to the memory cell(s) to increase Vt; otherwise pass, para. 21] and
a preprogram operation is performed to the at least one selected memory cell coupled to a same word line in the first area [Fig. 3: step 303, performing a preprogram of one or more memory cells which have failed the preprogram verify test on a per-page basis in which each page includes a selected number of memory cells or bits, para. 21], and a strength of the preprogram operation is determined according to the second verification result [if Vt is below the PVT voltage, perform a preprogramming of one or more memory cells in which a program pulse of a selected voltage level is applied to the memory cell(s) to increase Vt; otherwise pass if Vt is above PVT, para. 21].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Choy et al. to the teaching of Choi such that modifying Choi’s NOR flash memory device by applying a preprogram-verify on the page before Choi’s erase operation and then executing a preprogram step on the selected memory cell with the preprogram strength according to that verify result as taught by Choy et al. to reduce over erasure, tighten the threshold voltage distribution, and shorten erase time [see Choy et al.’s Abstract and para. 2].
Regarding claim 12, Choi in combination with Choy et al. teach the limitation with respect to claim 11.
Furthermore, Choy et al. disclose when a largest threshold voltage of the at least one selected memory cell coupled to the same word line in the first area is greater than or equal to the second verification voltage, the strength of the preprogram operation is set to a third strength [if Vt is above PVT, no pulse voltage on passing cells, para. 21], and
when the largest threshold voltage of the at least one selected memory cell coupled to the same word line in the first area is less than the second verification voltage, the strength of the preprogram operation is set to a fourth strength greater than the third strength [If Vt is below the PVT voltage, perform a preprogramming of one or more memory cells in which a program pulse of a selected voltage level is applied to the memory cell(s) to increase Vt. The flow loops 301-303 apply additional pulses until each relevant cell reaches PVT, para. 21].
Regarding claim 13, Choi teaches the limitation with respect to claim 8 above.
However, Choi is silent with respect to after the erase operation, a third read operation is performed to a selected memory cell according to a third verification voltage to obtain a third verification result, and
a soft program operation is performed to the selected memory cell in the first area, and a strength of the soft program operation is determined according to the third verification result.
Choy et al. teach after the erase operation [see Fig. 3], a third read operation is performed to a selected memory cell according to a third verification voltage to obtain a third verification result [Fig. 3: step 309, performing a soft program verify test comparing Vt to a soft program verify threshold (SPVT) voltage. If Vt is below SPVT, it branches to apply a soft program pulse to one or more of the memory cells 209 which fail the soft program verify test, para. 25], and
a soft program operation is performed to the selected memory cell in the first area [Fig. 13: step 311, applying a soft program pulse to one or more of the memory cells 209 which fail the soft program verify test, para. 25], and a strength of the soft program operation is determined according to the third verification result [If Vt is below SPVT, it branches to apply a soft program pulse to one or more of the memory cells 209 which fail the soft program verify test. The soft program pulse has a selected voltage level and duration to increase Vt above SPVT while remaining below EVT, para. 25].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of Choy et al. to the teaching of Choi such that modifying Choi’s NOR flash memory device by applying a soft program operation on the page after Choi’s erase operation and then executing a soft program step on the selected memory cell with the soft program strength according to that verify result as taught by Choy et al. to reduce over erasure, tighten the threshold voltage distribution, and shorten erase time [see Choy et al.’s Abstract and para. 2].
Regarding claim 14, Choi in combination with Choy et al. teach the limitation with respect to claim 13.
Furthermore, Choy et al. disclose when a threshold voltage of the selected memory cell is greater than or equal to the third verification voltage, the strength of the soft program operation is set to a fifth strength [if Vt is above SPVT, no soft program pulse on passing cells, para. 25], and
when the threshold voltage of the selected memory cell is less than the third verification voltage, the strength of the soft program operation is set to a sixth strength greater than the fifth strength [if Vt is below SPVT, it branches to apply a soft program pulse to one or more of the memory cells 209 which fail the soft program verify test. Operation loops between steps 309 and 311 by applying additional soft program pulses until Vt of each memory cell 209 of the memory block 202 is between the SPVT and EVT voltages, para. 25].
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 20040066685) as applied to claim 8 above, and in view of So et al. (US 20030021149).
Regarding claim 15, Choi teaches the limitation with respect to claim 8 above.
However, Choi is silent with respect to after the erase operation, a fourth read operation is performed to a programmed memory cell in a second area outside the first area according to a fourth verification voltage to obtain a fourth verification result,
a refresh program operation is performed to the programmed memory cell in the second area, and a strength of the refresh program operation is determined according to the fourth verification result.
So et al. teach a fourth read operation is performed to a programmed memory cell in a second area outside the first area according to a fourth verification voltage to obtain a fourth verification result [during read stage 330, the controller performs multiple comparisons to locate voltage VR, a verification reference that bounds the cell’s threshold. Voltage VR at the end of read stage 330 indicates the upper bound of either an allowed state or a forbidden zone containing the threshold voltage of the target memory cell, para. 29-30. A refresh operation is performed on an identified sector, corrected data may be buffered or written to another sector, para. 37-39],
a refresh program operation is performed to the programmed memory cell in the second area [if voltage VR is the upper bound of a forbidden zone, a refresh stage 340 of the read/refresh process begins. During refresh stage 340, programming cycles 310 and verify cycles 320 raise the threshold voltage of the target memory cell to the next higher threshold voltage state, para. 30-31], and a strength of the refresh program operation is determined according to the fourth verification result [only if voltage VR is the upper bound of a forbidden zone, a refresh stage 340 begins; otherwise, no refresh is applied, para. 30. During refresh page 340, programming cycles 310 continue until a verify cycle 320 indicates that the threshold voltage of the target cell has reached the level of reference voltage, para. 31].
It would have been obvious for a person having ordinary skill in the art before the effective filling date of claimed invention to apply teachings of So et al. to the teaching of Choi such that modifying Choi’s NOR flash memory device by applying in a second area a read-verify operation after Choi’s erase operation in a first area and then executing a refresh program operation that strength is selected according to that verify result as taught by So et al. to maintain data integrity and tighten threshold voltage distribution.
Regarding claim 16, Choi in combination with So et al. teach the limitation with respect to claim 15.
Furthermore, So et al. disclose when a threshold voltage of the programmed memory cell is greater than or equal to the fourth verification voltage, the strength of the refresh program operation is set to a seventh strength [if voltage VR is the upper bound of an allowed threshold voltage state at the end of read stage 330, the read/refresh process is complete, no refresh is required, para. 30], and
when the threshold voltage of the programmed memory cell in the second area is less than the fourth verification voltage, the refresh program operation is set to an eighth strength greater than the seventh strength [if voltage VR is the upper bound of a forbidden zone, a refresh stage 340 begins. During refresh page 340, programming cycles 310 continue until a verify cycle 320 indicates that the threshold voltage of the target cell has reached the level of reference voltage, para. 30-31].
Allowable Subject Matter
Claims 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 18, the closest prior art, Aritome et al. (US 20130033936), which shows, in Figure 7 that describes the memory device 700 includes an array 730 of non-volatile memory cells, such as the one illustrated previously in FIG. 4. The memory array 730 is arranged in banks of word line rows and bit line columns. In one embodiment, the columns of the memory array 730 are comprised of series strings of memory cells. A controller (e.g., control circuitry) 770 decodes signals provided on control connections 772 from the processor 710. These signals are used to control the operations on the memory array 730, including data read, data write (program), and erase operations [para. 39-42]. However, Aritome et al. do not disclose a first switch circuit configured to selectively provide a first program signal having the first strength to the memory cell through a bit line and a second switch circuit configured to selectively provide a second program signal having the second strength to the memory cell through the bit line. Aritome et al. also do not disclose a logic circuit coupled to the first and second switches, and configured to control the first and second switches to allow one of the first and second program signals to the memory cell through the bit line according to the first and second verification results. Or as claims, there is no teaching or suggestion in the prior art of record to provide the recited of the program circuit comprises: a first switch circuit configured to selectively provide a first program signal having the first strength to the memory cell through a bit line; a second switch circuit configured to selectively provide a second program signal having the second strength to the memory cell through the bit line; and a logic circuit coupled to the first and second switches, and configured to control the first and second switches to allow one of the first and second program signals to the memory cell through the bit line according to the first and second verification results.
Response to Arguments
Applicant’s arguments with respect to claims 1, 8 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
In passing, applicant argues the difference between the claimed invention and Kim et al (US 20080298133) is that Kim is for NAND memory and the claimed invention is for NOR memory. This argument is not persuasive because, in the memory industry, it is well established that NAND and NOR are obvious variants, albeit having various differences and recognized advantages and disadvantages (e.g., M-Systems “Two Flash Technologies Compared: NOR vs. NAND”). Regardless, new prior art is applied and these arguments are now moot.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825