DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention I, Species I, Modification A in the reply filed on 7/2/2026 is acknowledged.
Claim 5 is withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/2/2026.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng et al. US 20200044060 A1 (hereinafter referred to as Cheng), in view of Frougier et al. US 9991352 B1 (hereinafter referred to as Frougier).
Regarding claim 1, Cheng teaches
A semiconductor device (“GAA FET device” para. 0040 FIG. 1A), comprising:
a channel structure (uppermost “semiconductor wire 20” para. 0041)
a dielectric structure (“gate dielectric layer 104” para. 0042) surrounding the channel structure;
a gate structure (“gate electrode layer 108” para. 0042) surrounding the dielectric structure;
a first conductive structure (“source/drain epitaxial layer 80” on the left) disposed below the channel structure and embedded in the channel structure (“source/drain epitaxial layer 80” is predominantly below the uppermost “semiconductor wire 20” and has a portion in the V or U shaped concavity of “semiconductor wire 20”, para. 0043); and
a second conductive structure (“source/drain epitaxial layer 80” on the right) disposed on the channel structure and embedded in the channel structure (“source/drain epitaxial layer 80” on the right has a portion in the concavity of “semiconductor wire 20”).
However, Cheng fails to teach the channel structure having a H-shape profile.
Nevertheless, Frougier teaches
the channel structure having a H-shape profile (“channel semiconductor layer 108C” is trimmed and resembles an H shape with sloped inner sides, col 10 lines 49-56 FIG. 12-16).
Cheng and Frougier teach gate-all-around finFETs. The “channel semiconductor layer 108C” is thinned in a middle region so that larger gaps are formed between adjacent “channel semiconductor material layers 108” so that more gate material can be formed (col 11 lines 39-42). Maintaining the original thickness for portions in contact with the “epi source/drain regions 118” reduces the resistance in those regions; dopants from “epi source/drain regions 118” are driven into the “first and second non-trimmed initial thickness portions 108X” of the “channel semiconductor material layers 108”, forming extension regions with greater surface area than in regular channels (col 12 lines 20-26 and 30-51). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that a plurality of “semiconductor wire 20” with thinned inner regions and untrimmed outer regions allow for a greater amount of gate material to form around them while maintaining a desired electrical performance of the “semiconductor wire 20”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the channel structure in Cheng with the H-shape taught in Frougier. A channel with an H-shape can have a reduced resistance in the region with greater thickness while the middle portion with lesser thickness can be surrounded by more gate material.
Regarding claim 2, Cheng teaches the semiconductor device of claim 1, wherein each of the first conductive structure and the second conductive structure is partially embedded in the channel structure (both “source/drain epitaxial layer 80” have portions embedded into the V or U shaped concave portions of “semiconductor wire 20”).
Regarding claim 3, Cheng teaches the semiconductor device of claim 1, wherein the first conductive structure is symmetrical to the second conductive structure with respect to the channel structure (the “source/drain epitaxial layers 80” are disposed on opposite sides of uppermost “semiconductor wire 20” and can be considered symmetrically disposed).
Regarding claim 4, Cheng teaches the semiconductor device of claim 1, wherein each of the first conductive structure and the second conductive structure is embedded in a concave portion of the H-shape profile of the channel structure (both “source/drain epitaxial layer 80” have portions embedded into the V or U shaped concave portions of “semiconductor wire 20”).
Regarding claim 6, Cheng teaches the semiconductor device of claim 1, wherein maximum length of the channel structure is smaller than a length of the dielectric structure.
Nevertheless, FIG. 26A-26B and 31A-31B in Cheng show how “semiconductor wires 20” extending in the X direction and the “gate dielectric layer 104” extends in the Y direction. Their lengths are not described but it is clear that three possibilities exist: the “semiconductor wires 20” is longer, the “gate dielectric layer 104” is longer, or they are equal. In all three cases, a transistor is formed with “gate dielectric layer 104” isolating the “semiconductor wires 20” from “gate electrode layer 108”. The examiner understands that the length of the channel will affect the electrical performance of the transistor. Furthermore, FIG. 5-10 show two “fin structures 30” upon which the “sacrificial gate structure 50” is formed, but there may be any number of “fin structures 30” (para. 0073). Though later figures only one “fin structure 30”, the examiner understands that the “gate structure 100” can be formed over a plurality of “fin structures 30”. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the differences in length between “semiconductor wire 20” and “gate dielectric layer 104” will depend on the desired channel length and the amount of “fin structures 30”. It is reasonable to expect that the length of “gate dielectric layer 1064” is greater than the length of “semiconductor wire 20” when “gate structure 100” is applied to a plurality of “fin structures 30”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the maximum length of the channel may be smaller than the length of the gate dielectric structure. It is obvious to try as being one of three predictable solutions that reasonably lead to a successfully formed semiconductor device (see. MPEP 2143.I.E). Furthermore, the channel structure length is chosen based on desired performance and the gate dielectric structure may be applied to multiple fin structures, increasing its length.
Regarding claim 9, Cheng teaches the semiconductor device of claim 1, wherein a material of the gate structure comprises aluminum, chromium, copper, tantalum, tungsten, polysilicon, or combinations thereof (“gate electrode layer 108” comprises polysilicon, aluminum, copper, titanium, tantalum, tungsten, or other conductors, para. 0110).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng, modified by Frougier, as applied to claim 1, in view of Dewey et al. US 20190058043 A1 (hereinafter referred to as Dewey)
Cheng, modified by Frougier, teach the semiconductor device of claim 1 but fail to teach wherein a material of the channel structure comprises oxide.
Nevertheless, Dewey teaches “channel material 102” made of tin oxide, indium oxide, titanium oxide, or other oxides (para. 0022 FIG.11A-11B). These are taught as being high mobility oxide semiconductor materials, such that their performance is improved relative to other materials (para. 0014). Meanwhile, the “semiconductor wire 20” in Cheng comprises silicon germanium (para. 0041). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that oxide semiconductors are desirable channel materials due to their high carrier mobility.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Cheng and Frougier with the oxide taught in Dewey. Oxide semiconductors have high carrier mobility and provide improved device performance.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng, modified by Frougier, as applied to claim 1, in view of Jambunathan et al. US 20180358436 A1 (hereinafter referred to as Jambunathan).
Cheng, modified by Frougier, teaches the semiconductor device of claim 1 but fails to teach wherein a material of each of the first conductive structure and the second conductive structure comprises molybdenum, niobium, tantalum, tungsten, or combinations thereof.
Nevertheless, Jambunathan teaches wherein a material of each of the first conductive structure (left side “source/drain structure 124” with “source/drain contact structure 144”, para. 0041 FIG. 11) and the second conductive structure (right side “source/drain structure 124” with “source/drain contact structure 144”) comprises molybdenum, niobium, tantalum, tungsten, or combinations thereof (“source/drain contact structure 144” comprises a metal such as tungsten, para. 0041).
Cheng, modified by Frougier, and Jambunathan teach gate-all-around transistors. Frougier teaches the formation of source/drain contact structures but is silent on their material composition. Jambunathan teaches tungsten as a metal for use as “source/drain contact structures 144”. The examiner understands that source/drain contacts are what provide signal to the source/drain from the outside. One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that “source/drain contact structures 144” can be used to send and receive signals to and from the “GAA FET device” in Cheng.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Cheng and Frougier with the tugnsten source/drain contacts taught in Jambunathan. Source/drain contacts provide the source and drain signals to and from the device and can be made of metal such as tungsten.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng, modified by Frougier, as applied to claim 1, in view of Lilak et al. US 20200194435 A1 (hereinafter referred to as Lilak).
Cheng, modified by Frougier, teaches the semiconductor device of claim 1 but fails to teach further comprising: a capacitor electrically connected to the first conductive structure or the second conductive structure.
Nevertheless, Lilak teaches a “MIM capacitor 121” and a FinFet “transistor 131” with a common “metal electrode 141” operating as a memory cell (para. 0034 FIG. 1(a)-1(c)). The “transistor 131” is the selector that controls the access the the “MIM capacitor 121”, the storage cell (para. 0002). One of ordinary skill in the art before the effective filing date of the claimed invention would have recognized that the “source/drain epitaxial layer 80” of “GAA FET device” can be connected to a storage cell such as “MIM capacitor 121” to form a memory device.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the semiconductor device taught between Cheng and Fougrier with the capacitor in Lilak. A capacitor in contact with the first or second conductive structure can operate as a storage cell, such that the transistor and the capacitor work together as a memory cell.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC MULERO FLORES whose telephone number is (571)270-0070. The examiner can normally be reached Mon-Fri 8am-5pm (typically).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC MANUEL MULERO FLORES/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898
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