DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Election/Restrictions
1. Applicant's election with traverse of Species II, claims 11-20 in the reply filed on 7/3/2026 is acknowledged. The traversal is on the ground(s) that the disclosed species are not patentably distinct; they are complementary descriptions of a single, integrated display device”. This is found persuasive, and the Restriction Requirement is withdrawn.
Drawings
2. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “a scan line connected to…and the dummy line are positioned in a same electrode layer” (claim 11) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
3. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In particular, claim 1 cites “the dummy line is positioned between a first insulating layer and a second insulating layer” is not clear because of positions of first/second insulating layers. The claim early includes display area and non-display area, but does not clearly specify in which area(s) the first/second insulating layers formed and how they relate to each other. For best understanding & examination purpose, Figs. 15A-B will be used to consider positions of the first/second insulating layers.
Claim 2 cites “a third insulating layer positioned on the second insulating layer” is not clear because, reading into claim 1, the claim does not clearly specify in which area(s) the third insulating layer formed.
The above reasons are also applied to claims 16 & 17.
Claim 9 cites “a scan line connected to the oxide semiconductor transistor is positioned in a same electrode layer as the dummy line” is not clear. Reading in prior claims, the dummy line positioned in non-display area, between first/second insulating layers, and the transistor positioned in display area, it is not clear how the scan line positioned in same electrode layer as the dummy line since the claim does not clearly specify a particular of the scan line and positional relationship between the scan line with other claimed features. For best understand and examination purpose, the scan line and dummy line are considered in same level or formed of same layer.
Claim 11 cites “a scan line connected to the oxide semiconductor transistor and the dummy line are positioned in a same electrode layer” is not clear. (1) The claim does not clearly define in which area(s) of the substrate, the scan line is formed; (2) shown in Fig. 15A, dummy line (DML) positioned in/on an insulating layer, it is not clear how the scan line and the dummy line positioned in a same electrode layer. For best understanding and examination purpose, that they are positioned in/on a same level/layer.
Claim 12 cites “a vertical distance between the scan line connected to the oxide semiconductor transistor and the substrate is largest among vertical distance between scan lines connected to the outer pixels and the substrate” is not clear. Reading into claim 11, each of outer pixels includes transistors including at least one oxide semiconductor transistor. A scan line connected to a transistor also it connected to an outer pixel. It is not since the claim does not clearly specify positions of “scan lines” and how they connected to or not connected transistors, different from oxide semiconductor transistor, in outer pixels in order to determine the largest vertical distance among vertical distances.
Claims 2-10 & 12-20 are rejected as being dependent on claims 1 & 11.
Applicant is suggested to revise and clarify the claims to avoid any further confusions.
For best understanding and examination purpose, the claims will be best considered based on drawings, disclosure, and/or any applicable prior arts.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 1-5, 7 and 8 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 2023/0217734).
Re claim 1, Lee teaches, under BRI, Figs. 1-2, [0048, 0050, 0052, 0076, 0077, 0087, 0097, 0104], a display device comprising:
-a substrate (SUB) including a display area (AA) and a non-display area (IA);
-outer pixels (P) positioned in the display area (AA)and positioned in a first direction (lateral or x-axis) from an edge of the substrate (SUB);
-dummy holes (TR, indicated) positioned in the non-display area (IA) and positioned between the edge of the substrate (SUB) and the outer pixels (P); and
-a dummy line (SP) positioned in the non-display area (IA) and extending in a second direction (vertical or y-axis) different from the first direction between the dummy holes (TR, indicated),
wherein the dummy line (SP) is positioned between (e.g., top view) a first insulating layer (BN) and a second insulating layer (PLN), and
the dummy holes (TR, indicated) pass through the first insulating layer (BN) and the second insulating layer (PLN).
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Re claim 2, Lee teaches, Fig. 2, [0100], a third insulating layer (PAS1) positioned on the second insulating layer (BN), wherein the dummy holes include a portion of the third insulating layer (PAS1) therein.
Re claim 3, Lee teaches, Fig. 2, wherein the dummy holes (indicated) do not include an electrode material therein.
Re claim 4, Lee teaches, under BRI, Fig. 2, wherein one end of the dummy line (SP) is connected (through between layers) to a first power line (CPL or PL) in an area adjacent to a first corner of the substrate (SUB), and an other end of the dummy line (SP) is connected (through between layers) to the first power line (CPL or PL) in an area adjacent to a second corner of the substrate (SUB).
Re claim 5, Lee teaches, under BRI, Fig. 2, wherein other portions (center portions) of the dummy line (SP) except the one end of the dummy line and the other end of the dummy are not connected (not directly connected) to the first power line (CPL or PL).
Re claim 7, Lee teaches, [0078-0079], wherein each of the outer pixels (P) includes transistors (T), and at least one of the transistors is an oxide semiconductors transistor (e.g., oxide-based semiconductor material).
Re claim 8, Lee teaches, Fig. 2, wherein the oxide semiconductor transistor is a transistor (T) positioned most adjacent to the edge of the substrate (SUB) among the transistors.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 9, 11 and 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Ha et al. (US 2021/0134924).
The teachings of Lee have been discussed above.
Re claim 9, Lee teaches, Fig. 1, a scan line (SL) connected to the oxide semiconductor transistor (of pixel).
Lee does not explicitly teach the scan line is positioned in a same electrode layer as the dummy line.
Ha teaches, Fig. 5, plurality of lines (SL) positioned in a same electrode layer.
As taught by Ha, one of ordinary skill in the art would utilize & modify the above teaching to obtain the scan line is positioned in a same electrode layer as the dummy line as claimed, because it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Ha in combination Lee due to above reason.
Re claim 11, Lee teaches, under BRI, Figs. 1-2, [0048, 0050, 0052, 0060, 0076, 0077-0079 0087, 0097, 0104], a display device comprising:
-a substrate (SUB) including a display area (AA) and a non-display area (IA);
-outer pixels (P) positioned in the display area (AA) and positioned in a first direction (lateral or x-axis) from an edge of the substrate (SUB);
-a dummy line (SP) positioned in the non-display area (IA) and extending in a second direction (vertical or y-axis) different from the first direction between the edge of the substrate (SUB) and the outer pixels (P),
wherein each of the outer pixels includes transistors (T) including at least one oxide semiconductor transistor (e.g., oxide-based semiconductor material),
the oxide semiconductor transistor is a transistor (T) positioned closest to the edge of the substrate (SUB) among the transistors (T), and
-a scan line (SL) connected to the oxide semiconductor transistor (T) and the dummy line (SP).
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Lee does not explicitly teach the scan line and the dummy line posiitoned in a same electrode layer.
Ha teaches, Fig. 5, plurality of lines (SL) positioned in a same electrode layer.
As taught by Ha, one of ordinary skill in the art would utilize & modify the above teaching to obtain the scan line and the dummy line posiitoned in a same electrode layer as claimed, because it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Ha in combination Lee due to above reason.
Re claim 14, Lee teaches, Figs. 1-2, dummy holes (TR, indicated) positioned in the non-display area (IA) and positioned between the edge of the substrate (SUB) and the outer pixels (P) (in AA).
Re claim 15, Lee teaches, Fig. 2, wherein the dummy line (SP) extends so as not to vertically overlap the dummy holes (TR, indicated).
Re claim 16, Lee teaches, Fig. 2, the dummy line (SP) is positioned between (e.g., top view) a first insulating layer (BN) and a second insulating layer (PLN), and
the dummy holes (TR, indicated) pass through the first insulating layer (BN) and the second insulating layer (PLN).
Re claim 17, Lee teaches, Fig. 2, a third insulating layer (PAS1) positioned on the second insulating layer (BN), wherein the dummy holes (TR, indicated) include a portion of the third insulating layer (PAS1) therein.
Re claim 18, Lee teaches, Fig. 2, wherein the dummy holes (indicated) do not include an electrode material therein.
Re claim 19, Lee teaches, under BRI, Fig. 2, wherein one end of the dummy line (SP) is connected (through between layers) to a first power line (CPL or PL) in an area adjacent to a first corner of the substrate (SUB), and an other end of the dummy line (SP) is connected (through between layers) to the first power line (CPL or PL) in an area adjacent to a second corner of the substrate (SUB).
7. Claims 10, 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Lee as modified by Ha as applied to claims 1 & 7-9 above, and further in view of Hong et al. (US 2022/0384490).
The teachings of Lee/Ha have been discussed above.
Re claim 10, Lee/Ha does not explicitly teach wherein the oxide semiconductor transistor is further connected to a sub-scan line that overlaps the scan line.
Hong teaches, [0017], the oxide semiconductor transistor (thin film transistor) is further connected to a sub-scan line that overlaps the scan line (e.g., first & third scan lines overlap each other).
As taught by Hong, one of ordinary skill in the art would utilize & modify the above teaching to obtain the oxide semiconductor transistor is further connected to a sub-scan line that overlaps the scan line as claimed, because it aids in achieving a display device that may suppress or avoid an inspection error caused by aperiodicity of a contact hole. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Hong in combination Lee/Ha due to above reason.
Re claim 12, Lee/Ha does not explicitly teach wherein a vertical distance between the scan line connected to the oxide semiconductor transistor and the substrate is the largest among vertical distances between scan lines connected to the outer pixels and the substrate.
Hong does teach overlapping scan lines [0017].
As taught by Hong, one of ordinary skill in the art would utilize & modify the above teaching to obtain a vertical distance between the scan line connected to the oxide semiconductor transistor and the substrate is the largest among vertical distances between scan lines connected to the outer pixels and the substrate as claimed, because it aids in achieving a display device that may suppress or avoid an inspection error caused by aperiodicity of a contact hole. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Hong in combination Lee/Ha due to above reason.
Re claim 13, Lee/Ha does not explicitly teach wherein the oxide semiconductor transistor is further connected to a sub-scan line, and the sub-scan line is positioned to vertically overlap between the substrate and the scan line.
Hong teaches, [0017], the oxide semiconductor transistor (thin film transistor) is further connected to a sub-scan line, and the sub-scan line is positioned to vertically overlap between the substrate and the scan line (e.g., first & third scan lines overlap each other).
As taught by Hong, one of ordinary skill in the art would utilize & modify the above teaching to obtain the oxide semiconductor transistor is further connected to a sub-scan line, and the sub-scan line is positioned to vertically overlap between the substrate and the scan line as claimed, because it aids in achieving a display device that may suppress or avoid an inspection error caused by aperiodicity of a contact hole. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Hong in combination Lee/Ha due to above reason.
Allowable Subject Matter
8. Claims 6 & 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Conclusion
9. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Miyamoto et al. (US 2016/0071884, Figs. 1-6) discloses display device provided with pixel and dummy pixel.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 7/16/26
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