DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
2. Applicant’s election without traverse of Group I (claims 1-15 and 21-25) in the reply filed on June 12, 2026 is acknowledged.
Information Disclosure Statement
3. The information disclosure statements (IDS) submitted on March 18, 2025 and September 11, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner except as otherwise indicated.
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
5. Claims 1-2, 21, and 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al (US 2022/0293681 A1, hereafter Chen) in view of Hsu et al (US 2020/0075856 A1, hereafter Hsu).
Regarding claim 1¸ Chen discloses a device structure (Fig. 4A 400A; [0046]) comprising,
a first metal interconnect structure (Fig. 3D 118; [0026]) formed in a first dielectric material layer (Fig. 3D 116; [0026]);
an etch-stop dielectric layer (Fig. 3D 114; [0026]) overlying the first dielectric material layer (116) and having an opening (Fig. 3D gap between 114) along a first horizontal direction (Fig. 3D X)
a resistive memory cell (Figs. 3D+4 102a) comprising a stack of a bottom electrode (202+BV; [0037],[0052]), a memory material layer (Fig. 3D 204; [0033]), and a top electrode (Fig. 3D 206; [0033]), wherein the bottom electrode (202+BV) comprises a plate portion (Fig. 3D part of 202+BV above 114) overlying the etch-stop dielectric layer (114) and a via portion (Fig. 3D part of 202+BV between 114) located within the opening (gap between 114) in the etch-stop dielectric layer (114), the memory material layer (204) overlies the bottom electrode (202+BV), and the top electrode (206) overlies the memory material layer (204); and
a hard mask plate (Fig. 3D 208; [0033]) overlying the top electrode (206).
Chen fails to explicitly disclose having an opening having a first width along a first horizontal direction, and a periphery of a top surface of the hard mask plate has a second width along the first horizontal direction that is greater than the first width.
Hsu discloses having an opening (Fig. 4 area occupied by 116a between horizontal portion of 128) having a first width (Fig. 2B W1”; [0051]) along a first horizontal direction, and a periphery of a top surface of the hard mask plate (Fig. 2B 122; [0022]) has a second width (Fig. 2B W4; 0031]) along the first horizontal direction that is greater ([0031]) than the first width (W1”). Hsu is analogous to Chen in the field of memory structures.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use the width relationship of Hsu in the device of Chen to improve device performance by providing higher device density for device scaling-down.
Regarding claim 2, Chen and Hsu disclose the device structure of claim 1, further comprising:
a memory-level dielectric layer (Fig. 3D 110; [0020]) laterally surrounding (Fig. 3D) the bottom electrode (202+BV), the memory material layer (204), and the top electrode (206); and
a top electrode contact structure (Fig. 3D 120) vertically extending through (Fig. 3D) an upper portion of the memory-level dielectric layer (top half of 110) and contacting (120 is in contact with 206) a top surface of the top electrode (top of 206).
Regarding claim 21¸ Chen discloses a device structure comprising:
an etch-stop dielectric layer (Fig. 3D 114; [0026]) having an opening (Fig. 3D gap between 114) along a first horizontal direction (Fig. 3D X)
a resistive memory cell (Figs. 3D+4 102a) comprising a bottom electrode (202+BV; [0037], [0052]), a memory material layer (Fig. 3D 204; [0033]), and a top electrode (Fig. 3D 206; [0033]), wherein the bottom electrode (202+BV) comprises a via portion (Fig. 3D lower portion between 114) located within the opening (gap between 114);
a hard mask plate (Fig. 3D 208; [0033]) overlying the top electrode (206);
a memory-level dielectric layer (Fig. 3D 110) laterally surrounding (Fig. 3D) the resistive memory cell (102a); and
a top electrode contact structure (Fig. 3D 120) vertically extending through (Fig. 3D) an upper portion of the memory-level dielectric layer (top half of 110) and contacting (120 is in contact with 206) a top surface of the top electrode (top of 206),
Chen fails to explicitly disclose the opening having a first width, and a periphery of a top surface of the hard mask plate has a second width along the first horizontal direction that is greater than the first width.
Hsu discloses having an opening (Fig. 4 area occupied by 116a between horizontal portion of 128) having a first width (Fig. 2B W1”; [0051]) along a first horizontal direction, and a periphery of a top surface of the hard mask plate (Fig. 2B 122; [0022]) has a second width (Fig. 2B W4; 0031]) along the first horizontal direction that is greater ([0031]) than the first width (W1”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use the width relationship of Hsu in the device of Chen to improve device performance by providing higher device density for device scaling-down.
Regarding claim 23, Chen and Hsu disclose the device structure of claim 21, further comprising a dielectric spacer (Chen Figs. 3D 210) in contact with a tapered surface (Chen Fig. 3D outer surface of 206+208) laterally surrounding (Fig. 3D) the top electrode (206).
Chen and Hsu fail to disclose the dielectric spacer in contact with an entirety of a tapered surface extending from a periphery of the top surface of the hard mask plate to at least to a top surface of the bottom electrode and laterally surrounding the memory material layer.
However, Chen discloses a dielectric spacer (Fig. 2 210) in contact with an entirety of a tapered surface (Chen Fig. 2 outer surface of 202+204+206+208) extending from a periphery of the top surface of the hard mask plate (outer surface of 208) to at least to a top surface of the bottom electrode (Fig. 2 top of 202+214+BV) and laterally surrounding (Fig. 2) the memory material layer (204).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the edges of the device of Chen and Hsu to be tapered down to the top of the bottom electrode and surround the memory material layer, as shown by Chen (Fig. 2), to improve device performance by reducing electrical shorts and enabling higher device density.
Regarding claim 24, Chen and Hsu disclose the device structure of claim 21, wherein the top electrode contact structure (120) comprises a metal line structure (Chen Figs. 5+6B CL; [0055]) that laterally extends (Figs. 5+6B) along a column of resistive memory cells (Fig. 5 102, CL extends across columns of 102) and contacts (Fig. 6B) a respective top electrode (102) of each of the resistive memory cells (102).
6. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Chen and Hsu as applied to claim 2 above, and further in view of Chuang et al (US 2019/0371996 A1, hereafter Chuang) and Chen et al (US 2020/0127047, hereafter Chen 047).
Regarding claim 3¸ Chen and Hsu disclose the device structure of claim 2.
Chen and Hsu fail to explicitly disclose a bottom surface of the top electrode contact structure has a third width along the first horizontal direction that is less than the second width and greater than the first width.
Chuang discloses a bottom surface of the top electrode contact structure (Fig. 1A 116; [0016]) has a third width (Fig. 1A d2; [0016]) along the first horizontal direction that is less than the second width (Fig. 1A d1; [0016]). Chuang is analogous to Chen and Hsu in the field of memory structures.
Chuang fails to disclose a bottom surface of the top electrode contact structure has a third width along the first horizontal direction that is greater than the first width.
Chen 047 discloses a bottom surface of the top electrode contact structure (Fig. 1 bottom of 138; [0030]) has a third width (distance horizontally across bottom of 138) along the first horizontal direction that is greater than the first width (Fig. 1 distance between 110 across bottom of 119; [0028]). Chen 047 is analogous to Chen, Hsu, and Chuang in the field of memory structures.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use the dimensions disclosed by Chuang and Chen 047 in the device of Chen and Hsu to design the claimed device for desired device functions and improve conductivity.
7. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Chen and Hsu as applied to claim 2 above, and further in view of Chang et al (US 2022/0059550 A1, hereafter Chang).
Regarding claim 4¸ Chen and Hsu disclose the device structure of claim 2.
Chen and Hsu fail to disclose a hard mask divot-fill material portion located within a divot in the top surface of the top electrode, contacting a divot-shaped segment of the top surface of the top electrode and underlying a bottom surface of the top electrode contact structure.
Chang discloses a hard mask divot-fill material portion (Fig. 3 center V-shape of 120; [0028]) located within a divot (Fig. 3 V-shape in center of 208) in the top surface of the top electrode (Fig. 3 top of 118; [0027]), contacting a divot-shaped segment of the top surface of the top electrode (top of V-shape in 118) and underlying a bottom surface of the top electrode contact structure (Fig. 3 bottom of 216, V-shaped segment of 120 is below 216).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention been obvious to adjust the shape of the memory cell of Chen and Hsu to be similar to the memory cell of Chang to include the hardmask and top electrode shapes and improve device performance by the conductive surface area.
8. Claims 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen and Hsu as applied to claim 1 above, and further in view of Chang.
Regarding claim 5¸ Chen and Hsu disclose the device structure of claim 1.
Chen and Hsu fail to disclose the opening in the etch-stop dielectric layer has a shape of a circle, an oval, or a rounded rectangle; and the first width is a diameter, a minor axis, or a distance between a pair of parallel segments.
Chang discloses the opening (Fig. 20B 1906, bottom surface of bottom electrode is same dimension as opening; [0091]) in the etch-stop dielectric layer (Fig. 19A 110) has a shape of a circle (Fig. 23B 1906) or a rounded rectangle (Fig. 2B 214 has rounded edges, Fig. 20B 1906); and the width (Fig. 20B 2016; [0101]) is a diameter, a minor axis, or a distance between a pair of parallel segments.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the shape of the opening of the device of Chen and Hsu to be one of the shapes disclosed by Chang to maximize device density to improve device performance.
9. Claims 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chen and Hsu as applied to claim 1 above, and further in view of Chang et al (US 2015/0090949 A1, hereafter Chang 949).
Regarding claim 6, Chen and Hsu disclose the device of claim 1, wherein:
the etch-stop dielectric layer (114) comprises an annular portion (curved part of 114) that laterally surrounds the opening (area between 114) and having a first thickness (vertical distance of top part of 114 that is curved), and a planar layer portion (horizontally flat part of 114 not overlapping 202) having a second thickness (vertical distance of flat part of 114).
Chen and Hsu fail to explicitly disclose the memory material layer is configured to provide at least two states having different electrical resistance, and the second thickness less than the first thickness.
Chang 949 discloses the memory material layer (Fig. 1B 116; [0018]) is configured to provide at least two states having different electrical resistance ([0013]-[0014]), and the second thickness (Fig. 1B vertical distance of recessed flat part of 112) less than the first thickness (Fig. 1B vertical distance of raised part of 112 with rounded end) and laterally spaced from the opening by the annular portion (Fig. 1B curved raised part of 112 in between opening (area between 112) and recessed flat part of 112).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention been obvious to configure the memory material layer of Chen and Hsu to provide at least two different states to perform the intended device function and to design the etch-stop dielectric layer to have a similar shape to Chang 949 to protect the device from future processing steps, as discussed by Chang 949 ([0018]).
10. Claims 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, Hsu, and Chang 949 as applied to claim 6 above, and further in view of Chuang.
Regarding claim 7¸ Chen, Hsu, and Chang 949 disclose the device of claim 6, wherein a tapered surface (Fig. 3D outer surface of 202+204+206+208) extends from the periphery of the top surface of the hard mask plate (top of 208) at least to a top surface of the bottom electrode (top of 202).
Chen, Hsu, Chuang, and Chang 949 fail to explicitly disclose a tapered surface extends straight at a taper angle with respect to a vertical direction, the taper angle being in a range from 5 degrees to 20 degrees.
However, Chen discloses a tapered surface (Fig. 2 outer surface of 202+204+206+208) extends straight (Fig. 2 straight surface) from the periphery of the top surface of the hard mask plate (top of 208) at least to a top surface of the bottom electrode (top of 202) at a taper angle with respect to a vertical direction (angled with respect to plane normal to top of 114).
Chuang discloses the taper angle being in a range from 5 degrees to 20 degrees ([0035], Chuang discloses an angle other than 90 degrees).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the edges of the device of Chen, Hsu, Chuang, and Chang 949 to be straight and tapered, as shown by Chen (Fig. 2), and to make the taper angle to be within the claimed range, as disclosed by Chuang ([0035]), to improve device performance by reducing electrical shorts and enabling higher device density.
Regarding claim 8¸ Chen, Hsu, Chang 949, and Chuang disclose the device of claim 7, further comprising a dielectric spacer (Chen Figs. 2+3D 210) in contact with an entirety of the tapered surface (Chen Fig. 2 outer surface of 202+204+206+208) and laterally surrounding the top electrode (206) and the memory material layer (204).
Regarding claim 9¸ Chen, Hsu, Chang 949, and Chuang disclose the device structure of claim 8, wherein an annular bottom surface of the dielectric spacer (bottom of 210, which is annular) is in contact with an annular surface segment of the etch-stop dielectric layer (114) (Chen Fig. 2 210 in contact with 114, which would be connected to the annular segment of 114).
Regarding claim 10, Chen, Hsu, Chang 949, and Chuang disclose the device structure of claim 8, wherein an annular bottom surface of the dielectric spacer (bottom of 210, which is annular) is in contact with an annular surface segment of a top surface of the bottom electrode (top of 202 is annular in Chen Fig. 3D) (device as modified in claim 8 has dielectric spacer 210 extending top surface of bottom electrode 202 in Chen Fig. 3D, as shown in Chen Fig. 2).
11. Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Chang 949 and Hsu.
Regarding claim 11, Chen discloses a device structure comprising,
an etch-stop dielectric layer (Fig. 3D 114; [0026]) comprises an annular portion (Fig. 3D 114 curved part of 114) having a first thickness (vertical distance of top part of 114 that is curved), including an opening (Fig. 3D gap between 114) therethrough, and a planar layer portion (Fig. 3D 114 part not overlapping 202) having a second thickness (vertical distance of flat part of 114);
a resistive memory cell (Figs. 3D+4 102a) comprising a stack of a bottom electrode (202+BV; [0037],[0052]), a memory material layer (Fig. 3D 204; [0033]), and a top electrode (Fig. 3D 206; [0033]), the bottom electrode (202+BV) comprises a via portion (Fig. 3D part of 202+BV between 114) that vertically extends downward (Fig. 3D) into the opening (gap between 114) in the etch-stop dielectric layer (114); and
a hard mask plate (Fig. 3D 208; [0033]) overlying the top electrode (206),
wherein a tapered surface (Fig. 3D outer surface of 202+204+206+208) extends from the periphery of the top surface of the hard mask plate (top of 208) at least to a top surface of the bottom electrode (top of 202).
Chen fails to explicitly disclose the planar layer portion having a second thickness less than the first thickness and laterally spaced from the opening by the annular portion, wherein the opening has a first width along a first horizontal direction;
wherein a periphery of a top surface of the hard mask plate has a second width along the first horizontal direction that is greater than the first width,
wherein a tapered surface extends straight at a taper angle with respect to a vertical direction.
However, Chen discloses a tapered surface (Fig. 2 outer surface of 202+204+206+208) extends straight (Fig. 2 straight surface) from the periphery of the top surface of the hard mask plate (top of 208) at least to a top surface of the bottom electrode (top of 202) at a taper angle with respect to a vertical direction (angled with respect to plane normal to top of 114).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the adjust the edges of the device of Chen, Hsu, and Chang 949 to be straight and tapered to improve device performance by reducing electrical shorts and enabling higher device density.
Chang 949 discloses the second thickness (Fig. 1B vertical distance of recessed flat part of 112) less than the first thickness (Fig. 1B vertical distance of raised part of 112 with rounded end) and laterally spaced from the opening by the annular portion (Fig. 1B curved raised part of 112 in between opening (area between 112) and recessed flat part of 112).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention been obvious to design the etch-stop dielectric layer to have a similar shape to Chang 949 to protect the device from future processing steps, as discussed by Chang 949 ([0018]).
Chang 949 fails to disclose a periphery of a top surface of the hard mask plate has a second width along the first horizontal direction that is greater than the first width,
Hsu discloses a periphery of a top surface of the hard mask plate (Fig. 2B 122; [0022]) has a second width (Fig. 2B W4; 0031]) along the first horizontal direction that is greater ([0031]) than the first width (W1”).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use the width relationship of Hsu in the device of Chen and Chang 949 to improve device performance by providing higher device density for device scaling-down.
Regarding claim 12¸ Chen, Chang 949, and Hsu disclose the device structure of claim 11, further comprising a dielectric capping layer (Chen Fig. 3D 216; [0036]) laterally surrounding the resistive memory cell (102a), contacting a cylindrical sidewall of the etch-stop dielectric layer (114) (equivalent to 112 in Chang 949, device as modified above by Chang 949 has edges where capping layer 216 would be in contact with etch-stop dielectric layer) connecting a periphery of a top surface of the annular portion of the etch-stop dielectric layer (Chang 949 Fig. 1B raised part of 112 with rounded end) and a periphery of a top surface of the planar layer portion of the etch-stop dielectric layer (Chen Fig. 1B recessed flat part of 112), contacting (Fig. 3D) a sidewall of the bottom electrode (side edge of 202+BV), and contacting (Fig. 3D) the top surface of the hard mask plate (top of 208).
Regarding claim 13¸ Chen, Chang 949, and Hsu disclose the device structure of claim 12, further comprising:
a memory-level dielectric layer (Chen Fig. 3D 110; [0020]) overlying (Fig. 3D) a horizontally-extending portion of the dielectric capping layer (horizontal part of 216) and laterally surrounding (Fig. 3D) a portion of the dielectric capping layer (216) that protrudes above the horizontally-extending portion of the dielectric capping layer (portion of 216 surrounding resistive memory cell 102a); and
a top electrode contact structure (Fig. 3D 120) vertically extending through (Fig. 3D) an upper portion of the memory-level dielectric layer (top half of 110), the dielectric capping layer (216) and contacting (120 is in contact with 206) a top surface of the top electrode (top of 206).
12. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, Chang 949, and Hsu as applied to claim 13 above, and further in view of Chuang and Chen 047.
Regarding claim 14, Chen, Chang 949, and Hsu disclose the device structure of claim 13.
Chen, Chang 949, and Hsu fail to explicitly disclose a bottom surface of the top electrode contact structure has a third width along the first horizontal direction that is less than the second width and greater than the first width.
Chuang discloses a bottom surface of the top electrode contact structure (Fig. 1A 116; [0016]) has a third width (Fig. 1A d2; [0016]) along the first horizontal direction that is less than the second width (Fig. 1A d1; [0016]).
Chuang fails to disclose a bottom surface of the top electrode contact structure has a third width along the first horizontal direction that is greater than the first width.
Chen 047 discloses a bottom surface of the top electrode contact structure (Fig. 1 bottom of 138; [0030]) has a third width (distance horizontally across bottom of 138) along the first horizontal direction that is greater than the first width (Fig. 1 distance between 110 across bottom of 119; [0028]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use the dimensions disclosed by Chuang and Chen 047 in the device of Chen, Chang 949, and Hsu to design the claimed device for desired device functions and improve conductivity.
13. Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, Chang 949, and Hsu as applied to claim 13 above, and further in view of Chuang.
Regarding claim 15, Chen, Chang 949, and Hsu disclose the device structure of claim 11, wherein:
a top surface of the bottom electrode (top of 202+BV) comprises an annular top surface segment (portion of 202 curving downwards) and a central recessed horizontal surface segment (lower portion of 202) that underlies a downward-protruding portion of the memory material layer lower portion of 204), wherein a lateral extent of the central recessed horizontal surface segment (horizontal distance of 202 in contact with 204) along the first horizontal direction is less than the first width (W1”) (W1”, which is distance between 114, is greater than length of 204 in contact with 202).
Chen, Chang 949, and Hsu fail to disclose the taper angle is in a range from 5 degrees to 20 degrees.
Chuang discloses the taper angle being in a range from 5 degrees to 20 degrees ([0035], Chuang discloses an angle other than 90 degrees).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the adjust the edges of the device of Chen, Chang 949, and Hsu to make the taper angle to be within the claimed range, as disclosed by Chuang ([0035]), to improve device performance by reducing electrical shorts and enabling higher device density.
14. Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Chen and Hsu as applied to claim 21 above, and further in view of Chuang, Chen 047, and Chang.
Regarding claim 22¸ Chen and Hsu disclose the device structure of claim 21.
Chen and Hsu fail to disclose a bottom surface of the top electrode contact structure has a third width along the first horizontal direction that is less than the second width and greater than the first width; and
the device structure further comprises a hard mask divot-fill material portion located within a divot in the top surface of the top electrode, contacting a divot-shaped segment of the top surface of the top electrode, and underlying the bottom surface of the top electrode contact structure.
Chuang discloses a bottom surface of the top electrode contact structure (Fig. 1A 116; [0016]) has a third width (Fig. 1A d2; [0016]) along the first horizontal direction that is less than the second width (Fig. 1A d1; [0016]). Chuang is analogous to Chen and Hsu in the field of memory structures.
Chuang fails to disclose a bottom surface of the top electrode contact structure has a third width along the first horizontal direction that is greater than the first width, and the device structure further comprises a hard mask divot-fill material portion located within a divot in the top surface of the top electrode, contacting a divot-shaped segment of the top surface of the top electrode, and underlying the bottom surface of the top electrode contact structure.
Chen 047 discloses a bottom surface of the top electrode contact structure (Fig. 1 bottom of 138; [0030]) has a third width (distance horizontally across bottom of 138) along the first horizontal direction that is greater than the first width (Fig. 1 distance between 110 across bottom of 119; [0028]). Chen 047 is analogous to Chen, Hsu, and Chuang in the field of memory structures.
Chen 047 fails to disclose the device structure further comprises a hard mask divot-fill material portion located within a divot in the top surface of the top electrode, contacting a divot-shaped segment of the top surface of the top electrode, and underlying the bottom surface of the top electrode contact structure.
Chang discloses a hard mask divot-fill material portion (Fig. 3 center V-shape of 120; [0028]) located within a divot (Fig. 3 V-shape in center of 208) in the top surface of the top electrode (Fig. 3 top of 118; [0027]), contacting a divot-shaped segment of the top surface of the top electrode (top of V-shape in 118) and underlying a bottom surface of the top electrode contact structure (Fig. 3 bottom of 216, V-shaped segment of 120 is below 216).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use the dimensions disclosed by Chuang and Chen 047 in the device of Chen and Hsu to design the claimed device for desired device functions and improve conductivity. Additionally, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention been obvious to adjust the shape of the memory cell of Chen and Hsu to be similar to the memory cell of Chang to include the hardmask and top electrode shapes and improve device performance by the conductive surface area.
15. Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Chen and Hsu as applied to claim 21 above, and further in view of Chen 047.
Regarding claim 25, Chen and Hsu disclose the device structure of claim 21, further comprising a metallic via structure (Fig. 3D 118) underlying (Fig. 3D) the resistive memory cell (102a), wherein the memory material layer (204) is located within an area (Fig. 3D) of a top surface of the metallic via structure (top of 118).
Chen and Hsu fail to explicitly disclose the memory material layer (204) is located entirely within an area of a top surface of the metallic via structure in a plan view.
However, Chen discloses the memory material layer (Fig. 2 204) is located entirely within an area of a top surface of the metallic via structure (Fig. 2 top of 118) in a cross-sectional, and extrapolation of this view into a plan view would show the same, as evidenced by Chen 047 (Figs 2+3A).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to adjust the dimensions of the metallic via structure to completely overlap the memory material layer, as evidenced by Chen and Chen 047, to reduce resistivity and device performance.
Conclusion
16. The following art made of record and not relied upon is pertinent to applicant’s disclosure.
Lee et al (US 2021/0242399 A1) discloses a memory cell structure with top and bottom interconnects
Hsiao et al (US 2021/0217812 A1) discloses a memory device with tapered sides and a bottom via
Chaung et al (US 2020/0098982 A1) discloses a memory device with tapered sides and a bottom via
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/MICHAEL B SUN/Examiner, Art Unit 2892
/KHIEM D NGUYEN/Primary Examiner, Art Unit 2892
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