DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
3. Claim(s) 1, is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al., US-20210375877-A1, in view of Shiratake, US-20070096204-A1.
Claim 1. Kim et al., disclose a semiconductor device (such as the one in figs. 3-4, [0049-51]), comprising:
-a substrate (item 100) having an active region (item ACT) and a peripheral region (peripheral region PERI) surrounding the active region;
-a word line structure (word line WL, cited in [0049] disposed in the active region of the substrate;
-a first gate structure (item 102, [0117]) disposed in the peripheral region of the substrate.
Kim appears to not specifically specify “wherein a bottom surface of the first gate structure is curved toward the substrate, and the bottom surface of the first gate structure is below a top surface of the substrate; and a second gate structure disposed in the peripheral region of the substrate and the second gate structure located between the word line structure and the first gate structure, wherein a bottom surface of the second gate structure is coplanar with the top surface of the substrate”.
However, Shiratake is directed towards a method for manufacturing a semiconductor device, wherein a bottom surface of the first gate structure (item 208 in a memory cell region M, fig. 44), is curved toward the substrate, and the bottom surface of the first gate structure is below a top surface of the substrate (as seen in the structure of fig. 44);
-and a second gate structure (item 207 in the peripheral circuit region PE, fig. 44), disposed in the peripheral region of the substrate and the second gate structure located between the word line structure and the first gate structure, wherein a bottom surface of the second gate structure is coplanar with the top surface of the substrate (as seen in the structure of fig. 44).
Kim and Shiratake are in the same or similar fields of endeavor. It would have been obvious to one having ordinary skill in the art at a time prior to the effective filing date of the present application to combine Kim with Shiratake to optimize channel control, reduce leakage, improve stress distribution, enhance breakdown and current handling, and improve manufacturability.
Allowable Subject Matter
4. Claims 2-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
(A) Claim 2, contains allowable subject matter because none of references of record teach or suggest, either singularly or in combination, at least the limitation of wherein the first gate structure comprises: a first dielectric layer disposed below the top surface of the substrate; a first lower conductive layer disposed on the first dielectric layer; a first upper conductive layer disposed on the first lower conductive layer; and a first cap layer disposed on the first upper conductive layer.
(B) Claims 3-7, are also allowable subject matter, as depend on claim 2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILNER JEAN BAPTISTE whose telephone number is (571)270-7394. The examiner can normally be reached M-T 8:00-6:00.
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/W.J/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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