CTNF 18/625,485 CTNF 98866 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on 04/03/2024, 11/12/2024, 08/05/2025, 11/18/2025 are being considered by the examiner. Drawings 06-36 AIA The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “two-terminal write selector is formed after forming a write word line” in claim 19 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Objections 07-29-01 AIA Claim 19 is objected to because of the following informalities: The examiner is unsure how the “the two-terminal write selector is formed after forming a write word line”. The examiner does not see where the specification mentions this step. The examiner only sees Figs. 6G, 7A and 7B where the two-terminal write selector (110) is formed before the write word line (130). See paragraph [0102] . Appropriate correction is required. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 1-6 and 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshikawa (US 20230082665 A1) in view of Chiang et al. (US 20220246189 A1) . Regarding claim 1 , Yoshikawa discloses a memory device comprising: a spin-orbit torque (“SOT”) conductor (SOTL); ([0045], Fig. 4) a magnetic tunneling junction (“MTJ”) structure (MTJ) arranged above the SOT conductor (SOTL), wherein the MTJ structure has a free layer (27a), a pinned layer (27e), and a tunnel barrier layer (27b) sandwiched between the free layer (27a) and the pinned layer (27e), and wherein the free layer (27a) is in conductive contact with the SOT conductor (SOTL); ([0026], [0088], Fig. 5) a two-terminal read selector (SEL2) conductively connected to the pinned layer (27e) in the MTJ structure (MTJ), wherein the two-terminal read selector (SEL2) is arranged above the MTJ structure (MTJ); (Fig. 4) a two-terminal write selector (SEL1) conductively connected to a first terminal of the SOT conductor (SOTL), (Fig. 4) Yoshikawa does not disclose: wherein the two-terminal write selector is arranged above the MTJ structure; and a bit line conductively connected to a second terminal of the SOT conductor, wherein the bit line is arranged below the SOT conductor. However, Chiang discloses: wherein the two-terminal write selector (104) is arranged above the MTJ structure (100); ([0041], Fig. 5E) and a bit line (BL) conductively connected to a second terminal of the SOT conductor (102), wherein the bit line (BL) is arranged below the SOT conductor (102). (Fig. 5E) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yoshikawa and Chiang for the two-terminal write selector is arranged above the MTJ structure; and a bit line conductively connected to a second terminal of the SOT conductor, wherein the bit line is arranged below the SOT conductor so that “the storage unit SU can be more flexibly routed” (Chiang, [0043]) Regarding claim 2 , Yoshikawa discloses the memory device of claim 1, further comprising: a read word line (RBL) conductively connected to the two-terminal read selector (SEL2), wherein the read word line (RBL) is arranged above the two-terminal read selector (SEL2). (Fig. 4) Regarding claim 3 , Chiang discloses the memory device of claim 1, further comprising: a write word line (WWL) conductively connected to the two-terminal write selector (104), wherein the write word line (WWL) is arranged above the two-terminal write selector (104). (Fig. 5E) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yoshikawa and Chiang for similar reasons mentioned beforehand. Regarding claim 4 , Yoshikawa discloses the memory device of claim 1, further comprising: a read word line (RBL) conductively connected to the two-terminal read selector (SEL2); (Fig. 4) Yoshikawa does not disclose: and a write word line conductively connected to the two-terminal write selector. However, Chiang discloses: a write word line (WWL) conductively connected to the two-terminal write selector (104). It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yoshikawa and Chiang to have a write word line conductively connected to the two- terminal write selector so that “write disturbance of a memory array including a plurality of the memory devices 10 can be reduced.” (Chiang, [0016]) Regarding alim 5 , Chiang discloses the memory device of claim 4, wherein the read word line (RWL) and the write word line (WWL) are in a same conductive layer above the two-terminal write selector (104). ([0042], Fig. 5E) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yoshikawa and Chiang the read word line and the write word line are in a same conductive layer above the two-terminal write selector so that “the storage unit SU can be more flexibly routed” (Chiang, [0043]) Regarding claim 6 , Chiang discloses the memory device of claim 4, wherein each of the SOT conductor (102) and the bit line (BL) extends in a first direction (horizontal x), and wherein the write word line (WWL) and the read word line (RWL) extend in a second direction (horizontal y) that is perpendicular to the first direction. (Fig. 5E) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yoshikawa and Chiang to arrive at the claimed invention so that “the storage unit SU can be more flexibly routed” (Chiang, [0043]) Regarding claim 12 , Yoshikawa discloses a memory device comprising: a spin-orbit torque (“SOT”) conductor (SOTL); ([0045], Fig. 4) a magnetic tunneling junction (“MTJ”) structure (MTJ) arranged above the SOT conductor (SOTL), wherein the MTJ structure has a free layer (27a), a pinned layer (27e), and a tunnel barrier layer (27b) sandwiched between the free layer (27a) and the pinned layer (27e), and wherein the free layer (27a) is in conductive contact with the SOT conductor (SOTL); ([0026], [0088], Fig. 5) a two-terminal read selector (SEL2) conductively connected to the pinned layer (27e) in the MTJ structure (MTJ), wherein the two-terminal read selector (SEL2) is arranged above the MTJ structure (MTJ); (Fig. 4) Yoshikawa does not disclose: a two-terminal write selector conductively connected to a first terminal of the SOT conductor, wherein the two-terminal write selector is arranged below the MTJ structure; a write word line conductively connected to the two-terminal write selector, wherein the write word line is arranged below the two-terminal write selector; a bit line conductively connected to a second terminal of the SOT conductor, wherein the bit line is arranged below the write word line. However, Chiang discloses: a two-terminal write selector (104) conductively connected to a first terminal (right side) of the SOT conductor (102), wherein the two-terminal write selector (104) is arranged below the MTJ structure (100); ([0038], Fig. 5A) a write word line (WWL) conductively connected to the two-terminal write selector (104), wherein the write word line (WWL) is arranged below the two-terminal write selector (104); ([0038], Fig. 5A) a bit line (BL) conductively connected to a second terminal (left side) of the SOT conductor (102), wherein the bit line (BL) is arranged below the write word line (WWL). (Fig. 5A) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yoshikawa and Chiang to have a two-terminal write selector conductively connected to a first terminal of the SOT conductor, wherein the two-terminal write selector is arranged below the MTJ structure; a write word line conductively connected to the two-terminal write selector, wherein the write word line is arranged below the two-terminal write selector; a bit line conductively connected to a second terminal of the SOT conductor, wherein the bit line is arranged below the write word line so that “the storage unit SU can be more flexibly routed” (Chiang, [0043]) Regarding claim 13 , Yoshikawa discloses the memory device of claim 12, further comprising: a read word line (RBL) conductively connected to the two-terminal read selector (SEL2), wherein the read word line (RBL) is arranged above the two-terminal read selector (SEL2). (Fig. 4) Regarding claim 14 , Yoshikawa discloses the memory device of claim 13. Yoshikawa does not disclose wherein the SOT conductor extends in a first direction , and wherein the write word line and the read word line extend in a second direction that is perpendicular to the first direction. However, Chiang discloses: the SOT conductor (102) extends in a first direction (horizontal x direction) , and wherein the write word line (WWL) and the read word line (RWL) extend in a second direction (horizontal y) that is perpendicular to the first direction (horizontal x). (Fig. 5A) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yoshikawa and Chiang for the SOT conductor extends in a first direction , and wherein the write word line and the read word line extend in a second direction that is perpendicular to the first direction so that “the storage unit SU can be more flexibly routed” (Chiang, [0043]) Regarding alim 15 , Chiang discloses the memory device of claim 14, wherein the bit line (BL) extends in the first direction (horizontal x) and is vertically stacked with the SOT conductor (102). (Fig. 5A) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yoshikawa and Chiang for similar reasons mentioned beforehand. Regarding claim 16 , Yoshikawa discloses a method comprising: forming a spin-orbit torque (“SOT”) conductor (SOTL) extending in a first direction (horizontal x); forming a magnetic tunneling junction (“MTJ”) structure (MTJ) over the SOT conductor (SOTL), wherein forming the MTJ structure (MTJ) comprises depositing a free layer (27a) over the SOT conductor (SOTL), depositing a tunnel barrier layer (27b) over the free layer (27a), and depositing a pinned layer (27e) over the tunnel barrier layer (27b); (Fig. 4) and forming a two-terminal read selector (SEL2) above the MTJ structure (MTJ), wherein the two-terminal read selector (SEL2) is conductively connected to the pinned layer (27e) in the MTJ structure (MTJ); (Fig.4) and Yoshikawa does not disclose: forming a two-terminal write selector which is conductively connected to a first terminal of the SOT conductor. However, Chiang discloses: forming a two-terminal write selector (104) which is conductively connected to a first terminal (right side) of the SOT conductor (102). (Fig. 5D) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yoshikawa and Chiang for forming a two-terminal write selector which is conductively connected to a first terminal of the SOT conductor so that “write disturbance of a memory array including a plurality of the memory devices 10 can be reduced.” (Chiang, [0016]) Regarding claim 17 , Yoshikawa discloses the method of claim 16, further comprising: forming a read word line (RBL) above the two-terminal read selector (SEL2), (Fig. 4) Yoshikawa does not disclose: extending in a second direction wherein the second direction is perpendicular to the first direction. However, Chiang discloses: read word line (RWL) extending in a second direction (horizontal y) wherein the second direction is perpendicular to the first direction (horizontal x). (Fig. 5D) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yoshikawa and Chiang for the read word line extending in a second direction wherein the second direction is perpendicular to the first direction so that “the storage unit SU can be more flexibly routed” (Chiang, [0043]) Regarding claim 18 , Chiang discloses the method of claim 16, further comprising: forming the two-terminal write selector (104) above the MTJ structure (104); (Fig. 5D) and forming a write word line (WWL) extending in a second direction (horizontal y) above the two-terminal write selector (104). (Fig. 5D) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yoshikawa and Chiang for similar reasons mentioned beforehand. Regarding alim 19 , Chiang discloses the method of claim 16, wherein forming the SOT conductor comprise forming the SOT conductor (102) above the two-terminal write selector (104), (Fig. 5D) Chiang does not explicitly disclose: and wherein the two-terminal write selector is formed after forming a write word line extending in a second direction. However, Chiang does disclose: “In these embodiments, a conductive layer for forming the write word line WWL and material layers for forming the line-shaped selector 104 may simultaneously patterned, and a lithography process and one or more etching processes may be performed during this patterning step. Alternately, separate patterning processes may be performed for forming the write word line WWL and the line-shaped selector 104 ” in [0041]) which leads the examiner to believe that the order of steps to forming these layers are entirely dependent on how one skilled in the art chooses to do so. Therefore, it would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yoshikawa and Chiang for the two-terminal write selector is formed after forming a write word line extending in a second direction so that “ the storage unit SU can be more flexibly routed” (Chiang, [0043]) Regarding claim 20 , Chiang discloses the method of claim 16, further comprising: forming a bit line (BL) extending in the first direction (horizontal x); and forming the SOT conductor (102) above the bit line (BL) and having a second terminal (left side) conductively connected to the bit line (BL), wherein the SOT conductor (102) is vertically stacked with the bit line (BL). (Fig. It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yoshikawa and Chiang for similar reasons mentioned beforehand . 07-22-aia AIA Claim s 7-11 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshikawa (US 20230082665 A1) in view of Chiang et al. (US 20220246189 A1) as applied to claim 1 above, and further in view of Laurent (US 20180233177 A1) . Regarding claim 7 , Yoshikawa in view of Chiang disclose the memory device of claim 1. Yoshikawa in view of Chiang do not disclose wherein each of the two-terminal selector and the two-terminal selector is a non-linear diode. However, Laurent discloses: wherein each of the two-terminal read selector (105 per [0036]) and the two-terminal write selector (105 per [0036]) is a non-linear diode (per [0049]). (Fig. 3) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yoshikawa in view of Chiang and Laurent for each of the two-terminal read selector and the two-terminal write selector is a non-linear diode in order to “include increasing memory cell density, increasing read/write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics.” (Laurent, [0004]) Regarding claim 8 , Yoshikawa in view of Chiang disclose the memory device of claim 1. Yoshikawa in view of Chiang do not disclose wherein each of the two-terminal read selector and the two-terminal write selector includes a switching layer sandwiched between a first conductor layer and a second conductor layer. However, Laurent discloses: wherein each of the two-terminal read selector (105 per [0036]) and the two-terminal write selector (105 per [0036]) includes a switching layer (320) sandwiched between a first conductor layer (305-b) and a second conductor layer (305-a). ([0049], Fig. 3) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yoshikawa in view of Chiang and Laurent for each of the two-terminal read selector and the two-terminal write selector includes a switching layer sandwiched between a first conductor layer and a second conductor layer in order to “include increasing memory cell density, increasing read/write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics.” (Laurent, [0004]) Regarding alim 9 , Laurent discloses the memory device of claim 8, wherein the switching layer (320) in the two-terminal read selector(105 per [0036]) and the switching layer in the two-terminal write selector (105 per [0036]) are formed from a same layer of switching material (320). (Fig. 3) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yoshikawa in view of Chiang and Laurent for similar reasons mentioned beforehand. Regarding claim 10 , Laurent discloses the memory device of claim 8, wherein at least the switching layer (320) in the two-terminal write selector (105 per [0036]) includes a phase-change material. ([0051]-[0052], Fig. 3) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yoshikawa in view of Chiang and Laurent for similar reasons mentioned beforehand. Regarding claim 11 , Laurent discloses the memory device of claim 8, wherein at least the switching layer (320) in the two-terminal write selector (105 per [0036]) includes a chalcogenide material (per 0051]-[0052]) or a solid-electrolyte material. (Fig. 3) It would have been obvious to one skilled in the art before the effective filing date to combine the teachings of Yoshikawa in view of Chiang and Laurent for similar reasons mentioned beforehand. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY BLACKWELL whose telephone number is (703)756-1508. The examiner can normally be reached Mon-Fri 8:00-1600. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ASHLEY NICOLE BLACKWELL/Examiner, Art Unit 2897 /JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897 Application/Control Number: 18/625,485 Page 2 Art Unit: 2897 Application/Control Number: 18/625,485 Page 3 Art Unit: 2897 Application/Control Number: 18/625,485 Page 4 Art Unit: 2897 Application/Control Number: 18/625,485 Page 5 Art Unit: 2897 Application/Control Number: 18/625,485 Page 6 Art Unit: 2897 Application/Control Number: 18/625,485 Page 7 Art Unit: 2897 Application/Control Number: 18/625,485 Page 8 Art Unit: 2897 Application/Control Number: 18/625,485 Page 9 Art Unit: 2897 Application/Control Number: 18/625,485 Page 10 Art Unit: 2897 Application/Control Number: 18/625,485 Page 11 Art Unit: 2897 Application/Control Number: 18/625,485 Page 12 Art Unit: 2897 Application/Control Number: 18/625,485 Page 13 Art Unit: 2897 Application/Control Number: 18/625,485 Page 14 Art Unit: 2897
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