Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 9-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsieh et al (US 2023/0102166 A1).
Hsieh discloses a method of manufacturing a semiconductor structure [0001], comprising:
providing a substrate 10 and an active device level 10 (e.g., metal layers [0034], dielectric [0035]) on the substrate (Fig. 17A));
forming a stack film layer 20 (e.g., interlayer dielectric, [0037]) on the active device layer;
forming a resist platform layer 110ˊ [0109], [0117] on the stack film layer (Fig. 16);
depositing a blocking layer 115 (“middle layer” [0118]) on the resist platform layer conformally (Fig. 16);
forming a photoresist layer 120 [0118] on the blocking layer, wherein a top surface of the photoresist layer is higher than a topmost surface of the blocking layer (as depicted in Fig. 16);
etching the resist platform layer until exposing a plurality of top surfaces of the blocking layer to form a plurality of first openings (Fig. 17A, [0123]) and
etching the blocking layer, the resist platform layer and the stack film layer based on the plurality of first openings until exposing a plurality of top surfaces of the active device layer to form a plurality of second openings (Fig. 17B, [0124]).
As to claims 9 and 10, Hsieh teaches the cited selectivity because the openings are formed by etching one layer relative to other layers to obtain the cited openings (see Fig. 17A-17B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-8, 11-14 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al (US 2023/0102166 A1).
The discussion of Hsieh from above is repeated here.
As to claim 2, Hsieh teaches, with respect to a different embodiment, etching the plurality of first openings comprising: forming a reticle layer 30 containing a hole pattern 35 by a lithography process on the photoresist layer, wherein the reticle layer exposes a plurality of exposed top surfaces of the photoresist layer (see Fig. 3B); etching the photoresist layer at positions of the plurality of exposed top surfaces of the photoresist layer until exposing the plurality of top surfaces of the blocking layer; and removing the reticle layer (Fig. 5).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to include a reticle layer and remove it as cited in the method of Hsieh because Hsieh teaches in a different embodiment that such a technique is useful for forming patterns and such is expected to give the predictable result of a patterned layer.
As to claim 3, the modified method of Hsieh teaches that the hole pattern corresponds to an area of the plurality of first openings (see Figures 3, 5).
As to claim 4, the modified method of Hsieh teaches that the hole pattern is determined by a boundary rule in which distances D1 are 5-20 nm, or 0.005-0.02 microns, between the edge of one pattern and the edge of a neighboring pattern, and distances D3 are 0.005-0.02 microns [0088].
As to claim 5, the modified method of Hsieh teaches that distances of 0.02 microns or less are measured [0088]. D3 is a distance from an edge to edge of adjacent openings. Hsieh does not teach the distances from an edge of each of the plurality of first openings to a closest edge of the resist platform layer. However this is within the scope of one skilled in the art because the distances taught by Hsieh are smaller than the cited range. It is within the scope of one skilled in the art to use greater distances because it is harder to obtain the smaller distances. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to provide the cited distances of from 0.1 micrometers to 5 micrometers in a top view in the modified method of Hsieh because it is within the scope of one skilled in the art and because Hsieh discloses the claimed invention except for the cited distances. It would have been an obvious matter of design choice to provide the cited distances, since such a modification would have involved a mere change in the size of a component. A change of size is generally recognized as being within the ordinary level of skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
As to claim 6, Hsieh discloses in a different embodiment that a conductive material 150 is filled in the plurality of second openings to form a plurality of interconnect structures in the stack film layer (Fig. 18C, [0125]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to fill the plurality of second openings with conductive material as cited in the modified method of Hsieh because Hsieh teaches that such is a useful process to form desired structures in a semiconductor substrate.
As to claim 7, Hsieh teaches in some embodiments that the resist platform layer is a KrF photoresist layer [0077]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to use a KrF photoresist in the modified method of Hsieh because Hsieh teaches that it is a useful photoresist material and such is expected to give the predictable result of a patterned photoresist layer.
As to claim 8, Hsieh teaches in some embodiments that the resist platform layer is a ArF photoresist layer [0077]. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to use a ArF photoresist in the modified method of Hsieh because Hsieh teaches that it is a useful photoresist material and such is expected to give the predictable result of a patterned photoresist layer.
As to claim 11, Hsieh discloses a method of manufacturing a semiconductor structure [0001], comprising:
providing a substrate 10 and an active device level 10 (e.g., metal layers [0034], dielectric [0035]) on the substrate (Fig. 17A));
forming a stack film layer 20 (e.g., interlayer dielectric, [0037]) on the active device layer;
forming a resist platform layer 110ˊ [0109], [0117] on the stack film layer (Fig. 16);
depositing a blocking layer 115 (“middle layer” [0118]) on the resist platform layer conformally (Fig. 16);
forming a photoresist layer 120 [0118] on the blocking layer, wherein a top surface of the photoresist layer is higher than a topmost surface of the blocking layer (as depicted in Fig. 16);
etching the resist platform layer until exposing a plurality of top surfaces of the blocking layer to form a plurality of first openings (Fig. 17A, [0123]) and
etching the blocking layer, the resist platform layer and the stack film layer based on the plurality of first openings until exposing a plurality of top surfaces of the active device layer to form a plurality of second openings (Fig. 17B, [0124]).
More specifically with respect to claim 11, claim 11 further recites that “resist platform layer on the stack film” is “based on a hole pattern.” This limitation is interpreted as requiring that the resist platform layer itself is patterned with a hole pattern. Broadly interpreted, platform resist layer 110ˊ includes/based on pattern 55ˊ because it is deposited on layer 20 and fills the gaps that include hole pattern 55ˊ (see Fig. 8, Fig. 16, [0085]).
Claim 11 also further recites that the photoresist layer is etched “based on the hole pattern” to form “a plurality of first openings” and the hole pattern corresponds to “an area” of the plurality of first openings. Broadly interpreted, Hsieh also discloses this limitation because photoresist layer 120 is etched to form opening 130 that eventually is connected to pattern 55ˊ to form an opening that correspond to each other (see Fig. 17B) enabling a continuous hole pattern to be formed in the layers present in an area of the first openings. Figure 17B shows only one opening, not a plurality of first openings. However, the figures also show a small portion of the wafer surface, and the process would be repeated across the surface in order to form the final device. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to form a plurality of first openings rather than just a single opening as depicted in Figures 17A, 17B in the method of Hsieh because figures are idealized and the final product would have more openings across the wafer surface in order to form the final product with sufficient yield.
Still further as to claim 11, Hsieh discloses that the blocking layer is etched “based on the plurality of first openings” to form a plurality of second openings because opening 130ˊ aligns with the first plurality of openings to form a continuous opening that spans layers 120 through 20.
As to claim 12, see the rejection of claim 5. It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to provide the cited distances of from 0.1 micrometers to 5 micrometers in a top view in the modified method of Hsieh because it is within the scope of one skilled in the art and because Hsieh discloses the claimed invention except for the cited distances. It would have been an obvious matter of design choice to provide the cited distances, since such a modification would have involved a mere change in the size of a component. A change of size is generally recognized as being within the ordinary level of skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955).
As to claim 13, Hsieh discloses that the hole pattern 55 comprises a multiple-hole pattern (see Fig. 6).
As to claim 14, Hsieh discloses a thickness of the resist platform layer 110 of 10-2000 nm [0089], which encompasses the cited range.
As to claim 16, Hsieh discloses in other embodiments that the photoresist layer may serve as a negative photoresist layer (Fig. 3B, [0040]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to provide a negative photoresist layer as cited in the modified method of Hsieh because Hsieh teaches that they are useful photoresists layers to include and such are expected to give the predictable result of a patterned layer.
As to claims 17 and 18, Hsieh discloses the cited selectivities because the openings are formed through the layers without significant etching of overlying layers compared to underlying layers as depicted in Figure 17B.
As to claim 19, Hsieh teaches in a different embodiment that a conductive material 150 is filled in the plurality of second openings to form a plurality of interconnect structures in the stack film layer, followed by a planarizing to a coplanar surfaces as cited (see Fig. 18C, [0125]). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to fill the plurality of second openings with conductive material as cited, planarize and provide coplanar surfaces as cited in the modified method of Hsieh because Hsieh teaches that such is a useful process to form desired structures in a semiconductor substrate.
As to claim 20, Hsieh discloses that a bottom surface of the conductive layer, if deposited in the embodiment of Figure 17B, contacts each of the plurality of top surfaces of the active device layer (Fig. 18C depicts how the opening is filled with the conductive layer). It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have the conductive layer contact the top surfaces of the active device layer as cited because this is taught by Hsieh to have exposed surfaces in openings ready for filling with conductive material, and such is expected to give the predictable result of a useful semiconductor contact structure.
Allowable Subject Matter
Claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art fails to disclose a method of manufacturing a semiconductor structure wherein a second thickness measured from a top surface of the photoresist layer to a top surface of the blocking layer on the stack film layer is greater than a first thickness measured from the top surface of the photoresist layer to the top surface of the blocking layer on the resist platform layer, as in the context of claim 15.
The closest prior art, Hsieh, discloses a method as cited with a stack film layer, resist platform layer, blocking layer, photoresist layer and etching (see rejection of claim 11). However, Hsieh discloses that layer 110 is a planarizing layer or a spin-on carbon layer [0089]. This provides for an even, planar layer, not a layer that has different thicknesses. Therefore, Hsieh discloses the opposite of what is claimed, i.e., that the first distance and the second distance are equal, not different. There is no motivation to modify the method of Hsieh to arrive at the claimed invention because such is a different structure that changes the structure of any final device that would eventually be formed. Accordingly, there is no motivation provided in the prior art or Hsieh to provide a method where a second thickness is greater than a first thickness, as in the context of claim 15.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Chang et al (US 11,887,851 B2), Peng et al (US 2019/0148221 A1), Chang et al (US 10,916,427 B2) are cited to show a method with depositing and etching steps. Yano et al (US 2020/0216670 A1) is cited to show a method with ALD of a middle layer of a tri-layer resist [0040], [0199]. Kori et al (US 2012/0252218 A1) is also cited to show ALD of a middle layer of a tri-layer resist [0057], [0117].
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/ANITA K ALANKO/ Primary Examiner, Art Unit 1713