Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of the Group I invention (a method) and Species D (reading on Fig. 10C) in the reply filed on 8/11/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/13/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 21-25 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nam (US 20230411487 A1).
Regarding independent claim 21, Nam discloses a method (Fig. 8A), comprising:
forming, above a substrate (100; [0029]: “semiconductor substrate”) of a semiconductor device, a layer stack (STP) comprising a plurality of sacrificial nanostructure layers (SAL; [0094]: “sacrificial layers”) and a plurality of nanostructure channel layer stacks (ACL; [0094]: “active layers”),
wherein the plurality of sacrificial nanostructure layers and the plurality of nanostructure channel layer stacks are arranged in a direction (D3 direction) that is approximately perpendicular to the substrate, and
wherein a nanostructure channel layer stack (one of the ACL duplications), of the plurality of nanostructure channel layer stacks, comprises a nanostructure channel layer (one of ACL) and at least one supporting dielectric layer (BL; [0094]: “BL may include silicon (Si) and oxygen (O)”; [0112]: “a crystalline dielectric layer”) between (“between” in the D3 direction) the nanostructure channel layer and a sacrificial nanostructure layer of the plurality of sacrificial nanostructure layers (BL is sandwiched between each combination of ACL/SAL);
etching the layer stack ([0100]: “patterning process…etch”) to form a fin structure (Fig. 8B: AP1; [0100]: “defining…AP1”) that comprises the plurality of sacrificial nanostructure layers and the plurality of nanostructure channel layer stacks (these “stacks” are shown in method step Fig. 8B);
etching the plurality of sacrificial nanostructure layers ([0112]: “etching process”) to form cavities (IDR) between the plurality of nanostructure channel layer stacks;
forming an inner spacer layer (ISP) in the cavities and on exposed portions of the plurality of nanostructure channel layer stacks ([0112]: “formed…fill”);
etching the inner spacer layer ([0113]: “wet etching”) to form inner spacers in the cavities ([0113]: “may form the inner spacer”),
wherein etching the inner spacer layer results in ends of the plurality of nanostructure channel layer stacks being exposed ([0113]: “exposed”); and
forming a source/drain contact layer (Fig. 10A: SD1) on the fin structure such that the source/drain contact layer is in contact with the ends of the plurality of nanostructure channel layer stacks (there is a SD1 directly contacting each D2 side of ACL).
Illustrated below is Fig. 9A of Nam.
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Regarding claim 22, Nam discloses the method of claim 21 (Fig. 9A), wherein the inner spacers have an approximately C-shaped cross-sectional profile (the 3 unexposed surfaces of ISP form a C shape).
Regarding claim 23, Nam discloses the method of claim 21 (Fig. 9A), wherein an end of the at least one supporting dielectric layer is curved (RS1 is curved and exposes layer BL, thus BL “is curved” at RS1).
Regarding claim 24, Nam discloses the method of claim 21 (Fig. 9A), wherein an end of the nanostructure channel layer extends laterally outward (D2 direction) from an end of the at least one supporting dielectric layer.
Regarding claim 25, Nam discloses the method of claim 21 (Fig. 9A), further comprising: performing an etch operation (the same etch operation cited in claim 21 used when “etching the inner spacer”; [0112]: “etching process”) to laterally (D2 direction) etch the at least one supporting dielectric layer.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized claim limitations indicate limitations that are not explicitly disclosed in the primary reference (or combination of references), but are disclosed or rendered obvious by secondary references or remarks.
Claims 26-27 are rejected under 35 U.S.C. 103 as being unpatentable over Nam as applied to claim 25 above, and further in view of Chang (US 20220352349 A1) and Yin (US 20220157969 A1).
Regarding claim 26, Nam discloses the method of claim 25, but fails to teach 1) any specific etchant composition, and 2) Nam only teaches performing a wet etch operation (i.e., a liquid, [0113]: “wet etching”). Thus, Nam fails to teach “wherein the etch operation is performed with a hydrofluoric acid (HF) vapor”.
Chang teaches the etch operation ([0050]: “dry-etching process”) is performed with a hydrofluoric acid (HF) vapor (Note: a generic vapor is relied upon here, See additional remarks below; [0050]: “dry-etching process”).
Modifying the etch operation (of Nam) by choosing a “vapor” etchant (from Chang) would arrive at the claimed etch operation configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation “the inner spacer layer” is a similar dielectric material (Nam: [0094]: “BL may include silicon (Si) and oxygen (O)”; [0112]: “a crystalline dielectric layer”; Chang: [0049]: “SiO2”) similarly etched “to form inner spacers in the cavities” (Nam: Fig. 9A: spacers ISP; Chang: Fig. 10A: spacers 206). Chang provides a teaching to motivate one of ordinary skill in the art before the effective filing date to incorporate the claimed etch operation configuration in that it would enhance manufacturing properties of the etch by reducing reliance on masking techniques ([0050]: “self-aligned”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed etch operation because it would enhance manufacturing properties of the etch. MPEP 2143 (I)(G). MPEP 2143 (I)(C) has also been considered.
Illustrated below is Fig. 10A of Chang.
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Nam in view of Chang fails to teach fails to teach any specific etchant composition. Thus, Nam fails to teach “wherein the etch operation is performed with a hydrofluoric acid (HF) vapor”.
Yin discloses wherein the etch operation (Fig. 13) is performed with a hydrofluoric acid (HF) vapor ([0027]: “hydrogen fluoride…gas”). Modifying the etch operation (of Nam in view of Chang) by choosing a “hydrofluoric acid (HF)” etchant (from Yin) would arrive at the claimed etch operation configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation “the inner spacer layer” is a similar dielectric material (Nam: [0094]: “BL may include silicon (Si) and oxygen (O)”; [0112]: “a crystalline dielectric layer”; Yin: [0026]: “silicon oxide”) similarly etched “to form inner spacers in the cavities” (Nam: Fig. 9A: spacers ISP; Ying: Fig. 13: spacers 236). Since Nam, Chang, and Yin are in the same field of endeavor, a person having ordinary skill in the art before the effective filing date would have readily recognized the finite number of predictable solutions for etchant composition. These predictable solutions include “hydrofluoric acid (HF)” (Yin: [0027]). Absent unexpected results, it would have been obvious to one having ordinary skill in the art before the effective filing date to try using a different etchant composition. Therefore, the claim would have been obvious to one of ordinary skill in the art before the effective filing date because “a person of ordinary skill has good reason to pursue the known options within his or her technique grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense.” MPEP 2143 (1)(E).
Illustrated below is Fig. 13 of Yin.
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Regarding claim 27, Nam in view of Chang and Yin discloses the method of claim 26 (Nam: Fig. 9A), wherein an end of the at least one supporting dielectric layer (D2 facing “end”) is recessed (D2 “recessed”) relative to an end of the nanostructure channel layer (D2 facing “end”), and ends of a subset of the inner spacers adjacent to the nanostructure channel layer stack are approximately co-planar (all ends have surfaces along RS1, and thus “are approximately co-planar”. Similarly, Chang: 10A illustrates “approximately co-planar” within the breadth of the claim as written).
Claims 1-2 and 28-29 are rejected under 35 U.S.C. 103 as being unpatentable over Nam in view of Chang.
Regarding claim 1, Nam discloses a method (Fig. 8A), comprising:
forming, above a substrate (100; [0029]: “semiconductor substrate”) of a semiconductor device, a layer stack (STP) comprising a plurality of sacrificial nanostructure layers (SAL; [0094]: “sacrificial layers”) and a plurality of nanostructure channel layer stacks (ACL; [0094]: “active layers”),
wherein the plurality of sacrificial nanostructure layers and the plurality of nanostructure channel layer stacks are arranged in a direction (D3 direction) that is approximately perpendicular to the substrate, and
wherein a nanostructure channel layer stack (one of the ACL duplications), of the plurality of nanostructure channel layer stacks, comprises a nanostructure channel layer (one of ACL) and at least one supporting dielectric layer (BL; [0094]: “BL may include silicon (Si) and oxygen (O)”; [0112]: “a crystalline dielectric layer”) between (“between” in the D3 direction) the nanostructure channel layer and a sacrificial nanostructure layer of the plurality of sacrificial nanostructure layers (BL is sandwiched between each combination of ACL/SAL);
etching the layer stack ([0100]: “patterning process…etch”) to form a fin structure (Fig. 8B: AP1; [0100]: “defining…AP1”) that comprises the plurality of sacrificial nanostructure layers and the plurality of nanostructure channel layer stacks (these “stacks” are shown in method step Fig. 8B);
etching the plurality of sacrificial nanostructure layers ([0112]: “etching process”) to form cavities (IDR) between the plurality of nanostructure channel layer stacks;
forming an inner spacer layer (ISP) in the cavities and on exposed portions of the plurality of nanostructure channel layer stacks ([0112]: “formed…fill”);
performing a dry etch operation to etch the inner spacer layer ([0113]: “wet etching”. Note: wet etching is cited here, and additional remarks are provided below regarding “dry etch”) to form inner spacers in the cavities ([0113]: “may form the inner spacer”),
wherein the dry etch operation results in ends of the plurality of nanostructure channel layer stacks being exposed ([0113]: “exposed”); and
forming a source/drain contact layer (Fig. 10A: SD1) on the fin structure such that the source/drain contact layer is in contact with the ends of the plurality of nanostructure channel layer stacks (there is a SD1 directly contacting each D2 side of ACL).
Nam fails to teach “performing a dry etch operation to etch the inner spacer layer to form inner spacers in the cavities, wherein the dry etch operation results in ends of the plurality of nanostructure channel layer stacks being exposed” because Nam only teaches performing a wet etch operation ([0113]: “wet etching”).
Chang teaches performing a dry etch operation ([0050]: “dry-etching process”) to etch the inner spacer layer (Fig. 9A: layer 306) to form inner spacers (Fig. 10A: spacers 206) in the cavities (Fig. 8A: cavities 205), wherein the dry etch operation results in ends of the plurality of nanostructure channel layer stacks being exposed (Fig. 10A shows ends of 120 being exposed).
Modifying the etch operation (of Nam) by choosing “a dry etch operation” (from Chang) would arrive at the claimed etch operation configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation “the inner spacer layer” is a similar dielectric material (Nam: [0094]: “BL may include silicon (Si) and oxygen (O)”; [0112]: “a crystalline dielectric layer”; Chang: [0049]: “SiO2”) similarly etched “to form inner spacers in the cavities” (Nam: Fig. 9A: spacers ISP; Chang: Fig. 10A: spacers 206). Chang provides a teaching to motivate one of ordinary skill in the art before the effective filing date to incorporate the claimed etch operation configuration in that it would enhance manufacturing properties of the etch by reducing reliance on masking techniques ([0050]: “self-aligned”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed etch operation because it would enhance manufacturing properties of the etch. MPEP 2143 (I)(G). MPEP 2143 (I)(C) has also been considered.
Regarding claim 2, Nam in view of Chang discloses the method of claim 1 (Nam: Fig. 9A), wherein, after the dry etch operation, an end of the nanostructure channel layer (D2 facing “end”), an end of the at least one supporting dielectric layer (D2 facing “end”), and ends of a subset of the inner spacers (D2 facing “end”) adjacent to the nanostructure channel layer stack are approximately co-planar (all ends have surfaces along RS1, and thus “are approximately co-planar”. Similarly, Chang: 10A illustrates “approximately co-planar” within the breadth of the claim as written).
Regarding independent claim 28, Nam discloses a method (Fig. 8A), comprising:
forming a layer stack (STP) comprising a plurality of sacrificial nanostructure layers (SAL; [0094]: “sacrificial layers”) alternately arranged with a plurality of nanostructure channel layer stacks (ACL; [0094]: “active layers”),
wherein a nanostructure channel layer stack (one of the ACL duplications), of the plurality of nanostructure channel layer stacks, comprises a nanostructure channel layer (one of ACL) between (“between” in the D3 direction) a top supporting dielectric layer (BL; [0094]: “BL may include silicon (Si) and oxygen (O)”; [0112]: “a crystalline dielectric layer”) and a bottom supporting dielectric layer (BL is sandwiching each ACL, thus there is a “top” and “bottom” layer);
etching the layer stack ([0100]: “patterning process…etch”) to form a fin structure (Fig. 8B: AP1; [0100]: “defining…AP1”) that comprises the plurality of sacrificial nanostructure layers and the plurality of nanostructure channel layer stacks (these “stacks” are shown in method step Fig. 8B);
etching the plurality of sacrificial nanostructure layers ([0112]: “etching process”) to form cavities (IDR) between the plurality of nanostructure channel layer stacks;
forming an inner spacer layer (ISP) in the cavities and on exposed portions of the plurality of nanostructure channel layer stacks ([0112]: “formed…fill”);
performing a dry etch operation to etch the inner spacer layer ([0113]: “wet etching”. Note: wet etching is cited here, and additional remarks are provided below regarding “dry etch”) to form inner spacers in the cavities ([0113]: “may form the inner spacer”),
wherein the dry etch operation results in ends of the plurality of nanostructure channel layer stacks being exposed ([0113]: “exposed”); and
forming a source/drain contact layer (Fig. 10A: SD1) on the fin structure such that the source/drain contact layer is in contact with the ends of the plurality of nanostructure channel layer stacks (there is a SD1 directly contacting each D2 side of ACL).
Nam fails to teach “performing a dry etch operation to etch the inner spacer layer to form inner spacers in the cavities, wherein the dry etch operation results in ends of the plurality of nanostructure channel layer stacks being exposed” because Nam only teaches performing a wet etch operation ([0113]: “wet etching”).
Chang teaches performing a dry etch operation ([0050]: “dry-etching process”) to etch the inner spacer layer (Fig. 9A: layer 306) to form inner spacers (Fig. 10A: spacers 206) in the cavities (Fig. 8A: cavities 205), wherein the dry etch operation results in ends of the plurality of nanostructure channel layer stacks being exposed (Fig. 10A shows ends of 120 being exposed).
Modifying the etch operation (of Nam) by choosing “a dry etch operation” (from Chang) would arrive at the claimed etch operation configuration. A person of ordinary skill in the art before the effective filing date would have had a reasonable expectation of success doing so because in each situation “the inner spacer layer” is a similar dielectric material (Nam: [0094]: “BL may include silicon (Si) and oxygen (O)”; [0112]: “a crystalline dielectric layer”; Chang: [0049]: “SiO2”) similarly etched “to form inner spacers in the cavities” (Nam: Fig. 9A: spacers ISP; Chang: Fig. 10A: spacers 206). Chang provides a teaching to motivate one of ordinary skill in the art before the effective filing date to incorporate the claimed etch operation configuration in that it would enhance manufacturing properties of the etch by reducing reliance on masking techniques ([0050]: “self-aligned”). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to have the claimed etch operation because it would enhance manufacturing properties of the etch. MPEP 2143 (I)(G). MPEP 2143 (I)(C) has also been considered.
Regarding claim 29, Nam in view of Chang discloses the method of claim 28 (Nam: Fig. 9A), wherein, after the dry etch operation, an end of the nanostructure channel layer (D2 facing “end”), an end of the top supporting dielectric layer (D2 facing “end”), an end of the bottom supporting dielectric layer (D2 facing “end”), and ends of a subset of the inner spacers (D2 facing “end”) adjacent to the nanostructure channel layer stack are approximately co-planar (all ends have surfaces along RS1, and thus “are approximately co-planar”. Similarly, Chang: 10A illustrates “approximately co-planar” within the breadth of the claim as written).
Allowable Subject Matter
Claims 3-7 and 30-33 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the allowable subject matter of claims 3-7 is the inclusion of the limitation “further comprising: performing, using a wet etchant, a wet etch operation after the dry etch operation to etch the at least one supporting dielectric layer” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “wet etch operation”, “after”, and “supporting dielectric layer” in combination with all other limitations in claims 3 and 1. The claimed etch configuration goes beyond a mere adjustment of etching configuration because it also requires performing the etch upon materials that wouldn’t be etched in the teachings of the prior art. MPEP 2144.04 (IV)(C).
The primary reason for the allowable subject matter of claims 30-33 is the inclusion of the limitation “further comprising: performing, using a wet etchant, a wet etch operation after the dry etch operation to etch the top supporting dielectric layer and the bottom supporting dielectric layer” in combination with the other limitations in the claim. For example, prior art of record fails to teach or be reasonably combined to render obvious the claimed limitations “wet etch operation”, “after”, and “supporting dielectric layer” in combination with all other limitations in claims 3 and 1. The claimed etch configuration goes beyond a mere adjustment of etching configuration because it also requires performing the etch upon materials that wouldn’t be etched in the teachings of the prior art. MPEP 2144.04 (IV)(C).
Conclusion
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
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