DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-5, 9, 12 and 21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Bhushan et al. (U.S. Publication No. 2025/0309215).
Regarding claim 1, Bhushan teaches a semiconductor package, comprising:
an interposer (Fig. 13, interposer 1306);
a first semiconductor chip (445/605) disposed over the interposer, and having a first surface and a second surface opposite to each other (top and bottom surfaces);
a second semiconductor chip (805) disposed over the first semiconductor chip, and having a top surface and a bottom surface opposite to each other (Fig. 13); and
a dielectric sidewall (502) disposed along a side of the first semiconductor chip and over the interposer (Fig. 13), wherein at least one first via structure (1105) is disposed vertically through the dielectric sidewall and electrically connected to a power distribution network (PDN) (see paragraph [0086] and [0092]).
Regarding claim 4, Bhushan teaches the semiconductor package of claim 1, wherein the first semiconductor chip and the second semiconductor chip are bonded to each other by a plurality of second hybrid bonds between the second surface of the first semiconductor chip and the bottom surface of the second semiconductor chip (paragraph [0072]).
Regarding claim 5, Bhushan teaches the semiconductor package of claim 4, wherein the plurality of second hybrid bonds are formed by a plurality of third bonding pad metals (Fig. 6, pads 504) embedded into and flush with the second surface of the first semiconductor chip (Fig. 6) and a plurality of fourth bonding pad metals (608) embedded into and flush with the bottom surface of the second semiconductor chip (Fig. 6).
Regarding claim 9, Bhushan teaches the semiconductor package of claim 1, wherein the first semiconductor chip comprises a graphics processing unit (GPU) chip (Fig. 3, first chip can be chip 805, which is a GPU, paragraph [0077]).
Regarding claim 12, Bhushan teaches a semiconductor package, comprising:
a first semiconductor chip (Fig. 13, chip 445/605) disposed over an interposer (1306), and having a first surface and a second surface opposite to each other (top and bottom); and
at least one dielectric sidewall (502) disposed along a side of the first semiconductor chip and over the interposer (Fig. 13), wherein at least one a first via structure (1105) is disposed vertically through the dielectric sidewall and electrically connected to a power distribution network (PDN) via the interposer (paragraph [0086] and [0092]).
Regarding claim 21, Bhushan teaches a semiconductor package, comprising:
a first semiconductor chip (Fig. 13, 445/605) disposed over an interposer (1306), and having a first surface and a second surface opposite to each other (top and bottom);
a second semiconductor chip (805) disposed over the first semiconductor chip, and having a top surface and a bottom surface opposite to each other (Fig. 13); and
a dielectric sidewall (502) disposed along a side of the first semiconductor chip and over the interposer (Fig. 13), wherein at least one first via structure (1105) is disposed vertically through the dielectric sidewall and electrically connected to a power distribution network (PDN) (paragraph [0086] and [0092]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-3, 15 and 22-23 are rejected under 35 U.S.C. 103 as being unpatentable over Bhushan in view of Mun et al. (U.S. Publication No. 2025/0323196).
Regarding claim 2, Bhushan teaches the semiconductor package of claim 1, but does not teach wherein the first semiconductor chip and the interposer are bonded to each other by a plurality of first hybrid bonds between the first surface of the first semiconductor chip and a top surface of the interposer.
However, Mun teaches that an interposer can be hybrid bonded to a first chip in a stack (Mun paragraph [0038], Fig. 4). It would have been obvious to a person of skill in the art at the time of the effective filing date that a pre-made interposer and hybrid bond could have been used because this allows the interposer to be fabricated separately instead of requiring fabrication of the interposer as a part of packaging, reducing steps of packaging, and that hybrid bonds could have been used because it would have been a simple substitution of any other known bonding technique for hybrid bonding with predictable results
Regarding claim 3, Bhushan in view of Mun teaches the semiconductor package of claim 2, wherein the plurality of first hybrid bonds are formed by a plurality of first bonding pad metals (BPMs) embedded into and flush with the first surface of the first semiconductor chip and a plurality of second bonding pad metals embedded into and flush with the top surface of the interposer (see hybrid bonds of Bhushan Fig. 4, it would have been obvious that similar hybrid bonds could have been used between the chip and a pre-made interposer because hybrid bonding by definition requires both metal-metal and dielectric-dielectric contact).
Regarding claim 15, Bhushan teaches the semiconductor package of claim 12, but does not teach wherein the first semiconductor chip and the interposer are bonded to each other by a plurality of first hybrid bonds between the first surface of the first semiconductor chip and a top surface of the interposer.
However, Mun teaches that an interposer can be hybrid bonded to a first chip in a stack (Mun paragraph [0038], Fig. 4). It would have been obvious to a person of skill in the art at the time of the effective filing date that a pre-made interposer and hybrid bond could have been used because this allows the interposer to be fabricated separately instead of requiring fabrication of the interposer as a part of packaging, reducing steps of packaging, and that hybrid bonds could have been used because it would have been a simple substitution of any other known bonding technique for hybrid bonding with predictable results.
Regarding claim 22, Bhushan teaches the semiconductor package of claim 21, but does not teach wherein the first semiconductor chip and the interposer are bonded to each other by a plurality of first hybrid bonds between the first surface of the first semiconductor chip and a top surface of the interposer.
However, Mun teaches that an interposer can be hybrid bonded to a first chip in a stack (Mun paragraph [0038], Fig. 4). It would have been obvious to a person of skill in the art at the time of the effective filing date that a pre-made interposer and hybrid bond could have been used because this allows the interposer to be fabricated separately instead of requiring fabrication of the interposer as a part of packaging, reducing steps of packaging, and that hybrid bonds could have been used because it would have been a simple substitution of any other known bonding technique for hybrid bonding with predictable results
Regarding claim 23, Bhushan teaches the semiconductor package of claim 22, wherein the plurality of first hybrid bonds are formed by a plurality of first bonding pad metals (BPMs) embedded into and flush with the first surface of the first semiconductor chip and a plurality of second bonding pad metals embedded into and flush with the top surface of the interposer (see hybrid bonds of Bhushan Fig. 4, it would have been obvious that similar hybrid bonds could have been used between the chip and a pre-made interposer because hybrid bonding by definition requires both metal-metal and dielectric-dielectric contact).
Claims 6-8, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Bhushan in view of Chung et al. (U.S. Publication No. 2024/0222273)
Regarding claim 6, Bhushan teaches the semiconductor package of claim 1, wherein the second semiconductor chip is a high bandwidth memory (HBM) stack that comprises:
a logic base layer (see Fig. 3, can also be formed with CPU/GPU chip 805 as first chip and chips 605/445 as second chip, 605 is a logic base layer of an HBM); and
a plurality of HBM layers on the logic base layer (445), and stacked on top of one another.
Chung further teaches that the first chip can be a processor, and second chip can be an HBM stack with the through dielectric via arrangement of Bhushan Fig. 13 (Chung Fig. 1 and paragraphs [0056] and [0057]). It would have been obvious to a person of skill in the art at the time of the effective filing date that the interposer-logic-HBM stack arrangement of Bhushan Fig. 3 and Chung could have been utilized with the power via arrangement of Bhushan because it would have been a simple substitution of one stacking order for another with predictable results.
Regarding claim 7, Bhushan teaches the semiconductor package of claim 6, wherein a first layer and a second layer of the HBM stack respectively having a third surface and a fourth surface facing each other are bonded by a plurality of third hybrid bonds between the third surface of the first layer and the fourth surface of the second layer of the HBM stack (Bhushan paragraph [0066]).
Regarding claim 8, Bhushan teaches the semiconductor package of claim 7, wherein the plurality of third hybrid bonds are formed through a plurality of fifth bonding pad metals (Fig. 4, pads 410) embedded into and flush with the third surface of the first layer of the HBM stack (Fig. 4) and a plurality of sixth bonding pad metals (also labeled 410) embedded into and flush with the fourth surface of the second layer of the HBM stack (Fig. 4).
Regarding claim 16, Bhushan teaches the semiconductor package of claim 12, further comprising:
a second semiconductor chip (805) disposed over the first semiconductor chip and having a top surface and a bottom surface opposite to each other (Fig. 13).
Bhushan does not specifically teach wherein the second semiconductor chip is a high bandwidth memory (HBM) stack that comprises a logic base layer, and plurality of HBM layers on the logic base layer and stacked on top of one another. Bhushan teaches a package can also be formed with CPU/GPU chip 805 as first chip and chips 605/445 as second chip, 605 is a logic base layer of an HBM (Fig. 3). Chung further teaches that the first chip can be a processor, and second chip can be an HBM stack with the through dielectric via arrangement of Bhushan Fig. 13 (Chung Fig. 1 and paragraphs [0056] and [0057]). It would have been obvious to a person of skill in the art at the time of the effective filing date that the interposer-logic-HBM stack arrangement of Bhushan Fig. 3 and Chung could have been utilized with the power via arrangement of Bhushan because it would have been a simple substitution of one stacking order for another with predictable results.
Regarding claim 17, Bhushan in view of Chung teaches the semiconductor package of claim 16, wherein the first semiconductor chip and the second semiconductor chip are bonded to each other by a plurality of second hybrid bonds between the second surface of the first semiconductor chip and the bottom surface of the second semiconductor chip (paragraph [0072]).
Allowable Subject Matter
Claims 10-11 and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 10-11 and 13-14, the prior art, alone or in combination, fails to teach or suggest wherein the first semiconductor chip comprises a metal line on the backside thereof and electrically connected to the first via structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Evan G Clinton whose telephone number is (571)270-0525. The examiner can normally be reached Monday-Friday at 8:30am to 5:30pm.
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/EVAN G CLINTON/ Primary Examiner, Art Unit 2899
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