Prosecution Insights
Last updated: October 01, 2026
Application No. 18/627,570

METAL-INSULATOR-METAL DEVICE STRUCTURES AND METHODS OF FORMING THE SAME

Non-Final OA §103
Filed
Apr 05, 2024
Priority
Dec 14, 2023 — provisional 63/610,160
Examiner
CHOU, SHIH TSUN A
Art Unit
Tech Center
Assignee
Taiwan Semiconductor Manufacturing Company, Ltd.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
94%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allowance Rate
374 granted / 483 resolved
+17.4% vs TC avg
Strong +16% interview lift
Without
With
+16.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
24 currently pending
Career history
506
Total Applications
across all art units

Statute-Specific Performance

§103
51.4%
+11.4% vs TC avg
§102
21.4%
-18.6% vs TC avg
§112
26.8%
-13.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 483 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of invention II, corresponding to claims 9-28, in the reply filed on 7/9/2026 is acknowledged. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 9-11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Fox (US 2019/0148072) in view of Govindarajan (US 2008/0096363). Regarding claim 9, Fox discloses, in FIG. 1 and in related text, a method, comprising: depositing a first conductive layer (22) over a substrate (20); patterning the first conductive layer to form first and second portions of the first conductive layer (see Fox, FIGS. 1-2, [0012]-[0016]); forming a dielectric stack (30) on the first and second portions of the first conductive layer; depositing a second conductive layer (32) on the dielectric stack; and patterning the second conductive layer to form first and second portions of the second conductive layer (see Fox, FIGS. 3-4, [0017]-[0020]). Fox does not explicitly disclose: forming a dielectric stack, comprising: depositing a first dielectric layer; performing a treatment process; depositing a high-k dielectric layer on the first dielectric layer; and depositing a second dielectric layer on the high-k dielectric layer. Govindarajan teaches: forming a dielectric stack, comprising: depositing a first dielectric layer (TiO2); performing a treatment process (rapid thermal process); depositing a high-k dielectric layer (Al2O3) on the first dielectric layer; and depositing a second dielectric layer (TiO2) on the high-k dielectric layer (see Govindarajan, FIG. 2, [0043]-[0044]). Fox and Govindarajan are analogous art because they both are directed to capacitors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fox with the features of Govindarajan because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Fox to include forming a dielectric stack, comprising: depositing a first dielectric layer; performing a treatment process; depositing a high-k dielectric layer on the first dielectric layer; and depositing a second dielectric layer on the high-k dielectric layer, as taught by Govindarajan, to increase band offset (see Govindarajan, [0042]). Regarding claim 10, Fox in view of Govindarajan teaches the method of claim 9. Govindarajan teaches wherein the treatment process (rapid thermal process) is performed after the depositing of the first dielectric layer (see Govindarajan, [0044]). Govindarajan does not explicitly teach wherein the treatment process is performed before the depositing of the first dielectric layer. However, the limitation would have been found obvious since selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946). See also, MPEP § 2144.04. Regarding claim 11, Fox in view of Govindarajan teaches the method of claim 9. Govindarajan teaches wherein the treatment process (rapid thermal process) is performed after the depositing of the first dielectric layer (see Govindarajan, [0044]). Govindarajan does not explicitly teach wherein the treatment process is performed before the depositing of the first dielectric layer. However, the limitation would have been found obvious since selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results. In re Burhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946). See also, MPEP § 2144.04. Regarding claim 14, Fox in view of Govindarajan teaches the method of claim 9. Govindarajan teaches wherein the high-k dielectric layer is deposited by atomic layer deposition (see Govindarajan, [0058], claim 1). Claims 9-14 are rejected under 35 U.S.C. 103 as being unpatentable over Fox (US 2019/0148072) in view of Basceri (US 2004/0235242). Regarding claim 9, Fox discloses, in FIG. 1 and in related text, a method, comprising: depositing a first conductive layer (22) over a substrate (20); patterning the first conductive layer to form first and second portions of the first conductive layer (see Fox, FIGS. 1-2, [0012]-[0016]); forming a dielectric stack (30) on the first and second portions of the first conductive layer; depositing a second conductive layer (32) on the dielectric stack; and patterning the second conductive layer to form first and second portions of the second conductive layer (see Fox, FIGS. 3-4, [0017]-[0020]). Fox does not explicitly disclose: forming a dielectric stack, comprising: depositing a first dielectric layer; performing a treatment process; depositing a high-k dielectric layer on the first dielectric layer; and depositing a second dielectric layer on the high-k dielectric layer. Basceri teaches: forming a dielectric stack, comprising: depositing a first dielectric layer (36); performing a treatment process (plasma nitridation); depositing a high-k dielectric layer (34) on the first dielectric layer; and depositing a second dielectric layer (38) on the high-k dielectric layer (see Basceri, FIG. 1, [0037], [0040]-[0042]). Fox and Basceri are analogous art because they both are directed to capacitors and one of ordinary skill in the art would have had a reasonable expectation of success to modify Fox with the features of Basceri because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Fox to include forming a dielectric stack, comprising: depositing a first dielectric layer; performing a treatment process; depositing a high-k dielectric layer on the first dielectric layer; and depositing a second dielectric layer on the high-k dielectric layer, as taught by Basceri, to improve permittivity of the stack and avoid oxidation of the capacitor electrodes, and to decrease leakage and increase cell capacitance (see Basceri, [0037], [0042]). Regarding claim 10, Fox in view of Basceri teaches the method of claim 9. Basceri teaches wherein the treatment process is performed before the depositing of the first dielectric layer (see Basceri, [0037], [0040]), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 9. Regarding claim 11, Fox in view of Basceri teaches the method of claim 9. Basceri teaches wherein the treatment process is performed before the depositing of the first dielectric layer (see Basceri, [0037], [0040]), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 9. Regarding claim 12, Fox in view of Basceri teaches the method of claim 11. Basceri teaches wherein the treatment process is a plasma nitridation process (see Basceri, [0038]), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 9. Regarding claim 13, Fox in view of Basceri teaches the method of claim 11. Basceri teaches wherein the treatment process is an N2 plasma treatment process, an NH3 plasma treatment, or a combination thereof (see Basceri, [0038]), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 9. Regarding claim 14, Fox in view of Basceri teaches the method of claim 11. Basceri teaches wherein the high-k dielectric layer (34) is deposited by atomic layer deposition (see Basceri, [0041]), with the same analogous prior art and field of endeavor statement and the same motivation as provided for in claim 9. Allowable Subject Matter Claims 15-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 17-28 are allowed. The following is a statement of reasons for the indication of allowable subject matter: The prior art of records, individually or in combination, do not disclose nor teach “wherein oxygen-vacancies are formed at a bottom of the high-k dielectric layer” in combination with other limitations as recited in claim 15. The prior art of record, Basceri, discloses a method, comprising: depositing a first conductive layer over a substrate; forming a dielectric stack on the first conductive layer, comprising: depositing a first dielectric layer; performing a nitridation process, form a nitride layer; depositing a high-k dielectric layer on the nitride layer; and depositing a second dielectric layer on the high-k dielectric layer; and depositing a second conductive layer on the dielectric stack. The prior art of records, individually or in combination, do not disclose nor teach “performing a nitridation process on the first dielectric layer to form a nitride layer; wherein the high-k dielectric layer has a first oxygen concentration located at a top of the high-k dielectric layer substantially greater than a second oxygen concentration located at a bottom of the high-k dielectric layer” in combination with other limitations as recited in claim 17. The prior art of record, Basceri, discloses a method, comprising: depositing a first conductive layer over a substrate; forming a dielectric stack on the first conductive layer, comprising: depositing a first dielectric layer; forming a nitride layer; depositing a second dielectric layer on the nitride layer; and depositing a third dielectric layer on the second dielectric layer; and depositing a second conductive layer on the dielectric stack. The prior art of records, individually or in combination, do not disclose nor teach “wherein the second dielectric layer has a first oxygen concentration located at a top of the second dielectric layer substantially greater than a second oxygen concentration located at a bottom of the second dielectric layer” in combination with other limitations as recited in claim 21. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHIH TSUN A CHOU whose telephone number is (408)918-7583. The examiner can normally be reached M-F 8:00-16:00 Arizona Time. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at (571) 272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SHIH TSUN A CHOU/Primary Examiner, Art Unit 2811
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Prosecution Timeline

Apr 05, 2024
Application Filed
Sep 15, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
94%
With Interview (+16.4%)
2y 5m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 483 resolved cases by this examiner. Grant probability derived from career allowance rate.

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