Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to a restriction requirement mailed on 05/06/2026, the Applicant elected Group II encompassing method claims 15-20, canceled claims 1-14 directed to withdrawn Group I and added new method claims 21-34 directed to the elected Group II.
Currently, claims 15-34 are pending and examined below.
Information Disclosure Statement (IDS)
The information disclosure statement submitted on 04/05/2024 ("04-05-24 IDS") is in compliance with the provisions of 37 CFR 1.97. Accordingly, the 04-05-24 IDS is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: [[SEMICONDUCTOR PACKAGE AND]] METHOD INCLUDING OPTICALLY CONNECTING OPTICAL BRIDGE DIE TO ASIC DIES
A. Prior-art rejections based at least in part by the primary-reference Cho
Claim Rejections - 35 USC § 1021
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 15 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pub. No. US 2025/0096142 A1 to Cho ("Cho").
Figs. 6 and 7 of Cho are provided to support the rejections below:
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Regarding independent claim 15, Cho teaches a method, comprising:
arranging first and second application-specific integrated circuit (ASIC) dies 62, 64 (para [0030] - “The electronic chip 62 may be a non-photonics chip that includes electronic components, such as transistors, that form a functional electronic integrated circuit, such as an application-specific integrated circuit. In an embodiment, the memory chip 64 may be a non-photonics chip in the form of a High Bandwidth Memory (HBM) stack.”) next to each other on a carrier substrate 40 (para [0040] - “package substrate 40”);
forming a redistribution structure 51 (para [0024] - “a back-end-of-line stack 51 adjacent to a portion of the electro-optic bridge chip 38.”; para [0027] - “In an embodiment, each back-end-of-line stack 51 may include an opening in which the optical coupler 50 is positioned. The opening in each back-end-of-line stack 51 may be filled by a homogeneous dielectric material, such as silicon dioxide, that replaces a removed portion of the back-end-of-line stack 51.”) on the first ASIC die 62 and the second ASIC die 64, a first side of the redistribution structure 51 overlapping the first ASIC die 62 and the second ASIC die 64; and
connecting an optical bridge die 38 (see Fig. 5) on a second side of the redistribution structure 51, wherein the optical bridge die 38 at least partially overlap the first ASIC die 62 and the second ASIC die 64, wherein the first ASIC die 62 and the second ASIC die 64 are configured to optically communicate via the optical bridge die 38 (para [0030] - “With reference to FIG. 7 and in accordance with alternative embodiments, electro-optic bridge chips 38 may be deployed to couple multiple chips of different types for optical and electrical communication.”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
(1). Determining the scope and contents of the prior art.
(2). Ascertaining the differences between the prior art and the claims at issue.
(3). Resolving the level of ordinary skill in the pertinent art.
(4). Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Cho and further in view of Pub. No. US 2023/0194778 A1 to Kim et al. (“Kim”).
Regarding claim 16, Cho does not disclose disposing an encapsulant on the carrier substrate, wherein the encapsulant is disposed around and between the first ASIC die and the second ASIC die.
Kim teaches disposing an encapsulant 162 (para [0044] - “A mold compound 162, such as an epoxy, may fully encapsulate or partially encapsulate the PIC 152, EIC 154 and the OCC 156.”) to hold the dies in place to be protect the dies against external forces and contamination (para [0029] - “By fully embedding the EIC, PIC, and OCC within a mold, a high-performance optical module can be integrated, and may result in a compact form factor with high optical/electrical bandwidth and bandwidth density with increased I/O counts. In embodiments, radiofrequency (RF) performance may be improved by optimizing RF signal transmission lines within a redistribution layer (RDL) to be precisely fabricated for impedance matching, and removing the need for bond wires. In embodiments, due to the embedding within a mold compound, these optical modules may be rigidly held in place and thus resistant to external forces. In addition, contamination due to damage caused by die-to-die or die-to-board packaging processes and handling may be minimized, improving total cycle time and yield, and reducing cost by performing packaging processes at the wafer level, for example using glass or a silicon wafer as a carrier, or at the panel level, for example using a glass panel as a temporary carrier.”).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the method of Cho by disposing an encapsulant of Kim around and between the first ASIC die and the second ASIC die, so as to help protect the dies from the external forces and contamination.
B. Prior-art rejections based at least in part by the primary-reference Lin
Claim Rejections - 35 USC § 102
Claim 15 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Pub. No. US 2024/0264369 A1 to Lin et al. ("Lin").
Fig. 4 of Lin has been annotated to support the rejections below:
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[AltContent: arrow][AltContent: textbox (64)][AltContent: textbox (64)][AltContent: arrow][AltContent: arrow][AltContent: rect][AltContent: textbox (62)][AltContent: textbox (62’)]
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Regarding independent claim 15, Lin teaches a method, comprising:
arranging first and second application-specific integrated circuit (ASIC) dies 62, 62’ (para [0026] - “processing die 62”; para [0044] - “processing die 62’ “) next to each other on a carrier substrate 7 (para [0025] - “carrier 7”);
forming a redistribution structure 9 (para [0098] - “bridging component 9 may include circuit structures 93 and 94 respectively disposed on the surfaces 91 and 92.”) on the first ASIC die 62 and the second ASIC die 62’, a first side of the redistribution structure 9 overlapping the first ASIC die 62 and the second ASIC die 62’; and
connecting an optical bridge die 3 or OBD (para [0024] - “an optical connection element 3”; para [0101] - “As describe above, the photonic component 2 and the electronic component 8 are jointly called “optical engine”, or are integrated as an optical engine (e.g., a first optical engine). The photonic component 2′ and the electronic component 8′ are jointly called “optical engine”, or are integrated as an optical engine (e.g., a second optical engine). The first optical engine is disposed on or over the processing unit 6.”) on a second side of the redistribution structure 9, wherein the optical bridge die 3 or OBD is at least partially overlap the first ASIC die 62 and the second ASIC die 62’, wherein the first ASIC die 62 and the second ASIC die 62’ are configured to optically communicate via the optical bridge die 3 or OBD.
Claim Rejections - 35 USC § 103
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Lin and further in view of Kim.
Regarding claim 16, Lin does not disclose disposing an encapsulant on the carrier substrate, wherein the encapsulant is disposed around and between the first ASIC die and the second ASIC die.
Kim teaches disposing an encapsulant 162 (para [0044] - “A mold compound 162, such as an epoxy, may fully encapsulate or partially encapsulate the PIC 152, EIC 154 and the OCC 156.”) to hold the dies in place to be protect the dies against external forces and contamination (para [0029] - “By fully embedding the EIC, PIC, and OCC within a mold, a high-performance optical module can be integrated, and may result in a compact form factor with high optical/electrical bandwidth and bandwidth density with increased I/O counts. In embodiments, radiofrequency (RF) performance may be improved by optimizing RF signal transmission lines within a redistribution layer (RDL) to be precisely fabricated for impedance matching, and removing the need for bond wires. In embodiments, due to the embedding within a mold compound, these optical modules may be rigidly held in place and thus resistant to external forces. In addition, contamination due to damage caused by die-to-die or die-to-board packaging processes and handling may be minimized, improving total cycle time and yield, and reducing cost by performing packaging processes at the wafer level, for example using glass or a silicon wafer as a carrier, or at the panel level, for example using a glass panel as a temporary carrier.”).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the method of Lin by disposing an encapsulant of Kim around and between the first ASIC die and the second ASIC die, so as to help protect the dies from the external forces and contamination.
Claims 21, 23, 26, 28 and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Lin in view of Kim.
Regarding independent claim 21, Lin teaches a method, comprising:
encapsulating a first semiconductor die 62 and a second semiconductor die 62’ (para [0026] - “processing die 62”; para [0044] - “processing die 62’ “) in a first insulating material 64, 64 (para [0026] - “The dielectric structure 64 surrounds or encapsulates the processing die 62.”) wherein the first semiconductor die 62 is laterally offset from the second semiconductor die 62’;
forming a redistribution structure 9 (para [0098] - “bridging component 9 may include circuit structures 93 and 94 respectively disposed on the surfaces 91 and 92.”) over the first insulating material 64, 64, the first semiconductor die 62 and the second semiconductor die 62’;
bonding an optical die 3 or OBD (para [0024] - “an optical connection element 3”; para [0101] - “As describe above, the photonic component 2 and the electronic component 8 are jointly called “optical engine”, or are integrated as an optical engine (e.g., a first optical engine). The photonic component 2′ and the electronic component 8′ are jointly called “optical engine”, or are integrated as an optical engine (e.g., a second optical engine). The first optical engine is disposed on or over the processing unit 6.”) to the redistribution structure 9, wherein the optical die 3 or OBD communicatively connects the first semiconductor die 62 to the second semiconductor die 62’ through optical elements in the optical die 3 or OBD.
Lin does not disclose encapsulating the optical die 3 or OBD in a second insulating material.
Kim teaches disposing an encapsulant 162 (para [0044] - “A mold compound 162, such as an epoxy, may fully encapsulate or partially encapsulate the PIC 152, EIC 154 and the OCC 156.”) to hold the dies in place to be protect the dies against external forces and contamination (para [0029] - “By fully embedding the EIC, PIC, and OCC within a mold, a high-performance optical module can be integrated, and may result in a compact form factor with high optical/electrical bandwidth and bandwidth density with increased I/O counts. In embodiments, radiofrequency (RF) performance may be improved by optimizing RF signal transmission lines within a redistribution layer (RDL) to be precisely fabricated for impedance matching, and removing the need for bond wires. In embodiments, due to the embedding within a mold compound, these optical modules may be rigidly held in place and thus resistant to external forces. In addition, contamination due to damage caused by die-to-die or die-to-board packaging processes and handling may be minimized, improving total cycle time and yield, and reducing cost by performing packaging processes at the wafer level, for example using glass or a silicon wafer as a carrier, or at the panel level, for example using a glass panel as a temporary carrier.”).
Regarding claim 23, Lin of the combination above further teaches the first semiconductor die 62 and the second semiconductor die 62’ that are logic (processing) dies.
Regarding claim 26, the combination above further teaches bonding a third semiconductor die 8 (Lin) to the redistribution structure 9 (Lin), wherein encapsulating the optical die 3 (Lin) in the second insulating material 162 (Kim) that comprises encapsulating the third semiconductor die 8 (Lin) in the second insulating material 612 (Kim).
Regarding claim 28, Lin of the combination above further teaches the optical die 3 or OBD that overlaps the first semiconductor die 62, the second semiconductor die 62’, and the first insulating material 64, 64.
Regarding independent claim 29, Lin teaches a method, comprising:
attaching a first integrated circuit die 62 and a second integrated circuit die 62’ (para [0026] - “processing die 62”; para [0044] - “processing die 62’ “) to a first substrate 7 (para [0025] - “carrier 7”);
forming a first insulating material 64, 64 (para [0026] - “The dielectric structure 64 surrounds or encapsulates the processing die 62.”) between the first integrated circuit die 62 and the second integrated circuit die 62’;
forming a redistribution structure 9 (para [0098] - “bridging component 9 may include circuit structures 93 and 94 respectively disposed on the surfaces 91 and 92.”) over the first insulating material 64, 64, the first integrated circuit die 62 and the second integrated circuit die 62’;
bonding an optical die 3 (para [0024] - “an optical connection element 3”), a third integrated circuit die 8, and a fourth integrated circuit die 8’ (para [0039] - “In some embodiments, the electronic components 8 and 8′ may independently include an integrated digital signal processor (DSP), a transimpedance amplifier (TIA), a driver (DRV), or a combination thereof.”) to the redistribution structure 9, wherein the third integrated circuit die 8 overlaps with the first integrated circuit die 62, wherein the fourth integrated circuit die 8’ overlaps the second integrated circuit die 62’, and wherein the optical die 3 overlaps the first integrated circuit die 62 and the second integrated circuit die 62’; and
Lin does not disclose encapsulating the optical die 3, the third integrated circuit die 8 and the fourth integrated circuit die 8’ in a second insulating material.
Kim teaches disposing an encapsulant 162 (para [0044] - “A mold compound 162, such as an epoxy, may fully encapsulate or partially encapsulate the PIC 152, EIC 154 and the OCC 156.”) to hold the dies in place to be protect the dies against external forces and contamination (para [0029] - “By fully embedding the EIC, PIC, and OCC within a mold, a high-performance optical module can be integrated, and may result in a compact form factor with high optical/electrical bandwidth and bandwidth density with increased I/O counts. In embodiments, radiofrequency (RF) performance may be improved by optimizing RF signal transmission lines within a redistribution layer (RDL) to be precisely fabricated for impedance matching, and removing the need for bond wires. In embodiments, due to the embedding within a mold compound, these optical modules may be rigidly held in place and thus resistant to external forces. In addition, contamination due to damage caused by die-to-die or die-to-board packaging processes and handling may be minimized, improving total cycle time and yield, and reducing cost by performing packaging processes at the wafer level, for example using glass or a silicon wafer as a carrier, or at the panel level, for example using a glass panel as a temporary carrier.”).
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Claim 17 is objected to for depending on a rejected base claim 15 and the intervening claim 16, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 15 and the intervening claim 16 or the base claim 15 is amended to include all of the limitations of claim 17 and the intervening claim 16.
Claim 18 is objected to for depending on a rejected base claim 15 and the intervening claim 16, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 15 and the intervening claim 16 or the base claim 15 is amended to include all of the limitations of claim 18 and the intervening claim 16.
Claim 19 is objected to for depending on a rejected base claim 15 and the intervening claim 16, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 15 and the intervening claim 16 or the base claim 15 is amended to include all of the limitations of claim 19 and the intervening claim 16.
Claim 20 is allowable for depending on the allowable claim 19.
Claim 22 is objected to for depending on a rejected base claim 21, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 21 or the base claim 21 is amended to include all of the limitations of claim 22.
Claim 24 is objected to for depending on a rejected base claim 21, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 21 or the base claim 21 is amended to include all of the limitations of claim 24.
Claim 25 is objected to for depending on a rejected base claim 21, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 21 or the base claim 21 is amended to include all of the limitations of claim 25.
Claim 27 is objected to for depending on a rejected base claim 21, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 21 or the base claim 21 is amended to include all of the limitations of claim 27.
Claim 30 is objected to for depending on a rejected base claim 29, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 29 or the base claim 29 is amended to include all of the limitations of claim 30.
Claims 31-33 are allowable for depending from the allowable claim 30.
Claim 34 is objected to for depending on a rejected base claim 29, but would be allowable if it is rewritten in independent form to include all of the limitations of the base claim 29 or the base claim 29 is amended to include all of the limitations of claim 34.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Pub. No. US 2024/0120305 A1 to Ecton et al.
Pub. No. US 2024/0004129 A1 to Suthram et al.
Pub. No. US 2023/0314701 A1 to Libsch et al.
Pub. No. US 2023/0296854 A1 to Winterbottom et al.
Pub. No. US 2025/0004216 A1 to Hwang
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL JUNG whose telephone number is (408) 918-7554. The examiner can normally be reached on 8:30 A.M. to 7 P.M.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MICHAEL JUNG/Primary Examiner, Art Unit 2817 16 July 2026
1 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status
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