CTNF 18/628,513 CTNF 89943 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-5 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Chang et al. (US 2020/0251476 A1 hereinafter referred to as “Chang”) . With respect to claim 1 , Chang discloses, in Figs.1-6, a memory device, comprising: a first memory array (20A) disposed over a substrate (110); a second memory array (20B) disposed over the substrate (110) and separated from the first memory array (20A) along a first direction/(X-direction) (see Par.[0018]-[0021] wherein well strap cell 50 is disposed between a SRAM cell 20A of memory cells 20 and a SRAM cell 20B of memory cells 20; well strap cell 50 includes a substrate (wafer) 110. In the depicted embodiment, substrate 110 is a bulk substrate that includes silicon); and a strap cell (50) defined in the substrate (110) and interposed between the first memory array (20A) and the second memory array (20b) (see Par.[0022] wherein a well strap column 40 includes well strap cells 50 arranged along the first direction; well strap column 40 is disposed between memory array 12A and memory array 12B, such that each row of memory cells 20 in memory array 12A is disposed between a respective edge dummy cell 30 and a respective well strap cell 50 and each row of memory cells 20 in memory array 12B is disposed between a respective well strap cell 50 and a respective edge dummy cell 30), the strap cell including: a first boundary/(interface between 20A, 50B) abutting the first memory array (20A), a second boundary/(interface between 20B and 50C) abutting the second memory array (20B), the first boundary and the second boundary (20C) extending along a second direction/(Y-direction) perpendicular to the first direction/(X-direction), a p-type well strap (50A) interposed between the first boundary and the second boundary along the first direction/(X-direction), and an n-type well strap (50C) spaced from the p-type well strap (50A) along the second direction/(Y-direction), wherein: the p-type well strap (50A) is coupled to a first power supply voltage (VSS), and the n-type well strap (50C) is coupled to a second power supply voltage (VDD) (see Par.[0019] wherein P-type well strap 50A is configured to electrically connect p-type wells of memory cells 20 to a first power supply voltage, such as a power supply voltage V.sub.SS. N-type well strap 50B and n-type well strap 50C are each configured to electrically connect n-type wells of memory cells 20 to a second power supply voltage, such as a power supply voltage VDD; in some implementations, power supply voltage V.sub.DD is a positive power supply voltage, and power supply voltage V.sub.SS is an electrical ground). With respect to claim 2 , Chang discloses, in Figs.1-6, the memory device, wherein the first power supply voltage is electrical ground, and wherein the second power supply voltage is a positive power supply voltage (see Par.[0019] wherein P-type well strap 50A is configured to electrically connect p-type wells of memory cells 20 to a first power supply voltage, such as a power supply voltage V.sub.SS. N-type well strap 50B and n-type well strap 50C are each configured to electrically connect n-type wells of memory cells 20 to a second power supply voltage, such as a power supply voltage VDD; in some implementations, power supply voltage V.sub.DD is a positive power supply voltage, and power supply voltage V.sub.SS is an electrical ground). With respect to claim 3 , Chang discloses, in Figs.1-6, the memory device, wherein the strap cell further includes: a n-type transistor disposed adjacent to the p-type well strap along the first direction, the n-type transistor including a first gate terminal, and a p-type transistor disposed adjacent to the n-type well strap along the first direction, the p-type transistor including a second gate terminal, the first gate terminal and the second gate terminal each coupled to the first power supply voltage and the second power supply voltage, respectively (see Par.[0013] wherein a fin-based n-type well strap electrically connects an n-well region corresponding with a p-type FinFET to a voltage node, such as a voltage node associated with the p-type transistor, and a fin-based p-type well strap electrically connects a p-well region corresponding with an n-type FinFET to a voltage node, such as a voltage node associated with the n-type transistor; see Par.[0020] wherein substrate 110 includes doped regions, such as an n-type doped region 112A, an n-type doped region 112B, an n-type doped region 112C, an n-type doped region 112D, a p-type doped region 114A, a p-type doped region 114B, and a p-type doped region 114C (referred to hereafter as n-wells 112A-112D and p-wells 114A-114C); N-type doped regions, such as n-wells 112A-112D, are doped with n-type dopants, such as phosphorus, arsenic, other n-type dopant, or combinations thereof; P-type doped regions, such as p-wells 114A-114C, are doped with p-type dopants, such as boron, indium, other p-type dopant, or combinations thereof; see Par.[0017] wherein dummy cells can include p-type wells, n-type wells, fin structures (including one or more fins), gate structures, source/drain features, and/or contact features; Well strap cells generally refer to dummy cells that are configured to electrically connect a voltage to an n-type well of memory cells 20, a p-type well of memory cells 20, or both). With respect to claim 4 , Chang discloses, in Figs.1-6, the memory device, further comprising: a p-type doped region (114) defined in the substrate and extending across the first memory array, the strap cell, and the second memory array along the first direction, the p-type well strap disposed in the p-type doped region; and an n-type doped region (112) defined in the substrate and extending across the first memory array, the strap cell, and the second memory array along the first direction, the n-type well strap disposed the n-type doped region (see Par.[0013] wherein a fin-based n-type well strap electrically connects an n-well region corresponding with a p-type FinFET to a voltage node, such as a voltage node associated with the p-type transistor, and a fin-based p-type well strap electrically connects a p-well region corresponding with an n-type FinFET to a voltage node, such as a voltage node associated with the n-type transistor; see Par.[0020]-[0025] wherein substrate 110 includes doped regions, such as an n-type doped region 112A, an n-type doped region 112B, an n-type doped region 112C, an n-type doped region 112D, a p-type doped region 114A, a p-type doped region 114B, and a p-type doped region 114C (referred to hereafter as n-wells 112A-112D and p-wells 114A-114C); N-type doped regions, such as n-wells 112A-112D, are doped with n-type dopants, such as phosphorus, arsenic, other n-type dopant, or combinations thereof; P-type doped regions, such as p-wells 114A-114C, are doped with p-type dopants, such as boron, indium, other p-type dopant, or combinations thereof; see Par.[0017] wherein dummy cells can include p-type wells, n-type wells, fin structures (including one or more fins), gate structures, source/drain features, and/or contact features; Well strap cells generally refer to dummy cells that are configured to electrically connect a voltage to an n-type well of memory cells 20, a p-type well of memory cells 20, or both). With respect to claim 5 , Chang discloses, in Figs.1-6, the memory device, wherein the strap cell further includes: a first via coupling the p-type well strap to the first power supply voltage, and a second via coupling the n-type well strap to the second power supply voltage (see Par.[0036] wherein The conductive layers are configured to form vertical interconnect features, such as device-level contacts and/or vias, and/or horizontal interconnect features, such as conductive lines) . 07-15 AIA Claim s 1-14 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Ryu et al. (US 2019/0074296 A1 hereinafter referred to as “Ryu”) . With respect to claim 1 , Ryu discloses, in Figs.1-19, a memory device, comprising: a first memory array (215a) disposed over a substrate; a second memory array (215b) disposed over the substrate and separated from the first memory array (215a) along a first direction/(x-direction); and a strap cell (214) defined in the substrate and interposed between the first memory array (215a) and the second memory array (215b) (see Par.[0032] wherein a plurality of cells may be arranged in a first area 150 between the first and second macroblocks 110 and 120, and the plurality of cells may include standard cells and ending cells and the ending cells may include ties or taps (e.g., well ties or well taps, or substrate ties or substrate taps), and thus may mitigate or prevent a latch-up that may occur when a forward bias is applied to a diode at a substrate/well junction; see, for example, in Fig.10, Par.[0092] wherein the plurality of cells 210 may include first to third ending cells 211 to 213 arranged in edge regions of the first area 150b, center cells 214 arranged in a central region of the first area 150b, standard cells 215a arranged between the first ending cells 211 and the center cells 214, and standard cells 215b arranged between the second ending cells 212 and the center cells 214), the strap cell including: a first boundary abutting the first memory array (215a), a second boundary abutting the second memory array (215b), the first boundary and the second boundary extending along a second direction/(y-direction) perpendicular to the first direction/(x-direction), a p-type well strap (AR2) interposed between the first boundary and the second boundary along the first direction/(x-direction), and an n-type well strap (AR1) spaced from the p-type well strap (AR2) along the second direction/(y-direction), wherein: the p-type well strap (AR2) is coupled to a first power supply voltage (VSS), and the n-type well strap (AR1) is coupled to a second power supply voltage (VDD) (see Fig.4, Par.[0045]-[0050] wherein the first definition layer DL1 may be a PMOS definition layer and the second definition layer DL2 may be an NMOS definition layer. For example, the first definition layer DL1 may correspond to an N-type well region and the second definition layer DL2 may correspond to a P-type substrate region; the first to fourth active regions AR1 to AR4 may extend in the first direction; the first active region AR1 and the second active region AR2 may be spaced apart from each other in a second direction (e.g., the Y direction) substantially perpendicular to the first direction, and may be of different conductivity types; the first and second taps T1 and T2 may be arranged on the first and second active regions AR1 and AR2, respectively; the first and second taps T1 and T2 may include any material having electrical conductivity; the first tap T1 may receive the power supply voltage VDD applied to the first power rail PWR1 and thus may provide the power supply voltage VDD to the first active region AR1; the second tap T2 may receive the ground voltage VSS applied to the second power rail PWR2 and thus may provide the ground voltage VSS to the second active region AR2; the first and second taps T1 and T2 may be referred to as first and second ties. For example, the first tap T1 may be referred to as a well tap or a well tie, and the second tap T2 may be referred to as a substrate tap or a substrate tie). With respect to claim 2 , Ryu discloses, in Figs.1-19, the memory device, wherein the first power supply voltage (VSS) is electrical ground, and wherein the second power supply voltage (VDD) is a positive power supply voltage (see Fig.4, Par.[0045]-[0050] wherein the first definition layer DL1 may be a PMOS definition layer and the second definition layer DL2 may be an NMOS definition layer. For example, the first definition layer DL1 may correspond to an N-type well region and the second definition layer DL2 may correspond to a P-type substrate region; the first to fourth active regions AR1 to AR4 may extend in the first direction; the first active region AR1 and the second active region AR2 may be spaced apart from each other in a second direction (e.g., the Y direction) substantially perpendicular to the first direction, and may be of different conductivity types; the first and second taps T1 and T2 may be arranged on the first and second active regions AR1 and AR2, respectively; the first and second taps T1 and T2 may include any material having electrical conductivity; the first tap T1 may receive the power supply voltage VDD applied to the first power rail PWR1 and thus may provide the power supply voltage VDD to the first active region AR1; the second tap T2 may receive the ground voltage VSS applied to the second power rail PWR2 and thus may provide the ground voltage VSS to the second active region AR2; the first and second taps T1 and T2 may be referred to as first and second ties. For example, the first tap T1 may be referred to as a well tap or a well tie, and the second tap T2 may be referred to as a substrate tap or a substrate tie). With respect to claim 3 , Ryu discloses, in Figs.1-19, the memory device, wherein the strap cell further includes: a n-type transistor disposed adjacent to the p-type well strap along the first direction, the n-type transistor including a first gate terminal, and a p-type transistor disposed adjacent to the n-type well strap along the first direction, the p-type transistor including a second gate terminal, the first gate terminal and the second gate terminal each coupled to the first power supply voltage and the second power supply voltage, respectively (see Fig.4, Par.[0045]-[0050] wherein the first definition layer DL1 may be a PMOS definition layer and the second definition layer DL2 may be an NMOS definition layer. For example, the first definition layer DL1 may correspond to an N-type well region and the second definition layer DL2 may correspond to a P-type substrate region; the first to fourth active regions AR1 to AR4 may extend in the first direction; the first active region AR1 and the second active region AR2 may be spaced apart from each other in a second direction (e.g., the Y direction) substantially perpendicular to the first direction, and may be of different conductivity types; the first and second taps T1 and T2 may be arranged on the first and second active regions AR1 and AR2, respectively; the first and second taps T1 and T2 may include any material having electrical conductivity; the first tap T1 may receive the power supply voltage VDD applied to the first power rail PWR1 and thus may provide the power supply voltage VDD to the first active region AR1; the second tap T2 may receive the ground voltage VSS applied to the second power rail PWR2 and thus may provide the ground voltage VSS to the second active region AR2; the first and second taps T1 and T2 may be referred to as first and second ties. For example, the first tap T1 may be referred to as a well tap or a well tie, and the second tap T2 may be referred to as a substrate tap or a substrate tie). With respect to claim 4 , Ryu discloses, in Figs.1-19, the memory device, further comprising: a p-type doped region defined in the substrate and extending across the first memory array, the strap cell, and the second memory array along the first direction, the p-type well strap disposed in the p-type doped region; and an n-type doped region defined in the substrate and extending across the first memory array, the strap cell, and the second memory array along the first direction, the n-type well strap disposed the n-type doped region (see Fig.4, Par.[0045]-[0050] wherein the first definition layer DL1 may be a PMOS definition layer and the second definition layer DL2 may be an NMOS definition layer. For example, the first definition layer DL1 may correspond to an N-type well region and the second definition layer DL2 may correspond to a P-type substrate region; the first to fourth active regions AR1 to AR4 may extend in the first direction; the first active region AR1 and the second active region AR2 may be spaced apart from each other in a second direction (e.g., the Y direction) substantially perpendicular to the first direction, and may be of different conductivity types; the first and second taps T1 and T2 may be arranged on the first and second active regions AR1 and AR2, respectively; the first and second taps T1 and T2 may include any material having electrical conductivity; the first tap T1 may receive the power supply voltage VDD applied to the first power rail PWR1 and thus may provide the power supply voltage VDD to the first active region AR1; the second tap T2 may receive the ground voltage VSS applied to the second power rail PWR2 and thus may provide the ground voltage VSS to the second active region AR2; the first and second taps T1 and T2 may be referred to as first and second ties. For example, the first tap T1 may be referred to as a well tap or a well tie, and the second tap T2 may be referred to as a substrate tap or a substrate tie). With respect to claim 5 , Ryu discloses, in Figs.1-19, the memory device, wherein the strap cell further includes: a first via (V0a, V0b) coupling the p-type well strap (AR2) to the first power supply voltage (VSS), and a second via (V0a, V0b) coupling the n-type well strap (AR1) to the second power supply voltage (VDD) (see Par.[0050] wherein the vias V0a may be arranged on the contacts CAL respectively and the vias V0b may be arranged on the vias V0a, respectively; the first and second power rails PWR1 and PWR2 extending in the first direction may be arranged on the vias V0b; the contacts CAL the vias V0a and V0b, and the first and second power rails PWR1 and PWR2 may each include any material having electrical conductivity, for example, tungsten; the first section SEC1 will be described in more detail with reference to FIG. 4). With respect to claim 6 , Ryu discloses, in Figs.1-19, the memory device, further comprising: a first peripheral circuit configured to control the first memory array; and a second peripheral circuit configured to control the second memory array, the first peripheral circuit and the second peripheral circuit disposed on opposite sides of the strap cell (see Par.[0128] wherein referring to FIG. 17, the application processor 500 may include a central processing unit (CPU) 510, a graphics processing unit (GPU) 520, a digital signal processor (DSP) 530, a multimedia unit 540, and a plurality of input/output (I/O) blocks 550; the application processor 500 may further include a peripheral circuit including various interfaces for interfacing with the outside). With respect to claim 7 , Ryu discloses, in Figs.1-19, a memory device, comprising: a first bank of memory arrays (215a) disposed over a substrate; a second bank of memory arrays (215b) disposed over the substrate and separated from the first bank along a first direction/(x-direction); a first strap cell (214) interposed between the first bank (215a) and the second bank (215b), the first strap cell (214) directly adjoining the first bank (215a) and the second bank (215B) (see Par.[0032] wherein a plurality of cells may be arranged in a first area 150 between the first and second macroblocks 110 and 120, and the plurality of cells may include standard cells and ending cells and the ending cells may include ties or taps (e.g., well ties or well taps, or substrate ties or substrate taps), and thus may mitigate or prevent a latch-up that may occur when a forward bias is applied to a diode at a substrate/well junction; see, for example, in Fig.10, Par.[0092] wherein the plurality of cells 210 may include first to third ending cells 211 to 213 arranged in edge regions of the first area 150b, center cells 214 arranged in a central region of the first area 150b, standard cells 215a arranged between the first ending cells 211 and the center cells 214, and standard cells 215b arranged between the second ending cells 212 and the center cells 214); a second strap cell (211a) adjoining the first bank (215A) opposite the first strap cell (214) along the first direction/(x-direction); and a third strap cell (212a) adjoining the second bank (215b) opposite the second strap cell (211a) along the first direction/(x-direction), wherein: the first strap cell (214) has a first width (W3) along the first direction/(x-direction), the second strap cell (211a) and the third strap cell (212a) each have a second width (W2) along the first direction/(x-direction), and the second width (W2) is different from the first width (W3) (see Fig.13B, Par.[0103]-[0108] wherein Referring to FIG. 13B, the integrated circuit 200c may be an example of the integrated circuit 200a of FIG. 12. A first macroblock 110 may be in contact with or border first ending cells 211a in the first direction. For example, the first space SP1 between the first macroblock 110 and the first ending cells 211a may be removed (e.g., may be zero), as compared to FIG. 12. Further, a second macroblock 120 may be in contact with or border second ending cells 212a in the first direction; see Par.[0112]-[0113] wherein the width of the second macroblock 320 in the first direction may be greater than the width of the third macroblock 330 in the first direction; each of the first ending cells 341 may have a first width W1 in the first direction. In an example embodiment, the first ending cells 341 may be implemented in the same manner as the first ending cell 131′ of FIG. 3A, the first ending cell 131″ of FIG. 3B, the first ending cell 131a′ of FIG. 7A, or the first ending cell 131a″ of FIG. 7B; each of the second ending cells 342 may have a second width W2 in the first direction; the third ending cells 343 may be adjacent to the third macroblock 330 and may be arranged in a line in the second direction; each of the third ending cells 343 may have a second width W2 in the first direction; see Par.[0094] wherein the center cells 214 may be arranged in a line between the first ending cells 211 and the second ending cells 212; each of the center cells 214 may have a third width W3 in the first direction. In an example embodiment, each of the center cells 214 may include taps or ties; the third width W3 may be greater than the second width W2; the inventive concepts are not limited thereto; the third width W3 may be less than the second width W2). With respect to claim 8 , Ryu discloses, in Figs.1-19, the memory device, wherein: the second width (W2) is less than the first width (W3) (see Figs.10, 12, 13A), and the first strap cell includes a p-type well strap (AR2) and an n-type well strap (AR1) spaced from the p-type well strap (AR2) along a second direction/(y-direction) perpendicular to the first direction/(x-direction), wherein: the p-type well strap (AR2) is coupled to a first power supply voltage (VSS), and the n-type well strap (AR1) is coupled to a second power supply voltage (VDD) (see Fig.4). With respect to claim 9 , Ryu discloses, in Figs.1-19, the memory device, wherein the second strap cell and the third strap cell are electrically isolated from each of the first power supply voltage and the second power supply voltage (see Figs.10, 12, 13A). With respect to claim 10 , Ryu discloses, in Figs.1-19, the memory device, wherein: the second width is greater than the first width, the second strap cell includes a first p-type well strap and a first n-type well strap spaced from the first p-type well strap along a second direction perpendicular to the first direction, wherein: the first p-type well strap is coupled to a first power supply voltage, and the first n-type well strap is coupled to a second power supply voltage; and the third strap cell includes a second p-type well strap and a second n-type well strap spaced from the second p-type well strap along the second direction, wherein: the second p-type well strap is coupled to the first power supply voltage, and the second n-type well strap is coupled to the second power supply voltage (see Fig.4; and see Figs.10, 12, 13A). With respect to claim 11 , Ryu discloses, in Figs.1-19, the memory device, wherein the first strap cell is electrically isolated from each of the first power supply voltage and the second power supply voltage (see Fig.4; and see Figs.10, 12, 13A). With respect to claim 12 , Ryu discloses, in Figs.1-19, the memory device, wherein the first bank includes a first number of memory arrays arranged along a second direction perpendicular to the first direction, and wherein the second bank includes a second number of memory arrays arranged along the second direction, the first number and the second number each being greater than or equal to 1 (see Fig.4; and see Figs.10, 12, 13A; see Par.[0128] wherein referring to FIG. 17, the application processor 500 may include a central processing unit (CPU) 510, a graphics processing unit (GPU) 520, a digital signal processor (DSP) 530, a multimedia unit 540, and a plurality of input/output (I/O) blocks 550; the application processor 500 may further include a peripheral circuit including various interfaces for interfacing with the outside). With respect to claim 13 , Ryu discloses, in Figs.1-19, the memory device, further comprising: a first peripheral circuit configured to control the first bank; and a second peripheral circuit configured to control the second bank, the first peripheral circuit and the second peripheral circuit disposed on opposite sides of the first strap cell (see Par.[0128] wherein referring to FIG. 17, the application processor 500 may include a central processing unit (CPU) 510, a graphics processing unit (GPU) 520, a digital signal processor (DSP) 530, a multimedia unit 540, and a plurality of input/output (I/O) blocks 550; the application processor 500 may further include a peripheral circuit including various interfaces for interfacing with the outside). With respect to claim 14 , Ryu discloses, in Figs.1-19, the memory device, further comprising a transition cell aligned with the first strap cell along a second direction perpendicular to the first direction, the transition cell having a fourth width along the first direction, wherein the fourth width is the same as the first width (see Fig.4; and see Figs.10, 12, 13A) . Allowable Subject Matter 12-151-07 AIA 07-97 12-51-07 Claim s 15-20 are allowed. 13-03-01 AIA The following is a statement of reasons for the indication of allowable subject matter: With respect to claim 15, none of the prior art of record teaches, suggest, or renders obvious, either alone or in combination, a semiconductor structure, comprising: an upper edge cell abutting the first memory device opposite the middle edge cell, the upper edge cell having a second height along the second direction; and a lower edge cell abutting the second memory device opposite the middle edge cell, the lower edge cell having a third height along the second direction, wherein the first height is less than a sum of the second height and the third height. Claims 16-20 are also allowed because of their dependency to the allowed base claim 15. Citation of Pertinent Prior Art The prior art made of record (e.g.; see PTO-892) and not relied upon is considered pertinent to applicant's disclosure. Examiner’s Telephone/Fax Contacts Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOULOUCOULAYE INOUSSA whose telephone number is (571)272-0596. The examiner can normally be reached Monday-Friday (10-18). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JEFF W NATALINI can be reached at 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Mouloucoulaye Inoussa/ Primary Examiner, Art Unit 2818 Application/Control Number: 18/628,513 Page 2 Art Unit: 2818 Application/Control Number: 18/628,513 Page 3 Art Unit: 2818 Application/Control Number: 18/628,513 Page 4 Art Unit: 2818 Application/Control Number: 18/628,513 Page 5 Art Unit: 2818 Application/Control Number: 18/628,513 Page 6 Art Unit: 2818 Application/Control Number: 18/628,513 Page 7 Art Unit: 2818 Application/Control Number: 18/628,513 Page 8 Art Unit: 2818 Application/Control Number: 18/628,513 Page 9 Art Unit: 2818 Application/Control Number: 18/628,513 Page 10 Art Unit: 2818 Application/Control Number: 18/628,513 Page 11 Art Unit: 2818 Application/Control Number: 18/628,513 Page 12 Art Unit: 2818 Application/Control Number: 18/628,513 Page 13 Art Unit: 2818
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