DETAILED ACTION
Election/Restrictions
A restriction requirement was mailed on 5/6/26
Applicant’s election without traverse of Group I (device claims 1-13) in the reply filed on 6/14/26 is acknowledged. Applicant has canceled nonelected claims 14-20.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 5/5/25 is in compliance with the provisions of 37 CFR 1.97 and 1.98. Accordingly, the information disclosure statement has been considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102, some of which form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-3 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US 2023/0354586 A1 (“Cui”).
Cui teaches, for example:
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Cui teaches:
1. A semiconductor structure (see e.g. Figs. 1-2), comprising:
a substrate (e.g. “base 100”) having an array area (e.g. “memory array region” 110) and a peripheral area adjacent (e.g. “peripheral circuit region” 120) to the array area,
wherein the peripheral area of the substrate has a recess (e.g. area occupied by buried gate 300);
a gate dielectric layer (e.g. “high-K dielectric layer” 310) located on a surface of the recess; and
a gate structure (e.g. 320/330) located in the recess and comprising:
a first work function layer (e.g. “gate contact layer” 320) located on the gate dielectric layer; and
a second work function layer (e.g. “metal gate layer” 330; and/or “barrier layer” made of e.g. TiN, but not shown, see e.g. para 118) located on the first work function layer and surrounded by the first work function layer,
wherein the first work function layer is located between the second work function layer and the gate dielectric layer (see e.g. Fig. 2), and
a work function of the first work function layer is different from a work function of the second work function layer (they are made from different conductive materials, so they necessarily have different work functions).
2. The semiconductor structure of claim 1, wherein the work function of the second work function layer is higher than the work function of the first work function layer (see e.g. para 118, for barrier made of TiN; see e.g. para 65 for 330 made of e.g. W, Ta, Ti, or alloys thereof; see e.g. para 65, for 320 made of e.g. polysilicon; for several of the disclosed materials, the combinations thereof meet the claimed limitation).
3. The semiconductor structure of claim 1, wherein a material of the first work function layer comprises polysilicon (see e.g. para 65, for 320 made of polysilicon), and a material of the second work function layer comprises titanium nitride (see e.g. para 118).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cui.
Re claims 4 and 7-9, Cui teaches claim 1 but does not explicitly teach:
4. The semiconductor structure of claim 1, further comprising: a first dielectric layer located on a top surface of the substrate; a second dielectric layer located on the first dielectric layer; and an insulating layer located on the second dielectric layer, wherein a top surface of the second work function layer and a top surface of the first work function layer are higher than a bottom surface of the insulating layer.
7. The semiconductor structure of claim 4, wherein the first work function layer has a portion between the second work function layer and the insulating layer.
8. The semiconductor structure of claim 4, wherein the first work function layer has a portion between the second work function layer and the second dielectric layer.
9. The semiconductor structure of claim 4, wherein the first work function layer has a portion between the second work function layer and the first dielectric layer.
However, one of ordinary skill in the art at the time of invention would have found it obvious, given the teachings of Cui, to provide:
4. The semiconductor structure of claim 1, further comprising: a first dielectric layer (see “1st” in the annotated version of Fig. 2, below) located on a top surface of the substrate (the top surface of the “base” / substrate has a complex shape having recesses therein for 300 and for the shallow trench isolations; the shallow trench isolation comprises “1st”, “2nd”, and “INS” layers therein, on the top surface of the base, in the trench for the STI); a second dielectric layer (see “2nd” in the annotated version of Fig. 2, below) located on the first dielectric layer; and an insulating layer (see “INS” in the annotated version of Fig. 2, below) located on the second dielectric layer, wherein a top surface of the second work function layer and a top surface of the first work function layer are higher than a bottom surface of the insulating layer (the bottom of “INS” is far below the bottoms of the parts of 300, as can be seen in Fig. 2).
While Cui does not explicitly label the structures of the shallow trench isolation, one of ordinary skill in the art would recognize them as insulating layers of a shallow trench isolation (see e.g. para 62, wherein it’s clearly disclosed that 121 in the peripheral region is separated from the memory array region 110 by the isolation structure 112, so the “1st”, “2nd”, and “INS” layers are part of the isolation structure 112. The materials of the isolation structure are disclosed to be insulating materials (“silicon oxide, silicon nitride, and silicon oxynitride”, see para 72). Thus, it would have been obvious that the “1st”, “2nd”, and “INS” layers comprise the claimed “a first dielectric layer”, “a second dielectric layer,” and “an insulating layer”.
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7. The semiconductor structure of claim 4, wherein the first work function layer has a portion between the second work function layer and the insulating layer (see Fig. 2).
8. The semiconductor structure of claim 4, wherein the first work function layer has a portion between the second work function layer and the second dielectric layer (see Fig. 2).
9. The semiconductor structure of claim 4, wherein the first work function layer has a portion between the second work function layer and the first dielectric layer (see Fig. 2).
It has been established that “the [obviousness] analysis need not seek out precise teachings directed to the specific subject matter of the challenged claim” because the Office or “a court can take account of the inferences and creative steps that a person of ordinary skill in the art would employ.” KSR Int’ Co. v. Teleflex Inc., 550 U.S. 398, 418 (2007). It is also well settled that a reference stands for all of the specific teachings thereof as well as the inferences one of ordinary skill in the art would have reasonably been expected to draw therefrom. See In re Fritch, 972 F.2d 1260, 1264-65 (Fed. Cir. 1992).
Allowable Subject Matter
Claim(s) 5-6 and 10-13 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art does not explicitly teach, or reasonably suggest as obvious to one of ordinary skill in the art, an invention having all of the limitations of claims 5, 6, or 10, including:
5. The semiconductor structure of claim 4, wherein the top surface of the second work function layer and the top surface of the first work function layer are higher than a top surface of the second dielectric layer.
6. The semiconductor structure of claim 4, wherein the gate dielectric layer extends to a sidewall of the insulating layer sequentially along a sidewall of the first dielectric layer and a sidewall of the second dielectric layer.
10. The semiconductor structure of claim 4, wherein the array area of the substrate has a trench, and the second dielectric layer extends into the trench of the array area of the substrate.
The other claims each depend from one of these claims, and each would be allowable for the same reasons as the claim from which it depends.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Conclusion / Prior Art
The prior art made of record, because it is considered pertinent to applicant's disclosure, but which is not relied upon specifically in the rejections above, is listed on the Notice of References Cited.
Conclusion / Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Kevin Parendo who can be contacted by phone at (571) 270-5030 or by direct fax at (571) 270-6030. The examiner can normally be reached Monday-Friday from 9 am to 4 pm ET.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Billy Kraig, can be reached at (571) 272-8660. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Kevin Parendo/Primary Examiner, Art Unit 2896
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