DETAILED ACTION
This Office action is in response to the reply filed 10 October 2025. Claims 4-23 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 10 October 2025 have been fully considered; Applicant has asserted that US 2018/0226375 A1 to Enquist et al. is not prior art at least under 35 U.S.C. §§ 102(b)(2)(A) and 102 (b)(2)(C). (Remarks, p. 5.)
As to 35 U.S.C. § 102(b)(2)(A), Applicant’s statement of the presence of common inventor Katkar is insufficient to establish this exception. No affidavit or declaration of attribution under 37 CFR 1.130 has been filed, and Applicant has not established that common inventor Katkar is responsible for all of the subject matter relied upon. Thus, Enquist is not excepted under 35 U.S.C. § 102(b)(2)(A). However, in view of Applicant’s statement of common ownership/assignment not later than the effective filing date of the claimed invention, Enquist is excepted under 35 U.S.C. § 102(b)(2)(C). Therefore, the rejection has been withdrawn. However, in view of the references contained in the IDS filed 13 October 2025, a new ground(s) of rejection is made in view of JP2011054637 A to Inoue.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 4-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by JP2011054637 A to Inoue (citations refer to the English machine translation attached; hereinafter “Inoue”).
Regarding independent claim 4, Inoue (Fig. 2 - annotated version below) discloses a semiconductor element comprising:
a first elongate conductive layer (Fig. 2 below; p. 4, para. 8) embedded in a non-conductive layer 41 (p. 4, para. 8), the first elongate conductive layer having a thickness measured from a bonding side (top side) and a back side (bottom) opposite the bonding side, wherein the thickness varies along a length of the first elongate conductive layer (Fig. 2 - thickness as measured at A varies from thickness as measured at B at a point spaced in length from A); Examiner also notes that since Applicant has not indicated how much the thickness varies along its length, variation that naturally results from manufacturing imperfections would fit within the scope of this limitation);
a second elongate conductive layer (Fig. 2 below; p. 4, para. 8) embedded in the non-conductive layer 41; and
an integrated device 23 (p. 5, 5th para. From bottom), the first and second elongate conductive layers disposed around the integrated device (p. 5, 5th para. from bottom), wherein at least a portion of the non-conductive layer 41 is disposed over the back side (bottom) of the first elongate conductive layer (Fig. 2).
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Regarding claim 5, Inoue (Fig. 2) discloses the semiconductor element of claim 4, wherein the first or second elongate conductive layer comprises a plurality of elongate conductive layers (p. 5, 5th para. from bottom).
Regarding claim 6, Inoue (Fig. 2) discloses the semiconductor element of claim 4, wherein a width of a portion of the non-conductive layer 41 disposed between the first and second elongate conductive layers is less than 5 times a width of one of the first and second elongate conductive layers (Fig. 2).
Regarding independent claim 7, Inoue (Fig. 2 - annotated version above) discloses a semiconductor element 21 (p. 4, para. 8), comprising:
an integrated device 23 (p. 5, 5th para. From bottom);
a non-conductive feature 41/51 (p. 4, paras. 8, 12) comprising a trench (Fig. 2 - “first elongate conductive layer” disposed therein) extending at least partially around the integrated device (p. 5, 5th para. from bottom), wherein the integrated device 23 is disposed in or on the semiconductor element, and wherein the trench comprises a first depth at a first location (Fig. 2 - first depth measured at location A), and a second depth at a second location spaced from the first location along a length of the trench (Fig. 2 - second depth measured at location B, spaced along a length of the trench), the first depth being greater than the second depth (Examiner also notes that due to variation that would naturally result from manufacturing imperfections the trench depth would vary, and as such would have first and second locations that would also read upon the above recited limitations);
a conductive material (Fig. 2 - “first elongate conductive layer”, p. 4, para. 8) disposed in the trench; and
a bonding surface (Fig. 2 - top surface of “first elongate conductive layer” and 41/51), wherein the bonding surface comprises a surface of the non-conductive feature 41/51 and a surface of the conductive material (Fig. 2).
Regarding claim 8, Inoue (Fig. 2 - annotated above) discloses the semiconductor element of Claim 7, wherein the second depth (Fig. 2 - second depth measured at location B, spaced along a length of the trench from A) is in a range between 10% and 90% of the first depth (Fig. 2 - first depth measured at location A).
Regarding claim 9, Inoue (Fig. 2 - annotated above) discloses the semiconductor element of Claim 7, wherein the second depth (Fig. 2 - second depth measured at location B, spaced along a length of the trench from A) is in a range between 20% and 80% of the first depth (Fig. 2 - first depth measured at location A).
Regarding claim 10, Inoue (Fig. 2 - annotated above) discloses the semiconductor element of Claim 7, wherein the trench (Fig. 2 - “first elongate conductive layer” disposed therein) extends completely around the integrated device 23 to laterally enclose the integrated device (p. 5, 5th para. from bottom).
Regarding claim 11, Inoue (Fig. 2 - annotated above) discloses the semiconductor element of Claim 10, wherein the trench (Fig. 2 - “first elongate conductive layer” disposed therein) comprises an annular or closed profile (p. 5, 5th para. from bottom).
Regarding claim 12, Inoue (Fig. 2 - annotated above) discloses the semiconductor element of Claim 7, wherein the conductive material (Fig. 2 - “first elongate conductive layer”) in the trench comprises a continuous ring (p. 5, 5th para. from bottom).
Regarding claim 13, Inoue (Fig. 2 - annotated above) discloses the semiconductor element of Claim 7, further comprising a barrier layer (p. 5, para. 3 - “insulating film formed at least on the side surface of the through groove 25 penetrating the insulating film 41”), wherein the conductive material is disposed over the barrier layer (Fig. 2).
Regarding claim 14, Inoue (Fig. 2 - annotated above) discloses the semiconductor element of Claim 7, wherein the bonding surface (Fig. 2 - top surface of “first elongate conductive layer” and 41/51) comprises a planarized surface (Fig. 2 - bonding surface is planar). The limitation "planarized surface" is merely a product-by-process limitation that does not structurally distinguish the claimed invention over the prior art. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966.
Regarding claim 15, Inoue (Fig. 2 - annotated above) discloses the semiconductor element of Claim 7, wherein the conductive material (Fig. 2 - “first elongate conductive layer”) in the trench defines an elongate conductive feature (Fig. 2 - “first elongate conductive layer”; p. 4, para. 8) that includes a first thickness and a second thickness, a difference between the first thickness and the second thickness corresponding to a difference between the first depth and the second depth (Fig. 2 - first depth measured at location A, second depth measured at location B, spaced along a length of the trench; additionally, Examiner notes that due to variation that would naturally result from manufacturing imperfections the trench depth would vary, conductive material formed therein would also reflect said variation in thickness and would fit within the scope of this limitation).
Regarding claim 16, Inoue (Fig. 2 - annotated above) discloses a bonded structure, comprising: the semiconductor element 21 of Claim 7; and a second element 11 (p. 4, para. 7), wherein the semiconductor element is bonded to the second element (Fig. 2).
Regarding claim 17, Inoue (Fig. 2 - annotated above) discloses the bonded structure of Claim 16, wherein
the second element 11 comprises a second bonding surface having a surface of a second non-conductive feature 31 (p. 4, para. 7) and a surface of a second conductive material 32 (p. 4, para. 7), the bonding surface and the second bonding surfaced directly bonded to on another such that the surfaces of the non-conductive feature 41/51 and the second non-conductive feature 31 are directly bonded to one another and the surfaces of the conductive material (Fig. 2 - “first elongate conductive layer”) and the second conductive material 32 are directly bonded to one another (Fig. 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 18-23 are rejected under 35 U.S.C. 103 as being unpatentable over Inoue in view of US 2008/0157284 A1 to Chang et al. (hereinafter “Chang”).
Regarding independent claim 18, Inoue (Fig. 2 - annotated above) discloses a semiconductor element 21 (p. 4, para. 8) comprising:
a trench (Fig. 2 - “first elongate conductive layer” disposed therein) located in a non-conductive feature 41/51 (p. 4, paras. 8, 12), wherein the trench extends at least partially around an integrated device 23 (p. 5, 5th para. from bottom) disposed in or on the semiconductor element (Fig. 2);
a conductive material (Fig. 2 - “first elongate conductive layer”, p. 4, para. 8) disposed in the trench; and a bonding surface (Fig. 2 - top surface of “first elongate conductive layer” and 41/51) comprising a surface of the non-conductive feature 41/51 and a surface of the conductive material (Fig. 2).
Inoue fails to expressly disclose: wherein the conductive material comprises a cavity; a dielectric material disposed in the cavity; and a bonding surface comprising a surface of the dielectric material. In the same field of endeavor, Chang (Fig. 2A) discloses a trench (226 disposed therein) located in a non-conductive feature 256 (¶ 0034), a conductive material 226 (¶ 0033) disposed in the trench, wherein the conductive material 226 comprises a cavity (portion of 256/266 disposed therein); a dielectric material 256/266 disposed in the cavity (Fig. 2A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the shape of the conductive material and trench of Inoue with the teachings of Chang for the purpose of providing a guard ring structure that provides protection from environmental stressors (¶ 0033), the combination of Inoue and Chang thus teaching the bonding surface comprising a surface of the dielectric material.
Regarding claim 19, Inoue (Fig. 2 - annotated above) and Chang disclose the semiconductor element of Claim 18, wherein the trench (Inoue, Fig. 2 - “first elongate conductive layer” disposed therein) comprises an annularly continuous profile around the integrated device (Inoue, p. 5, 5th para. from bottom).
Regarding claim 20, Inoue and Chang disclose the semiconductor element of Claim 18, wherein the conductive material (Inoue, Fig. 2 - “first elongate conductive layer”, p. 4, para. 8) comprises a metal, and wherein the metal fills the trench (Inoue, p. 5, para. 3).
Regarding claim 21, Inoue and Chang discloses the semiconductor element of Claim 18, wherein the conductive material comprises a second cavity (Chang, Fig. 2A, portion of 256/266 disposed therein), wherein the second cavity is spaced from the cavity along a length of the trench (Chang, Fig. 2A).
Regarding claim 22, Inoue and Chang disclose the semiconductor element of Claim 18, wherein the non-conductive feature 256/266 (Chang, Fig. 2A) and the dielectric material 256/266 comprise a same material (Chang, Fig. 2A).
Regarding claim 23, Inoue (Fig. 2) and Chang disclose a bonded structure, comprising: the semiconductor element 21 of Claim 18; and a second element 11 (Inoue, p. 4, para. 8), wherein the semiconductor element is hybrid bonded to the second element (Inoue, Fig. 2). The limitation "hybrid bonded" is merely a product-by-process limitation that does not structurally distinguish the claimed invention over the prior art. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 227 USPQ 964, 966.
Conclusion
Applicant's submission of an information disclosure statement under 37 CFR 1.97(c) with the timing fee set forth in 37 CFR 1.17(p) on 13 October 2025 prompted the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 609.04(b). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET.
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CANDICE Y. CHAN
Examiner
Art Unit 2813
6 February 2026
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813